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Diffstat (limited to 'os/hal/platforms/STM32/pwm_lld.c')
-rw-r--r--os/hal/platforms/STM32/pwm_lld.c42
1 files changed, 18 insertions, 24 deletions
diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index efe215458..901474091 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -348,9 +348,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
/* Clock activation and timer reset.*/
#if STM32_PWM_USE_TIM1
if (&PWMD1 == pwmp) {
- RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
- RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;
- RCC->APB2RSTR = 0;
+ rccEnableTIM1(FALSE);
+ rccResetTIM1();
NVICEnableVector(TIM1_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
NVICEnableVector(TIM1_CC_IRQn,
@@ -360,9 +359,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif
#if STM32_PWM_USE_TIM2
if (&PWMD2 == pwmp) {
- RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
- RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;
- RCC->APB1RSTR = 0;
+ rccEnableTIM2(FALSE);
+ rccResetTIM2();
NVICEnableVector(TIM2_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
clock = STM32_TIMCLK1;
@@ -370,9 +368,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif
#if STM32_PWM_USE_TIM3
if (&PWMD3 == pwmp) {
- RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
- RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;
- RCC->APB1RSTR = 0;
+ rccEnableTIM3(FALSE);
+ rccResetTIM3();
NVICEnableVector(TIM3_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
clock = STM32_TIMCLK1;
@@ -380,9 +377,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif
#if STM32_PWM_USE_TIM4
if (&PWMD4 == pwmp) {
- RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
- RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;
- RCC->APB1RSTR = 0;
+ rccEnableTIM4(FALSE);
+ rccResetTIM4();
NVICEnableVector(TIM4_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
clock = STM32_TIMCLK1;
@@ -391,9 +387,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#if STM32_PWM_USE_TIM5
if (&PWMD5 == pwmp) {
- RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
- RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;
- RCC->APB1RSTR = 0;
+ rccEnableTIM5(FALSE);
+ rccResetTIM5();
NVICEnableVector(TIM5_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
clock = STM32_TIMCLK1;
@@ -401,9 +396,8 @@ void pwm_lld_start(PWMDriver *pwmp) {
#endif
#if STM32_PWM_USE_TIM8
if (&PWMD8 == pwmp) {
- RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
- RCC->APB2RSTR = RCC_APB2RSTR_TIM8RST;
- RCC->APB2RSTR = 0;
+ rccEnableTIM8(FALSE);
+ rccResetTIM8();
NVICEnableVector(TIM8_UP_IRQn,
CORTEX_PRIORITY_MASK(STM32_PWM_TIM8_IRQ_PRIORITY));
NVICEnableVector(TIM8_CC_IRQn,
@@ -552,38 +546,38 @@ void pwm_lld_stop(PWMDriver *pwmp) {
if (&PWMD1 == pwmp) {
NVICDisableVector(TIM1_UP_IRQn);
NVICDisableVector(TIM1_CC_IRQn);
- RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;
+ rccDisableTIM1(FALSE);
}
#endif
#if STM32_PWM_USE_TIM2
if (&PWMD2 == pwmp) {
NVICDisableVector(TIM2_IRQn);
- RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
+ rccDisableTIM2(FALSE);
}
#endif
#if STM32_PWM_USE_TIM3
if (&PWMD3 == pwmp) {
NVICDisableVector(TIM3_IRQn);
- RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;
+ rccDisableTIM3(FALSE);
}
#endif
#if STM32_PWM_USE_TIM4
if (&PWMD4 == pwmp) {
NVICDisableVector(TIM4_IRQn);
- RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;
+ rccDisableTIM4(FALSE);
}
#endif
#if STM32_PWM_USE_TIM5
if (&PWMD5 == pwmp) {
NVICDisableVector(TIM5_IRQn);
- RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
+ rccDisableTIM5(FALSE);
}
#endif
#if STM32_PWM_USE_TIM8
if (&PWMD8 == pwmp) {
NVICDisableVector(TIM8_UP_IRQn);
NVICDisableVector(TIM8_CC_IRQn);
- RCC->APB2ENR &= ~RCC_APB2ENR_TIM8EN;
+ rccDisableTIM8(FALSE);
}
#endif
}