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-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @defgroup STM32_DRIVERS STM32 Drivers
- * @details This section describes all the supported drivers on the STM32
- * platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup STM32_HAL STM32 Initialization Support
- * @details The STM32 HAL support is responsible for system initialization.
- *
- * @section stm32_hal_1 Supported HW resources
- * - PLL1.
- * - PLL2 (where present).
- * - RCC.
- * - Flash.
- * .
- * @section stm32_hal_2 STM32 HAL driver implementation features
- * - PLLs startup and stabilization.
- * - Clock tree initialization.
- * - Clock source selection.
- * - Flash wait states initialization based on the selected clock options.
- * - SYSTICK initialization based on current clock and kernel required rate.
- * - DMA support initialization.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_ADC STM32 ADC Support
- * @details The STM32 ADC driver supports the ADC peripherals using DMA
- * channels for maximum performance.
- *
- * @section stm32_adc_1 Supported HW resources
- * - ADC1.
- * - DMA1.
- * .
- * @section stm32_adc_2 STM32 ADC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Streaming conversion using DMA for maximum performance.
- * - Programmable ADC interrupt priority level.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_CAN STM32 CAN Support
- * @details The STM32 CAN driver uses the CAN peripherals.
- *
- * @section stm32_can_1 Supported HW resources
- * - bxCAN1.
- * .
- * @section stm32_can_2 STM32 CAN driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Support for bxCAN sleep mode.
- * - Programmable bxCAN interrupts priority level.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_DMA STM32 DMA Support
- * @details This DMA helper driver is used by the other drivers in order to
- * access the shared DMA resources in a consistent way.
- *
- * @section stm32_dma_1 Supported HW resources
- * The DMA driver can support any of the following hardware resources:
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32_dma_2 STM32 DMA driver implementation features
- * - Automatic DMA clock stop when not in use by other drivers.
- * - Exports helper functions/macros to the other drivers that share the
- * DMA resource.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_GPT STM32 GPT Support
- * @details The STM32 GPT driver uses the TIMx peripherals.
- *
- * @section stm32_gpt_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32_gpt_2 STM32 GPT driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_ICU STM32 ICU Support
- * @details The STM32 ICU driver uses the TIMx peripherals.
- *
- * @section stm32_icu_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32_icu_2 STM32 ICU driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_PAL STM32 PAL Support
- * @details The STM32 PAL driver uses the GPIO peripherals.
- *
- * @section stm32_pal_1 Supported HW resources
- * - AFIO.
- * - GPIOA.
- * - GPIOB.
- * - GPIOC.
- * - GPIOD.
- * - GPIOE (where present).
- * - GPIOF (where present).
- * - GPIOG (where present).
- * .
- * @section stm32_pal_2 STM32 PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 16 bits wide ports.
- * - Atomic set/reset functions.
- * - Atomic set+reset function (atomic bus operations).
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section stm32_pal_3 Supported PAL setup modes
- * The STM32 PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_INPUT_PULLDOWN.
- * - @p PAL_MODE_INPUT_ANALOG.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * - @p PAL_MODE_STM32_ALTERNATE_PUSHPULL (non standard).
- * - @p PAL_MODE_STM32_ALTERNATE_OPENDRAIN (non standard).
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section stm32_pal_4 Suboptimal behavior
- * The STM32 GPIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * - Writing on pads/groups/ports programmed as input with pull-up/down
- * resistor can change the resistor setting because the output latch is
- * used for resistor selection.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_PWM STM32 PWM Support
- * @details The STM32 PWM driver uses the TIMx peripherals.
- *
- * @section stm32_pwm_1 Supported HW resources
- * - TIM1.
- * - TIM2.
- * - TIM3.
- * - TIM4.
- * - TIM5.
- * .
- * @section stm32_pwm_2 STM32 PWM driver implementation features
- * - Each timer can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Four independent PWM channels per timer.
- * - Programmable TIMx interrupts priority level.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_SDC STM32 SDC Support
- * @details The STM32 SDC driver uses the SDIO peripheral.
- *
- * @section stm32_sdc_1 Supported HW resources
- * - SDIO.
- * - DMA2.
- * .
- * @section stm32_sdc_2 STM32 SDC driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_SERIAL STM32 Serial Support
- * @details The STM32 Serial driver uses the USART/UART peripherals in a
- * buffered, interrupt driven, implementation.
- *
- * @section stm32_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3 (where present).
- * - UART4 (where present).
- * - UART5 (where present).
- * .
- * @section stm32_serial_2 STM32 Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each UART/USART.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_SPI STM32 SPI Support
- * @details The SPI driver supports the STM32 SPI peripherals using DMA
- * channels for maximum performance.
- *
- * @section stm32_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * - SPI3 (where present).
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32_spi_2 STM32 SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_UART STM32 UART Support
- * @details The UART driver supports the STM32 USART peripherals using DMA
- * channels for maximum performance.
- *
- * @section stm32_uart_1 Supported HW resources
- * The UART driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - USART3 (where present).
- * - UART4 (where present).
- * - DMA1.
- * - DMA2 (where present).
- * .
- * @section stm32_uart_2 STM32 UART driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each UART/USART can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each UART/USART.
- * - DMA is used for receiving and transmitting.
- * - Programmable DMA bus priority for each DMA channel.
- * - Programmable DMA interrupt priority for each DMA channel.
- * - Programmable DMA error hook.
- * .
- * @ingroup STM32_DRIVERS
- */
-
-/**
- * @defgroup STM32_USB STM32 USB Support
- * @details The USB driver supports the STM32 USB peripheral.
- *
- * @section stm32_usb_1 Supported HW resources
- * The USB driver can support any of the following hardware resources:
- * - USB.
- * .
- * @section stm32_usb_2 STM32 USB driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Programmable interrupt priority levels.
- * - Each endpoint programmable in Control, Bulk and Interrupt modes.
- * .
- * @ingroup STM32_DRIVERS
- */