diff options
Diffstat (limited to 'os/hal/boards')
137 files changed, 19713 insertions, 0 deletions
diff --git a/os/hal/boards/ARDUINO_MEGA/board.c b/os/hal/boards/ARDUINO_MEGA/board.c new file mode 100644 index 000000000..a33d693ad --- /dev/null +++ b/os/hal/boards/ARDUINO_MEGA/board.c @@ -0,0 +1,102 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+ {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+ {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+ {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+ {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+ {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+ {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+ {VAL_PORTG, VAL_DDRG},
+#endif
+#if defined(PORTH)
+ {VAL_PORTH, VAL_DDRH},
+#endif
+#if defined(PORTJ)
+ {VAL_PORTJ, VAL_DDRJ},
+#endif
+#if defined(PORTK)
+ {VAL_PORTK, VAL_DDRK},
+#endif
+#if defined(PORTL)
+ {VAL_PORTL, VAL_DDRL},
+#endif
+};
+#endif /* HAL_USE_PAL */
+
+/**
+ * @brief Timer0 interrupt handler.
+ */
+CH_IRQ_HANDLER(TIMER0_COMPA_vect) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * External interrupts setup, all disabled initially.
+ */
+ EICRA = 0x00;
+ EICRB = 0x00;
+ EIMSK = 0x00;
+
+ /*
+ * Timer 0 setup.
+ */
+ TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */
+ (0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */
+ (0 << COM0B1) | (0 << COM0B0); /* OC0B disabled. */
+ TCCR0B = (0 << WGM02) | /* CTC mode. */
+ (0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */
+ OCR0A = F_CPU / 64 / CH_FREQUENCY - 1;
+ TCNT0 = 0; /* Reset counter. */
+ TIFR0 = (1 << OCF0A); /* Reset pending. */
+ TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */
+}
diff --git a/os/hal/boards/ARDUINO_MEGA/board.h b/os/hal/boards/ARDUINO_MEGA/board.h new file mode 100644 index 000000000..9dc3b09e4 --- /dev/null +++ b/os/hal/boards/ARDUINO_MEGA/board.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Arduino Mega board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ARDUINO_MEGA
+#define BOARD_NAME "Arduino Mega"
+
+/* All inputs with pull-ups */
+#define VAL_DDRA 0x00
+#define VAL_PORTA 0xFF
+
+/* All inputs except PB7 which has a LED connected */
+#define VAL_DDRB 0x80
+#define VAL_PORTB 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRC 0x00
+#define VAL_PORTC 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRD 0x00
+#define VAL_PORTD 0xFF
+
+/* All inputs except PE1 (Serial TX0) */
+#define VAL_DDRE 0x02
+#define VAL_PORTE 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRF 0x00
+#define VAL_PORTF 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRG 0x00
+#define VAL_PORTG 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRH 0x00
+#define VAL_PORTH 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRJ 0x00
+#define VAL_PORTJ 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRK 0x00
+#define VAL_PORTK 0xFF
+
+/* All inputs with pull-ups */
+#define VAL_DDRL 0x00
+#define VAL_PORTL 0xFF
+
+#define PORTB_LED1 7
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ARDUINO_MEGA/board.mk b/os/hal/boards/ARDUINO_MEGA/board.mk new file mode 100644 index 000000000..8e7f1117e --- /dev/null +++ b/os/hal/boards/ARDUINO_MEGA/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ARDUINO_MEGA/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ARDUINO_MEGA
diff --git a/os/hal/boards/EA_LPCXPRESSO_11C24/board.c b/os/hal/boards/EA_LPCXPRESSO_11C24/board.c new file mode 100644 index 000000000..0e00ff2a3 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_11C24/board.c @@ -0,0 +1,54 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ LPC11C24 EA Board support - Copyright (C) 2013 mike brown
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ lpc111x_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Extra, board-specific, initializations.
+ */
+ LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_11C24/board.h b/os/hal/boards/EA_LPCXPRESSO_11C24/board.h new file mode 100644 index 000000000..b8de6f790 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_11C24/board.h @@ -0,0 +1,82 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ LPC11C24 EA Board support - Copyright (C) 2013 mike brown
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso LPC11C24
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC11C24
+#define BOARD_NAME "Embedded Artists LPCXpresso LPC11C24"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_LED)
+#define VAL_GPIO0DATA 0x00000000
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR 0x00000000
+#define VAL_GPIO1DATA 0x00000000
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR 0x00000000
+#define VAL_GPIO2DATA 0x00000000
+
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR 0x00000000
+#define VAL_GPIO3DATA 0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW_ISP 1
+#define GPIO0_LED 7
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk b/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk new file mode 100644 index 000000000..d60e6ea6d --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_11C24/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_11C24
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c new file mode 100644 index 000000000..a0af7d697 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c @@ -0,0 +1,59 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ lpc111x_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Extra, board-specific, initializations.
+ * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+ * you must comment that line first.
+ */
+ LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */
+ LPC_IOCON->R_PIO1_2 = 0xC1; /* Disables pull-up on LED3B output
+ and makes it GPIO1_2. */
+ LPC_IOCON->PIO1_9 = 0xC0; /* Disables pull-up on LED3R output.*/
+ LPC_IOCON->PIO1_10 = 0xC0; /* Disables pull-up on LED3G output.*/
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h new file mode 100644 index 000000000..c27830d28 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC1114
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1114"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_OLEDSEL) | \
+ PAL_PORT_BIT(GPIO0_LED2)
+#define VAL_GPIO0DATA PAL_PORT_BIT(GPIO0_OLEDSEL) | \
+ PAL_PORT_BIT(GPIO0_LED2)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED3B) | \
+ PAL_PORT_BIT(GPIO1_LED3R) | \
+ PAL_PORT_BIT(GPIO1_LED3G) | \
+ PAL_PORT_BIT(GPIO1_SPI0SEL)
+#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_LED3B) | \
+ PAL_PORT_BIT(GPIO1_LED3R) | \
+ PAL_PORT_BIT(GPIO1_LED3G) | \
+ PAL_PORT_BIT(GPIO1_SPI0SEL)
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR 0x00000000
+#define VAL_GPIO2DATA 0x00000000
+
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR 0x00000000
+#define VAL_GPIO3DATA 0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3 1
+#define GPIO0_OLEDSEL 2
+#define GPIO0_LED2 7
+
+#define GPIO1_LED3B 2
+#define GPIO1_SW4 4
+#define GPIO1_LED3R 9
+#define GPIO1_LED3G 10
+#define GPIO1_SPI0SEL 11
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk new file mode 100644 index 000000000..affca2d05 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1114/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1114
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c new file mode 100644 index 000000000..117e78c0e --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c @@ -0,0 +1,66 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ lpc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Extra, board-specific, initializations.
+ * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+ * you must comment that line first.
+ */
+ LPC_IOCON->PIO0_7 = 0x80; /* Disables pull-up on LED2 output. */
+ LPC_IOCON->TRST_PIO0_14 = 0x81; /* Disables pull-up on LED3B output
+ and makes it GPIO1_2. */
+ LPC_IOCON->PIO0_21 = 0x80; /* Disables pull-up on LED3R output.*/
+ LPC_IOCON->PIO0_22 = 0x80; /* Disables pull-up on LED3G output.*/
+
+ /* SSP0 mapping.*/
+ LPC_IOCON->PIO1_29 = 0x81; /* SCK0 without resistors. */
+ LPC_IOCON->PIO0_8 = 0x81; /* MISO0 without resistors. */
+ LPC_IOCON->PIO0_9 = 0x81; /* MOSI0 without resistors. */
+
+ /* USART mapping.*/
+ LPC_IOCON->PIO0_18 = 0x81; /* RDX without resistors. */
+ LPC_IOCON->PIO0_19 = 0x81; /* TDX without resistors. */
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h new file mode 100644 index 000000000..dac011460 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h @@ -0,0 +1,88 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC11U14
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC11U14"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_OLEDSEL) | \
+ PAL_PORT_BIT(GPIO0_USB_DPCTL) | \
+ PAL_PORT_BIT(GPIO0_LED2) | \
+ PAL_PORT_BIT(GPIO0_LED3B) | \
+ PAL_PORT_BIT(GPIO0_LED3R) | \
+ PAL_PORT_BIT(GPIO0_LED3G) | \
+ PAL_PORT_BIT(GPIO0_SPI0SEL)
+#define VAL_GPIO0DATA PAL_PORT_BIT(GPIO0_OLEDSEL) | \
+ PAL_PORT_BIT(GPIO0_LED2) | \
+ PAL_PORT_BIT(GPIO0_LED3B) | \
+ PAL_PORT_BIT(GPIO0_LED3R) | \
+ PAL_PORT_BIT(GPIO0_LED3G) | \
+ PAL_PORT_BIT(GPIO0_SPI0SEL)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR 0x00000000
+#define VAL_GPIO1DATA 0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3 1
+#define GPIO0_OLEDSEL 2
+#define GPIO0_USB_VBUS 3
+#define GPIO0_USB_DPCTL 6
+#define GPIO0_LED2 7
+#define GPIO0_SW4 16
+#define GPIO0_LED3B 14
+#define GPIO0_LED3R 21
+#define GPIO0_LED3G 22
+#define GPIO0_SPI0SEL 23
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk new file mode 100644 index 000000000..1c5d132d2 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_11U14/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_11U14
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c new file mode 100644 index 000000000..d25d93d20 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c @@ -0,0 +1,59 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ LPC13xx_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Extra, board-specific, initializations.
+ * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+ * you must comment that line first.
+ */
+ LPC_IOCON->PIO0_7 = 0xC0; /* Disables pull-up on LED2 output. */
+ LPC_IOCON->R_PIO1_2 = 0xC1; /* Disables pull-up on LED3B output
+ and makes it GPIO1_2. */
+ LPC_IOCON->PIO1_9 = 0xC0; /* Disables pull-up on LED3R output.*/
+ LPC_IOCON->PIO1_10 = 0xC0; /* Disables pull-up on LED3G output.*/
+}
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h new file mode 100644 index 000000000..b5ad73dbd --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h @@ -0,0 +1,91 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1343 daughter
+ * board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC1343
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1343"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_OLEDSEL) | \
+ PAL_PORT_BIT(GPIO0_LED2)
+#define VAL_GPIO0DATA PAL_PORT_BIT(GPIO0_OLEDSEL) | \
+ PAL_PORT_BIT(GPIO0_LED2)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED3B) | \
+ PAL_PORT_BIT(GPIO1_LED3R) | \
+ PAL_PORT_BIT(GPIO1_LED3G) | \
+ PAL_PORT_BIT(GPIO1_SPI0SEL)
+#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_LED3B) | \
+ PAL_PORT_BIT(GPIO1_LED3R) | \
+ PAL_PORT_BIT(GPIO1_LED3G) | \
+ PAL_PORT_BIT(GPIO1_SPI0SEL)
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR 0x00000000
+#define VAL_GPIO2DATA 0x00000000
+
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR 0x00000000
+#define VAL_GPIO3DATA 0x00000000
+
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3 1
+#define GPIO0_OLEDSEL 2
+#define GPIO0_LED2 7
+
+#define GPIO1_LED3B 2
+#define GPIO1_SW4 4
+#define GPIO1_LED3R 9
+#define GPIO1_LED3G 10
+#define GPIO1_SPI0SEL 11
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk new file mode 100644 index 000000000..da59e98c4 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1343/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_BB_1343
diff --git a/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c new file mode 100644 index 000000000..1f1952dbf --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c @@ -0,0 +1,136 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {VAL_GPIO0DATA, VAL_GPIO0DIR};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void){
+
+ lpc8xx_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void){
+
+ /* Enable clocks to IOCON & SWM */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7));
+
+#if defined VAL_PIO0_0
+ LPC_IOCON->PIO0_0 = PIN_RSVD|VAL_PIO0_0;
+#endif
+#if defined VAL_PIO0_1
+ LPC_IOCON->PIO0_1 = PIN_RSVD|VAL_PIO0_1;
+#endif
+#if defined VAL_PIO0_2
+ LPC_IOCON->PIO0_2 = PIN_RSVD|VAL_PIO0_2;
+#endif
+#if defined VAL_PIO0_3
+ LPC_IOCON->PIO0_3 = PIN_RSVD|VAL_PIO0_3;
+#endif
+#if defined VAL_PIO0_4
+ LPC_IOCON->PIO0_4 = PIN_RSVD|VAL_PIO0_4;
+#endif
+#if defined VAL_PIO0_5
+ LPC_IOCON->PIO0_5 = PIN_RSVD|VAL_PIO0_5;
+#endif
+#if defined VAL_PIO0_6
+ LPC_IOCON->PIO0_6 = PIN_RSVD|VAL_PIO0_6;
+#endif
+#if defined VAL_PIO0_7
+ LPC_IOCON->PIO0_7 = PIN_RSVD|VAL_PIO0_7;
+#endif
+#if defined VAL_PIO0_8
+ LPC_IOCON->PIO0_8 = PIN_RSVD|VAL_PIO0_8;
+#endif
+#if defined VAL_PIO0_9
+ LPC_IOCON->PIO0_9 = PIN_RSVD|VAL_PIO0_9;
+#endif
+#if defined VAL_PIO0_10
+ LPC_IOCON->PIO0_10 = PIN_RSVD|VAL_PIO0_10;
+#endif
+#if defined VAL_PIO0_11
+ LPC_IOCON->PIO0_11 = PIN_RSVD|VAL_PIO0_11;
+#endif
+#if defined VAL_PIO0_12
+ LPC_IOCON->PIO0_12 = PIN_RSVD|VAL_PIO0_12;
+#endif
+#if defined VAL_PIO0_13
+ LPC_IOCON->PIO0_13 = PIN_RSVD|VAL_PIO0_13;
+#endif
+#if defined VAL_PIO0_14
+ LPC_IOCON->PIO0_14 = PIN_RSVD|VAL_PIO0_14;
+#endif
+#if defined VAL_PIO0_15
+ LPC_IOCON->PIO0_15 = PIN_RSVD|VAL_PIO0_15;
+#endif
+#if defined VAL_PIO0_16
+ LPC_IOCON->PIO0_16 = PIN_RSVD|VAL_PIO0_16;
+#endif
+#if defined VAL_PIO0_17
+ LPC_IOCON->PIO0_17 = PIN_RSVD|VAL_PIO0_17;
+#endif
+
+
+#if defined VAL_PINASSIGN0
+ LPC_SWM->PINASSIGN0 = VAL_PINASSIGN0;
+#endif
+#if defined VAL_PINASSIGN1
+ LPC_SWM->PINASSIGN1 = VAL_PINASSIGN1;
+#endif
+#if defined VAL_PINASSIGN2
+ LPC_SWM->PINASSIGN2 = VAL_PINASSIGN2;
+#endif
+#if defined VAL_PINASSIGN3
+ LPC_SWM->PINASSIGN3 = VAL_PINASSIGN3;
+#endif
+#if defined VAL_PINASSIGN4
+ LPC_SWM->PINASSIGN4 = VAL_PINASSIGN4;
+#endif
+#if defined VAL_PINASSIGN5
+ LPC_SWM->PINASSIGN5 = VAL_PINASSIGN5;
+#endif
+#if defined VAL_PINASSIGN6
+ LPC_SWM->PINASSIGN6 = VAL_PINASSIGN6;
+#endif
+#if defined VAL_PINASSIGN7
+ LPC_SWM->PINASSIGN7 = VAL_PINASSIGN7;
+#endif
+#if defined VAL_PINASSIGN8
+ LPC_SWM->PINASSIGN8 = VAL_PINASSIGN8;
+#endif
+
+ /* Disable clocks to IOCON & SWM */
+ LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7));
+
+}
+
+
diff --git a/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h new file mode 100644 index 000000000..0a1618292 --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h @@ -0,0 +1,125 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Embedded Artists LPCXpresso LPC812 board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_LPC812
+#define BOARD_NAME "Embedded Artists LPCXpresso LPC812"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the LPC8xx Reference Manual for details.
+ */
+/* Pull-up/down */
+#define PIN_MODE_NOPULL (0<<3)
+#define PIN_MODE_PULLDOWN (1<<3)
+#define PIN_MODE_PULLUP (2<<3)
+#define PIN_MODE_REPEATER (3<<3)
+/* Hysteresis */
+#define PIN_HYS_EN (1<<5)
+/* Invert Input */
+#define PIN_INV_INPUT (1<<6)
+/* Reserved bits */
+#define PIN_RSVD (1<<7)
+/* I2C Mode */
+#define PIN_I2CMODE_STD (0<<8)
+#define PIN_I2CMODE_STDIO (1<<8)
+#define PIN_I2CMODE_FAST (2<<8)
+/* Open Drain */
+#define PIN_OPEN_DRAIN (1<<10)
+/* Input Filter Sample Clocks */
+#define PIN_SMODE_FILTER(n) ((n)<<11)
+/* Input Filter clock divider */
+#define PIN_CLKDIV_FILTER(n) ((n)<<13)
+
+/*
+ * Pin definitions.
+ */
+#define LED_RED 7
+#define LED_BLUE 16
+#define LED_GREEN 17
+
+
+/*
+ * GPIO 0 initial setup.
+ */
+/*#define VAL_PIO0_0 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_1 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_2 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_3 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_4 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_5 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_6 PIN_MODE_PULLUP*/
+#define VAL_PIO0_7 PIN_MODE_NOPULL
+/*#define VAL_PIO0_8 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_9 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_10 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_11 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_12 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_13 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_14 PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_15 PIN_MODE_PULLUP*/
+#define VAL_PIO0_16 PIN_MODE_NOPULL
+#define VAL_PIO0_17 PIN_MODE_NOPULL
+
+ /* UART0: TXD = P0.4, RXD = P0.0)*/
+#define VAL_PINASSIGN0 ((0xFFFF0000) | (0<<8) | (4))
+/*#define VAL_PINASSIGN1 0xFFFFFFFF*/
+/*#define VAL_PINASSIGN2 0xFFFFFFFF*/
+/*#define VAL_PINASSIGN3 0xFFFFFFFF*/
+/*#define VAL_PINASSIGN4 0xFFFFFFFF*/
+/*#define VAL_PINASSIGN5 0xFFFFFFFF*/
+/*#define VAL_PINASSIGN6 0xFFFFFFFF*/
+/*#define VAL_PINASSIGN7 0xFFFFFFFF*/
+/*#define VAL_PINASSIGN8 0xFFFFFFFF*/
+
+
+#define VAL_GPIO0DIR (PAL_PORT_BIT(LED_RED) | \
+ PAL_PORT_BIT(LED_BLUE) | \
+ PAL_PORT_BIT(LED_GREEN))
+
+#define VAL_GPIO0DATA (PAL_PORT_BIT(LED_RED) | \
+ PAL_PORT_BIT(LED_BLUE) | \
+ PAL_PORT_BIT(LED_GREEN))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk new file mode 100644 index 000000000..de80424bb --- /dev/null +++ b/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_LPC812/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_LPC812
diff --git a/os/hal/boards/MAPLEMINI_STM32_F103/board.c b/os/hal/boards/MAPLEMINI_STM32_F103/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/os/hal/boards/MAPLEMINI_STM32_F103/board.c @@ -0,0 +1,50 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/MAPLEMINI_STM32_F103/board.h b/os/hal/boards/MAPLEMINI_STM32_F103/board.h new file mode 100644 index 000000000..977a54bb7 --- /dev/null +++ b/os/hal/boards/MAPLEMINI_STM32_F103/board.h @@ -0,0 +1,137 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the LeafLabs Maple Mini.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MAPLEMINI_STM32_F103
+#define BOARD_NAME "LeafLabs Maple Mini"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+/* Missing.*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA2 - Alternate output (USART2 TX).
+ * PA3 - Normal input (USART2 RX).
+ * PA9 - Alternate output (USART1 TX).
+ * PA10 - Normal input (USART1 RX).
+ */
+#define VAL_GPIOACRL 0x88884B88 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x888884B8 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB1 - Push Pull output (LED).
+ */
+#define VAL_GPIOBCRL 0x88888838 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x88888888 /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0 - Normal input (XTAL).
+ * PD1 - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */
+#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
+#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/MAPLEMINI_STM32_F103/board.mk b/os/hal/boards/MAPLEMINI_STM32_F103/board.mk new file mode 100644 index 000000000..ab4b30cac --- /dev/null +++ b/os/hal/boards/MAPLEMINI_STM32_F103/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/MAPLEMINI_STM32_F103/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/MAPLEMINI_STM32_F103
diff --git a/os/hal/boards/NGX_BB_LPC11U14/board.c b/os/hal/boards/NGX_BB_LPC11U14/board.c new file mode 100644 index 000000000..3f3c3d726 --- /dev/null +++ b/os/hal/boards/NGX_BB_LPC11U14/board.c @@ -0,0 +1,61 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+__inline void __early_init(void) {
+
+ lpc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+__inline void boardInit(void) {
+
+ /* LCD */
+ LPC_IOCON->TMS_PIO0_12 = 0x91; /* LCD_EN: GPIO - pull-up */
+ LPC_IOCON->TDO_PIO0_13 = 0x81; /* LCD_RW: GPIO - No pull-up */
+ LPC_IOCON->TRST_PIO0_14 = 0x81; /* LCD_RS: GPIO - No pull-up */
+
+ /* USART */
+ LPC_IOCON->PIO0_18 = 0x81; /* RDX: RXD - No pull-up */
+ LPC_IOCON->PIO0_19 = 0x81; /* TDX: TXD - No pull-up */
+
+ /* Test LEDs */
+ LPC_IOCON->PIO0_22 = 0x80; /* LED_TEST1: GPIO - No pull-up */
+ LPC_IOCON->PIO0_23 = 0x80; /* LED_TEST2: GPIO - No pull-up */
+
+}
+
diff --git a/os/hal/boards/NGX_BB_LPC11U14/board.h b/os/hal/boards/NGX_BB_LPC11U14/board.h new file mode 100644 index 000000000..9a59a9c44 --- /dev/null +++ b/os/hal/boards/NGX_BB_LPC11U14/board.h @@ -0,0 +1,125 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for NGX BlueBoard LPC11U14.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_NGX_BB_LPC11U14
+#define BOARD_NAME "NGX BlueBoard LPC11U14"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+/*
+ * Pin definitions.
+ */
+
+/* GPIO Port0 */
+#define BUTTON_ISP_PORT GPIO0
+#define BUTTON_ISP 1
+
+#define LCD_ERD_PORT GPIO0
+#define LCD_ERD 12
+
+#define LCD_RWR_PORT GPIO0
+#define LCD_RWR 13
+
+#define LCD_RS_PORT GPIO0
+#define LCD_RS 14
+
+#define LED_PORT GPIO0
+#define LED_TEST1 22
+#define LED_TEST2 23
+
+/* GPIO Port1 */
+#define LCD_RST_PORT GPIO1
+#define LCD_RST 0
+
+#define LCD_CS_PORT GPIO1
+#define LCD_CS 13
+
+#define LCD_BL_PORT GPIO1
+#define LCD_BL 14
+#define LCD_VCCEN_PORT GPIO1
+#define LCD_VCCEN 14
+
+#define WHEEL_SENSOR_PORT GPIO0
+#define WHEEL_SENSOR 21
+
+#define LCD_DATA_PORT GPIO1
+#define LCD_D0 19
+#define LCD_D1 20
+#define LCD_D2 21
+#define LCD_D3 22
+#define LCD_D4 26
+#define LCD_D5 27
+#define LCD_D6 28
+#define LCD_D7 31
+
+#define LCD_DATA_MASK PAL_PORT_BIT(LCD_D0) | \
+ PAL_PORT_BIT(LCD_D1) | \
+ PAL_PORT_BIT(LCD_D2) | \
+ PAL_PORT_BIT(LCD_D3) | \
+ PAL_PORT_BIT(LCD_D4) | \
+ PAL_PORT_BIT(LCD_D5) | \
+ PAL_PORT_BIT(LCD_D6) | \
+ PAL_PORT_BIT(LCD_D7)
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR PAL_PORT_BIT(LCD_ERD) | \
+ PAL_PORT_BIT(LCD_RWR) | \
+ PAL_PORT_BIT(LCD_RS) | \
+ PAL_PORT_BIT(LED_TEST1) | \
+ PAL_PORT_BIT(LED_TEST2)
+
+#define VAL_GPIO0DATA PAL_PORT_BIT(LCD_ERD) | \
+ PAL_PORT_BIT(LCD_RWR) | \
+ PAL_PORT_BIT(LED_TEST1) | \
+ PAL_PORT_BIT(LED_TEST2)
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR PAL_PORT_BIT(LCD_RST) | \
+ PAL_PORT_BIT(LCD_CS) | \
+ PAL_PORT_BIT(LCD_BL) | \
+ LCD_DATA_MASK
+
+#define VAL_GPIO1DATA 0x00000000
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
diff --git a/os/hal/boards/NGX_BB_LPC11U14/board.mk b/os/hal/boards/NGX_BB_LPC11U14/board.mk new file mode 100644 index 000000000..451d160dd --- /dev/null +++ b/os/hal/boards/NGX_BB_LPC11U14/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/NGX_BB_LPC11U14/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/NGX_BB_LPC11U14
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c new file mode 100644 index 000000000..193217320 --- /dev/null +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c @@ -0,0 +1,83 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
+
+#if HAL_USE_SDC
+/**
+ * @brief Insertion monitor function.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ return !palReadPad(GPIOE, GPIOE_SDIO_DETECT);
+}
+
+/**
+ * @brief Protection detection.
+ * @note Not supported, always not protected.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h new file mode 100644 index 000000000..78ae3bd0e --- /dev/null +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.h @@ -0,0 +1,520 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_NONSTANDARD_STM32F4_BARTHESS1
+#define BOARD_NAME "Hand made STM32F4x board"
+
+/*
+ * Board frequencies.
+ * NOTE: The LSE crystal is not fitted by default on the board.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_USART2_CTS 0 /* xbee */
+#define GPIOA_USART2_RTS 1 /* xbee */
+#define GPIOA_USART2_TX 2 /* xbee */
+#define GPIOA_USART2_RX 3 /* xbee */
+#define GPIOA_SPI1_NSS 4
+#define GPIOA_SPI1_SCK 5
+#define GPIOA_SPI1_MISO 6
+#define GPIOA_SPI1_MOSI 7
+#define GPIOA_5V_DOMAIN_EN 8
+#define GPIOA_USART1_TX 9 /* gps */
+#define GPIOA_USART1_RX 10/* gps */
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_JTMS 13
+#define GPIOA_JTCK 14
+#define GPIOA_JTDI 15
+
+#define GPIOB_RECEIVER_PPM 0
+#define GPIOB_TACHOMETER 1
+#define GPIOB_BOOT1 2
+#define GPIOB_JTDO 3
+#define GPIOB_NJTRST 4
+#define GPIOB_LED_R 6
+#define GPIOB_LED_G 7
+#define GPIOB_LED_B 8
+#define GPIOB_I2C2_SCL 10
+#define GPIOB_I2C2_SDA 11
+
+
+#define GPIOC_AN_CURRENT_SENS 0
+#define GPIOC_AN_SUPPLY_SENS 1
+#define GPIOC_AN_6V_SENS 2
+#define GPIOC_AN33_0 3
+#define GPIOC_AN33_1 4
+#define GPIOC_AN33_2 5
+#define GPIOC_SDIO_D0 8
+#define GPIOC_SDIO_D1 9
+#define GPIOC_SDIO_D2 10
+#define GPIOC_SDIO_D3 11
+#define GPIOC_SDIO_CK 12
+#define GPIOC_TAMPER_RTC 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_SDIO_CMD 2
+#define GPIOD_PWM1 12
+#define GPIOD_PWM2 13
+#define GPIOD_PWM3 14
+#define GPIOD_PWM4 15
+
+#define GPIOE_GPS_PPS 0
+#define GPIOE_XBEE_SLEEP 1
+#define GPIOE_XBEE_RESET 2
+#define GPIOE_SDIO_DETECT 3
+#define GPIOE_USB_DISCOVERY 4
+#define GPIOE_GPS_PWR_EN 5
+#define GPIOE_BMP085_EOC 6
+#define GPIOE_MAG_INT 7
+#define GPIOE_MMA8451_INT1 8
+#define GPIOE_PWM5 9
+#define GPIOE_ITG3200_INT 10
+#define GPIOE_PWM6 11
+#define GPIOE_PWM7 13
+#define GPIOE_PWM8 14
+#define GPIOE_MMA8451_INT2 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ *
+ * 1 for open drain outputs denotes hi-Z state
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ * All input with pull-up except:
+#define GPIOA_USART2_CTS 0 //xbee
+#define GPIOA_USART2_RTS 1 //xbee
+#define GPIOA_USART2_TX 2 //xbee
+#define GPIOA_USART2_Rx 3 //xbee
+#define GPIOA_SPI1_NSS 4
+#define GPIOA_SPI1_SCK 5
+#define GPIOA_SPI1_MISO 6
+#define GPIOA_SPI1_MOSI 7
+#define GPIOA_5V_DOMAIN_EN 8
+#define GPIOA_USART1_TX 9
+#define GPIOA_USART1_RX 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_JTMS 13
+#define GPIOA_JTCK 14
+#define GPIOA_JTDI 15
+ */
+
+/* default after reset 0xA8000000 */
+#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(GPIOA_USART2_CTS) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART2_RTS) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_NSS) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \
+ PIN_MODE_OUTPUT(GPIOA_5V_DOMAIN_EN) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART1_TX) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART1_RX) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTMS) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTDI))
+/* default 0x00000000 */
+#define VAL_GPIOA_OTYPER 0x00000000
+/* default 0x00000000 */
+#define VAL_GPIOA_OSPEEDR 0x00000000
+/* 0x64000000 */
+#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(GPIOA_USART2_CTS) | \
+ PIN_PUDR_FLOATING(GPIOA_USART2_RTS) | \
+ PIN_PUDR_FLOATING(GPIOA_USART2_TX) | \
+ PIN_PUDR_FLOATING(GPIOA_USART2_RX) | \
+ PIN_PUDR_PULLUP(GPIOA_SPI1_NSS) | \
+ PIN_PUDR_PULLUP(GPIOA_SPI1_SCK) | \
+ PIN_PUDR_PULLUP(GPIOA_SPI1_MISO) | \
+ PIN_PUDR_PULLUP(GPIOA_SPI1_MOSI) | \
+ PIN_PUDR_FLOATING(GPIOA_5V_DOMAIN_EN) | \
+ PIN_PUDR_FLOATING(GPIOA_USART1_TX) | \
+ PIN_PUDR_FLOATING(GPIOA_USART1_RX) | \
+ PIN_PUDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUDR_PULLUP(GPIOA_JTMS) | \
+ PIN_PUDR_PULLDOWN(GPIOA_JTCK) | \
+ PIN_PUDR_PULLUP(GPIOA_JTDI))
+/* 0x00000000 */
+#define VAL_GPIOA_ODR 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_USART2_CTS, 7) | \
+ PIN_AFIO_AF(GPIOA_USART2_RTS, 7) | \
+ PIN_AFIO_AF(GPIOA_USART2_TX, 7) | \
+ PIN_AFIO_AF(GPIOA_USART2_RX, 7)| \
+ PIN_AFIO_AF(GPIOA_SPI1_NSS, 5) | \
+ PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) | \
+ PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) | \
+ PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5))
+/* 0x00000000 */
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USART1_TX, 7) | \
+ PIN_AFIO_AF(GPIOA_USART1_RX, 7) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_JTMS, 0) | \
+ PIN_AFIO_AF(GPIOA_JTCK, 0) | \
+ PIN_AFIO_AF(GPIOA_JTDI, 0))
+
+/*
+ * Port B setup.
+#define GPIOB_RECEIVER_PPM 0
+#define GPIOB_TACHOMETER 1
+#define GPIOB_BOOT1 2
+#define GPIOB_JTDO 3
+#define GPIOB_NJTRST 4
+#define GPIOB_LED_R 6
+#define GPIOB_LED_G 7
+#define GPIOB_LED_B 8
+#define GPIOB_I2C2_SCL 10
+#define GPIOB_I2C2_SDA 11
+ */
+/* 0x00000280 */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_RECEIVER_PPM) | \
+ PIN_MODE_INPUT(GPIOB_TACHOMETER) | \
+ PIN_MODE_INPUT(GPIOB_BOOT1) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTDO) | \
+ PIN_MODE_ALTERNATE(GPIOB_NJTRST) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_OUTPUT(GPIOB_LED_R) | \
+ PIN_MODE_OUTPUT(GPIOB_LED_G) | \
+ PIN_MODE_OUTPUT(GPIOB_LED_B) | \
+ PIN_MODE_INPUT(9) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_INPUT(13) | \
+ PIN_MODE_INPUT(14) | \
+ PIN_MODE_INPUT(15))
+/* 0x00000000 */
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOB_LED_R) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_LED_G) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_LED_B) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA))
+/* 0x000000C0 */
+#define VAL_GPIOB_OSPEEDR 0x000000C0//0xAAAAAAEA
+/* 0x00000100 */
+#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLDOWN(GPIOB_RECEIVER_PPM) | \
+ PIN_PUDR_PULLDOWN(GPIOB_TACHOMETER) | \
+ PIN_PUDR_FLOATING(GPIOB_BOOT1) | \
+ PIN_PUDR_FLOATING(GPIOB_JTDO) | \
+ PIN_PUDR_PULLUP(GPIOB_NJTRST) | \
+ PIN_PUDR_FLOATING(5) | \
+ PIN_PUDR_FLOATING(GPIOB_LED_R) | \
+ PIN_PUDR_FLOATING(GPIOB_LED_G) | \
+ PIN_PUDR_FLOATING(GPIOB_LED_B) | \
+ PIN_PUDR_FLOATING(9) | \
+ PIN_PUDR_FLOATING(GPIOB_I2C2_SCL) | \
+ PIN_PUDR_FLOATING(GPIOB_I2C2_SDA) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+/* 0x00000000 */
+#define VAL_GPIOB_ODR 0x000001C0
+/* 0x00000000 */
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_RECEIVER_PPM, 0) | \
+ PIN_AFIO_AF(GPIOB_JTDO, 0))
+/* 0x00000000 */
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C2_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_I2C2_SDA, 4))
+
+
+/*
+ * Port C setup.
+#define GPIOC_AN_CURRENT_SENS 0
+#define GPIOC_AN_SUPPLY_SENS 1
+#define GPIOC_AN_6V_SENS 2
+#define GPIOC_AN33_0 3
+#define GPIOC_AN33_1 4
+#define GPIOC_AN33_2 5
+
+#define GPIOC_SDIO_D0 8
+#define GPIOC_SDIO_D1 9
+#define GPIOC_SDIO_D2 10
+#define GPIOC_SDIO_D3 11
+#define GPIOC_SDIO_CK 12
+
+#define GPIOC_TAMPER_RTC 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+ */
+/* 0x00000000 */
+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_AN_CURRENT_SENS) | \
+ PIN_MODE_ANALOG(GPIOC_AN_SUPPLY_SENS) | \
+ PIN_MODE_ANALOG(GPIOC_AN_6V_SENS) | \
+ PIN_MODE_ANALOG(GPIOC_AN33_0) | \
+ PIN_MODE_ANALOG(GPIOC_AN33_1) | \
+ PIN_MODE_ANALOG(GPIOC_AN33_2) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_CK) | \
+ PIN_MODE_INPUT(GPIOC_TAMPER_RTC) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+
+/* 0x00000000 */
+#define VAL_GPIOC_OTYPER 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_25M(GPIOC_SDIO_D0) | \
+ PIN_OSPEED_25M(GPIOC_SDIO_D1) | \
+ PIN_OSPEED_25M(GPIOC_SDIO_D2) | \
+ PIN_OSPEED_25M(GPIOC_SDIO_D3) | \
+ PIN_OSPEED_25M(GPIOC_SDIO_CK) | \
+ PIN_OSPEED_2M(GPIOC_TAMPER_RTC))
+/* 0x00000000 */
+#define VAL_GPIOC_PUPDR (PIN_PUDR_FLOATING(GPIOC_AN_CURRENT_SENS) | \
+ PIN_PUDR_FLOATING(GPIOC_AN_SUPPLY_SENS) | \
+ PIN_PUDR_FLOATING(GPIOC_AN_6V_SENS) | \
+ PIN_PUDR_FLOATING(GPIOC_AN33_0) | \
+ PIN_PUDR_FLOATING(GPIOC_AN33_1) | \
+ PIN_PUDR_FLOATING(GPIOC_AN33_2) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(GPIOC_SDIO_D0) | \
+ PIN_PUDR_PULLUP(GPIOC_SDIO_D1) | \
+ PIN_PUDR_PULLUP(GPIOC_SDIO_D2) | \
+ PIN_PUDR_PULLUP(GPIOC_SDIO_D3) | \
+ PIN_PUDR_PULLUP(GPIOC_SDIO_CK) | \
+ PIN_PUDR_FLOATING(GPIOC_TAMPER_RTC) | \
+ PIN_PUDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUDR_FLOATING(GPIOC_OSC32_OUT))
+/* 0x00000000 */
+#define VAL_GPIOC_ODR 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOC_AFRL 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_D1, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_D2, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_D3, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_CK, 12))
+
+/*
+ * Port D setup.
+#define GPIOD_SDIO_CMD 2
+#define GPIOD_PWM1 12
+#define GPIOD_PWM2 13
+#define GPIOD_PWM3 14
+#define GPIOD_PWM4 15
+ */
+/* 0x00000000 */
+#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \
+ PIN_MODE_ALTERNATE(GPIOD_PWM1) | \
+ PIN_MODE_ALTERNATE(GPIOD_PWM2) | \
+ PIN_MODE_ALTERNATE(GPIOD_PWM3) | \
+ PIN_MODE_ALTERNATE(GPIOD_PWM4))
+/* 0x00000000 */
+#define VAL_GPIOD_OTYPER 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_25M(GPIOD_SDIO_CMD))
+/* 0x00000000 */
+#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(GPIOD_SDIO_CMD) | \
+ PIN_PUDR_PULLDOWN(GPIOD_PWM1) | \
+ PIN_PUDR_PULLDOWN(GPIOD_PWM2) | \
+ PIN_PUDR_PULLDOWN(GPIOD_PWM3) | \
+ PIN_PUDR_PULLDOWN(GPIOD_PWM4))
+/* 0x00000000 */
+#define VAL_GPIOD_ODR 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_SDIO_CMD, 12))
+/* 0x00000000 */
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PWM1, 2) | \
+ PIN_AFIO_AF(GPIOD_PWM2, 2) | \
+ PIN_AFIO_AF(GPIOD_PWM3, 2) | \
+ PIN_AFIO_AF(GPIOD_PWM4, 2))
+
+
+/*
+ * Port E setup.
+#define GPIOE_GPS_PPS 0
+#define GPIOE_XBEE_SLEEP 1
+#define GPIOE_XBEE_RESET 2
+#define GPIOE_SDIO_DETECT 3
+#define GPIOE_USB_DISCOVERY 4
+#define GPIOE_GPS_EN 5
+#define GPIOE_BMP085_EOC 6
+#define GPIOE_MAG_INT 7
+#define GPIOE_MMA8451_INT1 8
+#define GPIOE_PWM5 9
+#define GPIOE_ITG3200_INT 10
+#define GPIOE_PWM6 11
+#define GPIOE_TACHOMETER 12
+#define GPIOE_PWM7 13
+#define GPIOE_PWM8 14
+#define GPIOE_MMA8451_INT2 15
+ */
+/* 0x00000000 */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_GPS_PPS) | \
+ PIN_MODE_OUTPUT(GPIOE_XBEE_SLEEP) | \
+ PIN_MODE_OUTPUT(GPIOE_XBEE_RESET) | \
+ PIN_MODE_INPUT(GPIOE_SDIO_DETECT) | \
+ PIN_MODE_OUTPUT(GPIOE_USB_DISCOVERY) | \
+ PIN_MODE_OUTPUT(GPIOE_GPS_PWR_EN) | \
+ PIN_MODE_INPUT(GPIOE_BMP085_EOC) | \
+ PIN_MODE_INPUT(GPIOE_MAG_INT) | \
+ PIN_MODE_INPUT(GPIOE_MMA8451_INT1) | \
+ PIN_MODE_ALTERNATE(GPIOE_PWM5) | \
+ PIN_MODE_INPUT(GPIOE_ITG3200_INT) | \
+ PIN_MODE_ALTERNATE(GPIOE_PWM6) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_ALTERNATE(GPIOE_PWM7) | \
+ PIN_MODE_ALTERNATE(GPIOE_PWM8) | \
+ PIN_MODE_INPUT(GPIOE_MMA8451_INT2))
+/* 0x00000000 */
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_XBEE_SLEEP) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_XBEE_RESET) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_USB_DISCOVERY) | \
+ PIN_OTYPE_OPENDRAIN(GPIOE_GPS_PWR_EN) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PWM5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PWM6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PWM7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PWM8))
+/* 0x00000000 */
+#define VAL_GPIOE_OSPEEDR 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOE_PUPDR (PIN_PUDR_PULLDOWN(GPIOE_GPS_PPS) | \
+ PIN_PUDR_PULLUP(GPIOE_XBEE_SLEEP) | \
+ PIN_PUDR_FLOATING(GPIOE_XBEE_RESET) | \
+ PIN_PUDR_PULLUP(GPIOE_SDIO_DETECT) | \
+ PIN_PUDR_FLOATING(GPIOE_USB_DISCOVERY) | \
+ PIN_PUDR_FLOATING(GPIOE_GPS_PWR_EN) | \
+ PIN_PUDR_PULLDOWN(GPIOE_BMP085_EOC) | \
+ PIN_PUDR_PULLDOWN(GPIOE_MAG_INT) | \
+ PIN_PUDR_PULLDOWN(GPIOE_MMA8451_INT1) | \
+ PIN_PUDR_PULLDOWN(GPIOE_PWM5) | \
+ PIN_PUDR_PULLDOWN(GPIOE_ITG3200_INT) | \
+ PIN_PUDR_PULLDOWN(GPIOE_PWM6) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLDOWN(GPIOE_PWM7) | \
+ PIN_PUDR_PULLDOWN(GPIOE_PWM8) | \
+ PIN_PUDR_PULLDOWN(GPIOE_MMA8451_INT2))
+/* 0x00000000 */
+#define VAL_GPIOE_ODR 0x30
+/* 0x00000000 */
+#define VAL_GPIOE_AFRL 0x00000000
+/* 0x00000000 */
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PWM5, 1) | \
+ PIN_AFIO_AF(GPIOE_PWM6, 1) | \
+ PIN_AFIO_AF(GPIOE_PWM7, 1) | \
+ PIN_AFIO_AF(GPIOE_PWM8, 1))
+
+/*
+ * Port F setup.
+ */
+#define VAL_GPIOF_MODER 0x00000000
+#define VAL_GPIOF_OTYPER 0x00000000
+#define VAL_GPIOF_OSPEEDR 0x00000000
+#define VAL_GPIOF_PUPDR 0x00000000
+#define VAL_GPIOF_ODR 0x00000000
+#define VAL_GPIOF_AFRL 0x00000000
+#define VAL_GPIOF_AFRH 0x00000000
+
+/*
+ * Port G setup.
+ */
+#define VAL_GPIOG_MODER 0x00000000
+#define VAL_GPIOG_OTYPER 0x00000000
+#define VAL_GPIOG_OSPEEDR 0x00000000
+#define VAL_GPIOG_PUPDR 0x00000000
+#define VAL_GPIOG_ODR 0x00000000
+#define VAL_GPIOG_AFRL 0x00000000
+#define VAL_GPIOG_AFRH 0x00000000
+
+/*
+ * Port H setup.
+ */
+#define VAL_GPIOH_MODER 0x00000000
+#define VAL_GPIOH_OTYPER 0x00000000
+#define VAL_GPIOH_OSPEEDR 0x00000000
+#define VAL_GPIOH_PUPDR 0x00000000
+#define VAL_GPIOH_ODR 0x00000000
+#define VAL_GPIOH_AFRL 0x00000000
+#define VAL_GPIOH_AFRH 0x00000000
+
+/*
+ * Port I setup.
+ */
+#define VAL_GPIOI_MODER 0x00000000
+#define VAL_GPIOI_OTYPER 0x00000000
+#define VAL_GPIOI_OSPEEDR 0x00000000
+#define VAL_GPIOI_PUPDR 0x00000000
+#define VAL_GPIOI_ODR 0x00000000
+#define VAL_GPIOI_AFRL 0x00000000
+#define VAL_GPIOI_AFRH 0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk new file mode 100644 index 000000000..8f50edf14 --- /dev/null +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1
diff --git a/os/hal/boards/OLIMEX_AVR_CAN/board.c b/os/hal/boards/OLIMEX_AVR_CAN/board.c new file mode 100644 index 000000000..f7e458d9b --- /dev/null +++ b/os/hal/boards/OLIMEX_AVR_CAN/board.c @@ -0,0 +1,90 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+ {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+ {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+ {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+ {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+ {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+ {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+ {VAL_PORTG, VAL_DDRG},
+#endif
+};
+#endif /* HAL_USE_PAL */
+
+CH_IRQ_HANDLER(TIMER0_COMP_vect) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * External interrupts setup, all disabled initially.
+ */
+ EICRA = 0x00;
+ EICRB = 0x00;
+ EIMSK = 0x00;
+
+ /*
+ * Enables Idle mode for SLEEP instruction.
+ */
+ SMCR = (1 << SE);
+
+ /*
+ * Timer 0 setup.
+ */
+ TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */
+ (0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */
+ (0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */
+ OCR0A = F_CPU / 64 / CH_FREQUENCY - 1;
+ TCNT0 = 0; /* Reset counter. */
+ TIFR0 = (1 << OCF0A); /* Reset pending. */
+ TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */
+}
diff --git a/os/hal/boards/OLIMEX_AVR_CAN/board.h b/os/hal/boards/OLIMEX_AVR_CAN/board.h new file mode 100644 index 000000000..4d674756e --- /dev/null +++ b/os/hal/boards/OLIMEX_AVR_CAN/board.h @@ -0,0 +1,99 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex AVR-CAN proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_AVR_CAN
+#define BOARD_NAME "Olimex AVR-CAN"
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRA 0x00
+#define VAL_PORTA 0xFF
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRB 0x00
+#define VAL_PORTB 0xFF
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRC 0x00
+#define VAL_PORTC 0xFF
+
+/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
+ * IN IN OUT IN OUT IN IN IN
+ * DDRD 0 0 1 0 1 0 0 0
+ * PU HiZ VAL PU VAL HiZ HiZ HiZ
+ * PORTD 1 0 ?1 1 1 0 0 0
+ */
+#define VAL_DDRD 0x28
+#define VAL_PORTD 0xB8
+
+/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0
+ * IN IN IN OUT IN IN OUT IN
+ * DDRE 0 0 0 1 0 0 1 0
+ * PU PU HiZ VAL PU PU VAL HiZ
+ * PORTE 1 1 0 1 1 1 1 0
+ */
+#define VAL_DDRE 0x12
+#define VAL_PORTE 0xDE
+
+/* TDI TDO TMS TCK PF3 PF2 PF1 PF0
+ * x x x x IN IN IN IN
+ * DDRF 0 0 0 0 0 0 0 0
+ * x x x x PU PU PU PU
+ * PORTF 0 0 0 0 1 1 1 1
+ *
+ */
+#define VAL_DDRF 0x00
+#define VAL_PORTF 0x0F
+
+/* x x x x x PG2 PG1 PG0
+ * x x x x x IN IN IN
+ * DDRG 0 0 0 0 0 0 0 0
+ * x x x x x PU PU PU
+ * PORTG 0 0 0 0 0 1 1 1
+ *
+ */
+#define VAL_DDRG 0x00
+#define VAL_PORTG 0x07
+
+#define PORTE_LED 4
+#define PORTE_BUTTON 5
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_AVR_CAN/board.mk b/os/hal/boards/OLIMEX_AVR_CAN/board.mk new file mode 100644 index 000000000..4d2d406ad --- /dev/null +++ b/os/hal/boards/OLIMEX_AVR_CAN/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_AVR_CAN/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_AVR_CAN
diff --git a/os/hal/boards/OLIMEX_AVR_MT_128/board.c b/os/hal/boards/OLIMEX_AVR_MT_128/board.c new file mode 100644 index 000000000..ff1ee85e8 --- /dev/null +++ b/os/hal/boards/OLIMEX_AVR_MT_128/board.c @@ -0,0 +1,93 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+ {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+ {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+ {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+ {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+ {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+ {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+ {VAL_PORTG, VAL_DDRG},
+#endif
+};
+#endif /* HAL_USE_PAL */
+
+/**
+ * @brief Timer0 interrupt handler.
+ */
+CH_IRQ_HANDLER(TIMER0_COMP_vect) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * External interrupts setup, all disabled initially.
+ */
+ EICRA = 0x00;
+ EICRB = 0x00;
+ EIMSK = 0x00;
+
+ /*
+ * Enables Idle mode for SLEEP instruction.
+ */
+ MCUCR = (1 << SE);
+
+ /*
+ * Timer 0 setup.
+ */
+ TCCR0 = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */
+ (0 << COM01) | (0 << COM00) | /* OC0A disabled. */
+ (1 << CS02) | (0 << CS01) | (0 << CS00); /* CLK/64 clock. */
+ OCR0 = F_CPU / 64 / CH_FREQUENCY - 1;
+ TCNT0 = 0; /* Reset counter. */
+ TIFR = (1 << OCF0); /* Reset pending. */
+ TIMSK = (1 << OCIE0); /* IRQ on compare. */
+}
diff --git a/os/hal/boards/OLIMEX_AVR_MT_128/board.h b/os/hal/boards/OLIMEX_AVR_MT_128/board.h new file mode 100644 index 000000000..3c99f9d53 --- /dev/null +++ b/os/hal/boards/OLIMEX_AVR_MT_128/board.h @@ -0,0 +1,124 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex AVR-MT-128 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_AVR_MT_128
+#define BOARD_NAME "Olimex AVR-MT-128"
+
+/* PA7 RLY DS B5 B4 B3 B2 B1
+ * IN OUT IN IN IN IN IN IN
+ * DDRA 0 1 0 0 0 0 0 0
+ * PU VAL HiZ HiZ HiZ HiZ HiZ HiZ
+ * PORTA 1 0 0 0 0 0 0 0
+ */
+#define VAL_DDRA 0x40
+#define VAL_PORTA 0x80
+
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRB 0x00
+#define VAL_PORTB 0xFF
+
+/* D7 D6 D5 D4 PC3 E R/W RS
+ * OUT OUT OUT OUT IN OUT OUT OUT
+ * DDRC 1 1 1 1 0 1 1 1
+ * PU PU PU PU PU VAL VAL VAL
+ * PORTC 0 0 0 0 1 0 0 0
+ */
+#define VAL_DDRC 0xF7
+#define VAL_PORTC 0x08
+
+/* PD7 PD6 PD5 PD4 TXD RXD PD1 PD0
+ * IN IN IN IN OUT IN IN IN
+ * DDRD 0 0 0 0 1 0 0 0
+ * PU PU PU PU VAL HiZ PU PU
+ * PORTD 1 1 1 1 1 0 1 1
+ */
+#define VAL_DDRD 0x08
+#define VAL_PORTD 0xFB
+
+/* PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0
+ * IN IN OUT OUT IN IN OUT IN
+ * DDRE 0 0 1 1 0 0 1 0
+ * PU PU VAL VAL PU PU VAL PU
+ * PORTE 1 1 1 1 1 1 1 1
+ */
+#define VAL_DDRE 0x32
+#define VAL_PORTE 0xFF
+
+/* TDI TDO TMS TCK PF3 PF2 PF1 PF0
+ * x x x x IN IN IN IN
+ * DDRF 0 0 0 0 0 0 0 0
+ * x x x x PU PU PU PU
+ * PORTF 0 0 0 0 1 1 1 1
+ *
+ */
+#define VAL_DDRF 0x00
+#define VAL_PORTF 0x0F
+
+/* x x x x x PG2 PG1 PG0
+ * x x x x x IN IN IN
+ * DDRG 0 0 0 0 0 0 0 0
+ * x x x x x PU PU PU
+ * PORTG 0 0 0 0 0 1 1 1
+ *
+ */
+#define VAL_DDRG 0x00
+#define VAL_PORTG 0x07
+
+
+#define PORTA_BUTTON1 0
+#define PORTA_BUTTON2 1
+#define PORTA_BUTTON3 2
+#define PORTA_BUTTON4 3
+#define PORTA_BUTTON5 4
+#define PORTA_DALLAS 5
+#define PORTA_RELAY 6
+
+#define PORTC_44780_RS_MASK (1 << 0)
+#define PORTC_44780_RW_MASK (1 << 1)
+#define PORTC_44780_E_MASK (1 << 2)
+#define PORTC_44780_D4_MASK (1 << 4)
+#define PORTC_44780_D5_MASK (1 << 5)
+#define PORTC_44780_D6_MASK (1 << 6)
+#define PORTC_44780_D7_MASK (1 << 7)
+#define PORTC_44780_DATA_MASK (PORTC_44780_D4_MASK | PORTC_44780_D5_MASK | \
+ PORTC_44780_D6_MASK | PORTC_44780_D7_MASK)
+
+#define PORTE_BUZZ1 (1 << 4)
+#define PORTE_BUZZ2 (1 << 5)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_AVR_MT_128/board.mk b/os/hal/boards/OLIMEX_AVR_MT_128/board.mk new file mode 100644 index 000000000..7b903ffec --- /dev/null +++ b/os/hal/boards/OLIMEX_AVR_MT_128/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_AVR_MT_128/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_AVR_MT_128
diff --git a/os/hal/boards/OLIMEX_LPC-P1227/board.c b/os/hal/boards/OLIMEX_LPC-P1227/board.c new file mode 100644 index 000000000..09bb82e7b --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC-P1227/board.c @@ -0,0 +1,54 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ lpc122x_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Extra, board-specific, initializations.
+ */
+ LPC_IOCON->PIO1_4 = 0x80; /* Disables pull-up on LED2 output. */
+ LPC_IOCON->PIO1_5 = 0x80; /* Disables pull-up on LED1 output */
+ LPC_IOCON->PIO1_6 = 0x80; /* Disables pull-up on Buzzer output */
+}
diff --git a/os/hal/boards/OLIMEX_LPC-P1227/board.h b/os/hal/boards/OLIMEX_LPC-P1227/board.h new file mode 100644 index 000000000..ae2e879a7 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC-P1227/board.h @@ -0,0 +1,98 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex LPC-P1227 board.
+ *
+ */
+
+/*
+ * Board identifiers.
+ */
+#define OLIMEX_LPC_P1227
+#define BOARD_NAME "Olimex LPC-P1227"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR 0x00000000
+#define VAL_GPIO0DATA 0x00000000
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_LED1) | \
+ PAL_PORT_BIT(GPIO1_LED2) | \
+ PAL_PORT_BIT(GPIO1_BUZZER)
+
+#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_LED1)
+
+
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR PAL_PORT_BIT(GPIO2_LCD_DC) | \
+ PAL_PORT_BIT(GPIO2_LCD_SS) | \
+ PAL_PORT_BIT(GPIO2_LCD_RES)
+#define VAL_GPIO2DATA PAL_PORT_BIT(GPIO2_LCD_SS)
+
+
+/*
+ * Pin definitions.
+ */
+
+#define GPIO1_LED1 5
+#define GPIO1_LED2 4
+#define GPIO1_SW_WAKEUP 3
+#define GPIO1_BUZZER 6
+
+#define GPIO2_SW_USER1 12
+#define GPIO2_SW_USER2 11
+#define GPIO2_SW_USER3 10
+#define GPIO2_LCD_DC 15
+#define GPIO2_LCD_SS 14
+#define GPIO2_LCD_RES 13
+
+/* LCD3310 pins */
+#define LCD3310_RES_PIN GPIO2_LCD_RES
+#define LCD3310_RES_PORT GPIO2
+#define LCD3310_DC_PIN GPIO2_LCD_DC
+#define LCD3310_DC_PORT GPIO2
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_LPC-P1227/board.mk b/os/hal/boards/OLIMEX_LPC-P1227/board.mk new file mode 100644 index 000000000..090251880 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC-P1227/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_LPC-P1227/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_LPC-P1227
diff --git a/os/hal/boards/OLIMEX_LPC_P1343/board.c b/os/hal/boards/OLIMEX_LPC_P1343/board.c new file mode 100644 index 000000000..a0757d587 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P1343/board.c @@ -0,0 +1,52 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ LPC13xx_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Extra, board-specific, initializations.
+ */
+}
diff --git a/os/hal/boards/OLIMEX_LPC_P1343/board.h b/os/hal/boards/OLIMEX_LPC_P1343/board.h new file mode 100644 index 000000000..ca7934f4d --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P1343/board.h @@ -0,0 +1,104 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex LPC-P1343 proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_OLIMEX_LPC_P1343
+#define BOARD_NAME "Olimex LPC-P1343"
+
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK 12000000
+
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR 0x00000000
+#define VAL_GPIO0DATA 0x00000000
+
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR PAL_PORT_BIT(GPIO1_SW2)
+
+#define VAL_GPIO1DATA PAL_PORT_BIT(GPIO1_SW2)
+
+/*
+ * GPIO 2 initial setup.
+ */
+
+#define VAL_GPIO2DIR PAL_PORT_BIT(GPIO2_SW1) | \
+ PAL_PORT_BIT(GPIO2_LED5) | \
+ PAL_PORT_BIT(GPIO2_LED6) | \
+ PAL_PORT_BIT(GPIO2_LED7) | \
+ PAL_PORT_BIT(GPIO2_LED8)
+
+#define VAL_GPIO2DATA PAL_PORT_BIT(GPIO2_LED5) | \
+ PAL_PORT_BIT(GPIO2_LED6) | \
+ PAL_PORT_BIT(GPIO2_LED7) | \
+ PAL_PORT_BIT(GPIO2_LED8)
+
+/*
+ * GPIO 3 initial setup.
+ */
+
+#define VAL_GPIO3DIR PAL_PORT_BIT(GPIO3_LED1) | \
+ PAL_PORT_BIT(GPIO3_LED2) | \
+ PAL_PORT_BIT(GPIO3_LED3) | \
+ PAL_PORT_BIT(GPIO3_LED4)
+
+#define VAL_GPIO3DATA PAL_PORT_BIT(GPIO3_LED1) | \
+ PAL_PORT_BIT(GPIO3_LED2) | \
+ PAL_PORT_BIT(GPIO3_LED3) | \
+ PAL_PORT_BIT(GPIO3_LED4)
+
+/*
+ * Pin definitions.
+ */
+#define GPIO1_SW2 4
+#define GPIO1_SPI0SEL 11
+
+#define GPIO2_SW1 9
+
+#define GPIO3_LED1 0
+#define GPIO3_LED2 1
+#define GPIO3_LED3 2
+#define GPIO3_LED4 3
+#define GPIO2_LED5 4
+#define GPIO2_LED6 5
+#define GPIO2_LED7 6
+#define GPIO2_LED8 7
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_LPC_P1343/board.mk b/os/hal/boards/OLIMEX_LPC_P1343/board.mk new file mode 100644 index 000000000..718cc6e29 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P1343/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_LPC_P1343/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_LPC_P1343
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/board.c b/os/hal/boards/OLIMEX_LPC_P2148/board.c new file mode 100644 index 000000000..1c0a00302 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P2148/board.c @@ -0,0 +1,95 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#define VAL_TC0_PRESCALER 0
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ VAL_PINSEL0,
+ VAL_PINSEL1,
+ VAL_PINSEL2,
+ {VAL_FIO0PIN, VAL_FIO0DIR},
+ {VAL_FIO1PIN, VAL_FIO1DIR}
+};
+#endif
+
+/*
+ * Timer 0 IRQ handling here.
+ */
+static CH_IRQ_HANDLER(T0IrqHandler) {
+
+ CH_IRQ_PROLOGUE();
+ T0IR = 1; /* Clear interrupt on match MR0. */
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ VICVectAddr = 0;
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ lpc214x_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return !palReadPad(IOPORT2, PB_CP1);
+}
+
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return palReadPad(IOPORT2, PB_WP1);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * System Timer initialization, 1ms intervals.
+ */
+ SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
+ VICIntEnable = INTMASK(SOURCE_Timer0);
+ TC *timer = T0Base;
+ timer->TC_PR = VAL_TC0_PRESCALER;
+ timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1);
+ timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */
+ timer->TC_TCR = 2; /* Reset counter and prescaler. */
+ timer->TC_TCR = 1; /* Timer enabled. */
+}
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/board.h b/os/hal/boards/OLIMEX_LPC_P2148/board.h new file mode 100644 index 000000000..17651b313 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P2148/board.h @@ -0,0 +1,92 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex LPC-P2148 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_LPC_P2148
+#define BOARD_NAME "Olimex LPC-P2148"
+
+/*
+ * The following values are implementation dependent. You may change them in
+ * order to match your HW.
+ */
+#define FOSC 12000000
+#define CCLK 48000000
+#define PCLK 12000000
+
+/*
+ * Pins configuration for Olimex LPC-P2148.
+ *
+ * PINSEL0
+ * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD
+ * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0
+ * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01
+ * FIO0DIR (15...0)
+ * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- --
+ * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0
+ *
+ * PINSEL1
+ * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0
+ * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16
+ * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00
+ * FIO0DIR (31...16)
+ * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN
+ * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0
+ *
+ * FIO1DIR (31...16)
+ * -- -- -- -- -- IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT
+ * 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
+ */
+#define VAL_PINSEL0 0x00055555
+#define VAL_PINSEL1 0x100840A8
+#define VAL_PINSEL2 0x00000004 /* Do not modify */
+#define VAL_FIO0DIR 0xB0703C00
+#define VAL_FIO1DIR 0x01FF0000
+#define VAL_FIO0PIN 0xFFFFFFFF
+#define VAL_FIO1PIN 0xFFFFFFFF
+
+#define PA_LED1 10
+#define PA_LED2 11
+#define PA_BUZZ1 12
+#define PA_BUZZ2 13
+#define PA_BSL 14
+#define PA_BUTTON1 15
+#define PA_BUTTON2 16
+#define PA_SSEL1 20
+#define PA_LEDUSB 31
+
+#define PB_WP1 24
+#define PB_CP1 25
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/board.mk b/os/hal/boards/OLIMEX_LPC_P2148/board.mk new file mode 100644 index 000000000..5d0937e6d --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P2148/board.mk @@ -0,0 +1,5 @@ +# List of all the mandatory board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_LPC_P2148/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_LPC_P2148
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c new file mode 100644 index 000000000..cf2182f08 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c @@ -0,0 +1,111 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * Buzzer driver for Olimex LPC-P2148.
+ * Uses the timer 1 for wave generation and a Virtual Timer for the sound
+ * duration.
+ * The driver also generates an event when the sound is done and the buzzer
+ * goes silent.
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#include "buzzer.h"
+
+EventSource BuzzerSilentEventSource;
+
+#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1)
+#define StopCounter(t) ((t)->TC_EMR = 0, (t)->TC_TCR = 2)
+
+/**
+ * @brief Buzzer driver initialization.
+ */
+void buzzInit(void) {
+
+ chEvtInit(&BuzzerSilentEventSource);
+
+ /*
+ * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions.
+ * Enables Timer1 clock.
+ */
+ PINSEL0 &= 0xF0FFFFFF;
+ PINSEL0 |= 0x0A000000;
+ PCONP = (PCONP & PCALL) | PCTIM1;
+
+ /*
+ * Timer setup.
+ */
+ TC *tc = T1Base;
+ StopCounter(tc);
+ tc->TC_CTCR = 0; /* Clock source is PCLK. */
+ tc->TC_PR = 0; /* Prescaler disabled. */
+ tc->TC_MCR = 2; /* Clear TC on match MR0. */
+}
+
+/**
+ * @brief Stops the sound.
+ *
+ * @param[in] p pointer to the timer
+ */
+static void stop(void *p) {
+
+ StopCounter((TC *)p);
+ chSysLockFromIsr();
+ chEvtBroadcastI(&BuzzerSilentEventSource);
+ chSysUnlockFromIsr();
+}
+
+/**
+ * @brief Plays a tone asynchronously.
+ *
+ * @param[in] freq approximated tone frequency
+ * @param[in] duration tone duration in systicks
+ */
+void buzzPlay(uint32_t freq, systime_t duration) {
+ static VirtualTimer bvt;
+ TC *tc = T1Base;
+
+ chSysLock();
+
+ if (chVTIsArmedI(&bvt)) { /* If a sound is already being */
+ chVTResetI(&bvt); /* played then aborts it. */
+ StopCounter(tc);
+ }
+
+ tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
+ StartCounter(tc);
+ chVTSetI(&bvt, duration, stop, tc);
+
+ chSysUnlock();
+}
+
+/**
+ * @brief Plays a tone.
+ *
+ * @param[in] freq approximated tone frequency
+ * @param[in] duration tone duration in systicks
+ */
+void buzzPlayWait(uint32_t freq, systime_t duration) {
+ TC *tc = T1Base;
+
+ StopCounter(tc);
+ tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
+ StartCounter(tc);
+ chThdSleep(duration);
+ StopCounter(tc);
+}
diff --git a/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h new file mode 100644 index 000000000..82f573902 --- /dev/null +++ b/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h @@ -0,0 +1,32 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BUZZER_H_
+#define _BUZZER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void buzzInit(void);
+ void buzzPlay(uint32_t freq, systime_t duration);
+ void buzzPlayWait(uint32_t freq, systime_t duration);
+#ifdef __cplusplus
+}
+#endif
+
+extern EventSource BuzzerSilentEventSource;
+
+#endif /* _BUZZER_H_ */
diff --git a/os/hal/boards/OLIMEX_MSP430_P1611/board.c b/os/hal/boards/OLIMEX_MSP430_P1611/board.c new file mode 100644 index 000000000..bf89db001 --- /dev/null +++ b/os/hal/boards/OLIMEX_MSP430_P1611/board.c @@ -0,0 +1,80 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
+ {VAL_P1OUT, VAL_P1DIR},
+#endif
+#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__)
+ {VAL_P2OUT, VAL_P2DIR},
+#endif
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
+ {VAL_P3OUT, VAL_P3DIR},
+#endif
+#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
+ {VAL_P4OUT, VAL_P4DIR},
+#endif
+#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
+ {VAL_P5OUT, VAL_P5DIR},
+#endif
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
+ {VAL_P6OUT, VAL_P6DIR},
+#endif
+};
+#endif
+
+CH_IRQ_HANDLER(TIMERA0) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+#if USE_MSP430_USART0
+ P3SEL |= (1 << 4) | (1 << 5);
+#endif
+
+#if USE_MSP430_USART1
+ P3SEL |= (1 << 6) | (1 << 7);
+#endif
+
+ /*
+ * Timer 0 setup, uses SMCLK as source.
+ */
+ TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit. */
+ TACTL = TACLR; /* Clean start. */
+ TACTL = TASSEL_2 | ID_2 | MC_1; /* Src=SMCLK, ID=4, cmp=TACCR0. */
+ TACCTL0 = CCIE; /* Interrupt on compare. */
+}
diff --git a/os/hal/boards/OLIMEX_MSP430_P1611/board.h b/os/hal/boards/OLIMEX_MSP430_P1611/board.h new file mode 100644 index 000000000..e28b85bf5 --- /dev/null +++ b/os/hal/boards/OLIMEX_MSP430_P1611/board.h @@ -0,0 +1,80 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex MSP430-P1611 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_MSP430_P1611
+#define BOARD_NAME "Olimex MSP430-P1611"
+
+/*
+ * Clock constants.
+ */
+#define LFXT1CLK 32768
+#define XT2CLK 8000000
+#define DCOCLK 750000
+
+/*
+ * Pin definitions for the Olimex MSP430-P1611 board.
+ */
+#define P3_O_TXD0 4
+#define P3_O_TXD0_MASK (1 << P3_O_TXD0)
+#define P3_I_RXD0 5
+#define P3_I_RXD0_MASK (1 << P3_I_RXD0)
+#define P6_O_LED 0
+#define P6_O_LED_MASK (1 << P6_O_LED)
+#define P6_I_BUTTON 1
+#define P6_I_BUTTON_MASK (1 << P6_I_BUTTON)
+
+/*
+ * Initial I/O ports settings.
+ */
+#define VAL_P1OUT 0x00
+#define VAL_P1DIR 0xFF
+
+#define VAL_P2OUT 0x00
+#define VAL_P2DIR 0xFF
+
+#define VAL_P3OUT P3_O_TXD0_MASK
+#define VAL_P3DIR ~P3_I_RXD0_MASK
+
+#define VAL_P4OUT 0x00
+#define VAL_P4DIR 0xFF
+
+#define VAL_P5OUT 0x00
+#define VAL_P5DIR 0xFF
+
+#define VAL_P6OUT P6_O_LED_MASK
+#define VAL_P6DIR ~P6_I_BUTTON_MASK
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_MSP430_P1611/board.mk b/os/hal/boards/OLIMEX_MSP430_P1611/board.mk new file mode 100644 index 000000000..84acad8ed --- /dev/null +++ b/os/hal/boards/OLIMEX_MSP430_P1611/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_MSP430_P1611/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_MSP430_P1611
diff --git a/os/hal/boards/OLIMEX_SAM7_EX256/board.c b/os/hal/boards/OLIMEX_SAM7_EX256/board.c new file mode 100644 index 000000000..9de1b3ffc --- /dev/null +++ b/os/hal/boards/OLIMEX_SAM7_EX256/board.c @@ -0,0 +1,137 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
+#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+ (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
+ {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
+#endif
+};
+#endif
+
+/*
+ * SYS IRQ handling here.
+ */
+static CH_IRQ_HANDLER(SYSIrqHandler) {
+
+ CH_IRQ_PROLOGUE();
+
+ if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
+ (void) AT91C_BASE_PITC->PITC_PIVR;
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+ }
+
+#if USE_SAM7_DBGU_UART
+ if (AT91C_BASE_DBGU->DBGU_CSR &
+ (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME |
+ AT91C_US_OVRE | AT91C_US_RXBRK)) {
+ sd_lld_serve_interrupt(&SDDBG);
+ }
+#endif
+ AT91C_BASE_AIC->AIC_EOICR = 0;
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ /* Watchdog disabled.*/
+ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+ at91sam7_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return !palReadPad(IOPORT2, PIOB_MMC_CP);
+}
+
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return palReadPad(IOPORT2, PIOB_MMC_WP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * LCD pins setup.
+ */
+ palClearPad(IOPORT2, PIOB_LCD_BL);
+ palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL);
+
+ palSetPad(IOPORT1, PIOA_LCD_RESET);
+ palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL);
+
+ /*
+ * Joystick and buttons setup.
+ */
+ palSetGroupMode(IOPORT1,
+ PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK |
+ PIOA_B4_MASK | PIOA_B5_MASK,
+ 0,
+ PAL_MODE_INPUT);
+ palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, 0, PAL_MODE_INPUT);
+
+ /*
+ * MMC/SD slot setup.
+ */
+ palSetGroupMode(IOPORT2,
+ PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK,
+ 0,
+ PAL_MODE_INPUT);
+
+ /*
+ * PIT Initialization.
+ */
+ AIC_ConfigureIT(AT91C_ID_SYS,
+ AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1),
+ SYSIrqHandler);
+ AIC_EnableIT(AT91C_ID_SYS);
+ AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1;
+ AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+
+ /*
+ * RTS/CTS pins enabled for USART0 only.
+ */
+ AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0;
+ AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+ AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+}
diff --git a/os/hal/boards/OLIMEX_SAM7_EX256/board.h b/os/hal/boards/OLIMEX_SAM7_EX256/board.h new file mode 100644 index 000000000..efe5ead0c --- /dev/null +++ b/os/hal/boards/OLIMEX_SAM7_EX256/board.h @@ -0,0 +1,101 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex SAM7-EX256 development board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_SAM7_EX256
+#define BOARD_NAME "Olimex SAM7-EX256"
+
+/*
+ * Select your platform by modifying the following line.
+ */
+#if !defined(SAM7_PLATFORM)
+#define SAM7_PLATFORM SAM7X256
+#endif
+
+#include "at91sam7.h"
+
+#define CLK 18432000
+#define MCK 48054857
+
+/*
+ * Initial I/O setup.
+ */
+#define VAL_PIOA_ODSR 0x00000000 /* Output data. */
+#define VAL_PIOA_OSR 0x00000000 /* Direction. */
+#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */
+
+#define VAL_PIOB_ODSR 0x00000000 /* Output data. */
+#define VAL_PIOB_OSR 0x00000000 /* Direction. */
+#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */
+
+/*
+ * I/O definitions.
+ */
+#define PIOA_LCD_RESET 2
+#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET)
+#define PIOA_B1 7
+#define PIOA_B1_MASK (1 << PIOA_B1)
+#define PIOA_B2 8
+#define PIOA_B2_MASK (1 << PIOA_B2)
+#define PIOA_B3 9
+#define PIOA_B3_MASK (1 << PIOA_B3)
+#define PIOA_B4 14
+#define PIOA_B4_MASK (1 << PIOA_B4)
+#define PIOA_B5 15
+#define PIOA_B5_MASK (1 << PIOA_B5)
+#define PIOA_USB_PUP 25
+#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP)
+#define PIOA_USB_PR 26
+#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR)
+#define PIOA_CS_MMC 13
+
+#define PIOB_PHY_PD 18
+#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD)
+#define PIOB_AUDIO_OUT 19
+#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT)
+#define PIOB_LCD_BL 20
+#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL)
+#define PIOB_MMC_WP 22
+#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP)
+#define PIOB_MMC_CP 23
+#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP)
+#define PIOB_SW1 24
+#define PIOB_SW1_MASK (1 << PIOB_SW1)
+#define PIOB_SW2 25
+#define PIOB_SW2_MASK (1 << PIOB_SW2)
+#define PIOB_PHY_IRQ 26
+#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_SAM7_EX256/board.mk b/os/hal/boards/OLIMEX_SAM7_EX256/board.mk new file mode 100644 index 000000000..d0a4816f1 --- /dev/null +++ b/os/hal/boards/OLIMEX_SAM7_EX256/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_SAM7_EX256/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_SAM7_EX256
diff --git a/os/hal/boards/OLIMEX_SAM7_P256/board.c b/os/hal/boards/OLIMEX_SAM7_P256/board.c new file mode 100644 index 000000000..936019c4d --- /dev/null +++ b/os/hal/boards/OLIMEX_SAM7_P256/board.c @@ -0,0 +1,117 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
+#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+ (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
+ {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
+#endif
+};
+#endif
+
+/*
+ * SYS IRQ handling here.
+ */
+static CH_IRQ_HANDLER(SYSIrqHandler) {
+
+ CH_IRQ_PROLOGUE();
+
+ if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
+ (void) AT91C_BASE_PITC->PITC_PIVR;
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+ }
+ AT91C_BASE_AIC->AIC_EOICR = 0;
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ /* Watchdog disabled.*/
+ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+ at91sam7_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return !palReadPad(IOPORT1, PIOA_MMC_CP);
+}
+
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return palReadPad(IOPORT1, PIOA_MMC_WP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * LED pins setup.
+ */
+ palClearPad(IOPORT1, PIOA_LED1);
+ palSetPadMode(IOPORT1, PIOA_LED1, PAL_MODE_OUTPUT_PUSHPULL);
+ palClearPad(IOPORT1, PIOA_LED2);
+ palSetPadMode(IOPORT1, PIOA_LED2, PAL_MODE_OUTPUT_PUSHPULL);
+
+ /*
+ * buttons setup.
+ */
+ palSetGroupMode(IOPORT1, PIOA_B1_MASK | PIOA_B2_MASK, 0, PAL_MODE_INPUT);
+
+ /*
+ * MMC/SD slot setup.
+ */
+ palSetGroupMode(IOPORT1,
+ PIOA_MMC_WP_MASK | PIOA_MMC_CP_MASK,
+ 0,
+ PAL_MODE_INPUT);
+
+ /*
+ * PIT Initialization.
+ */
+ AIC_ConfigureIT(AT91C_ID_SYS,
+ AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1),
+ SYSIrqHandler);
+ AIC_EnableIT(AT91C_ID_SYS);
+ AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1;
+ AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+}
diff --git a/os/hal/boards/OLIMEX_SAM7_P256/board.h b/os/hal/boards/OLIMEX_SAM7_P256/board.h new file mode 100644 index 000000000..d16c13271 --- /dev/null +++ b/os/hal/boards/OLIMEX_SAM7_P256/board.h @@ -0,0 +1,81 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex SAM7-P256 development board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_SAM7_P256
+
+/*
+ * Select your platform by modifying the following line.
+ */
+#if !defined(SAM7_PLATFORM)
+#define SAM7_PLATFORM SAM7S256
+#endif
+
+#include "at91sam7.h"
+
+#define CLK 18432000
+#define MCK 48054857
+
+/*
+ * Initial I/O setup.
+ */
+#define VAL_PIOA_ODSR 0x00000000 /* Output data. */
+#define VAL_PIOA_OSR 0x00000000 /* Direction. */
+#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */
+
+/*
+ * I/O definitions.
+ */
+#define PIOA_LED1 18
+#define PIOA_LED1_MASK (1 << PIOA_LED1_MASK)
+#define PIOA_LED2 17
+#define PIOA_LED2_MASK (1 << PIOA_LED2_MASK)
+#define PIOA_B1 19
+#define PIOA_B1_MASK (1 << PIOA_B1)
+#define PIOA_B2 20
+#define PIOA_B2_MASK (1 << PIOA_B2)
+#define PIOA_DP_PUP 25
+#define PIOA_DD_PUP_MASK (1 << PIOA_DP_PUP)
+#define PIOA_USB_D 26
+#define PIOA_USB_D_MASK (1 << PIOA_USB_D)
+
+#define PIOA_MMC_WP 25
+#define PIOA_MMC_WP_MASK (1 << PIOA_MMC_WP)
+#define PIOA_MMC_CP 15
+#define PIOA_MMC_CP_MASK (1 << PIOA_MMC_CP)
+#define PIOA_MMC_NPCS0 11
+#define PIOA_MMC_NPCS0_MASK (1 << PIOA_MMC_NPCS0_MASK)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_SAM7_P256/board.mk b/os/hal/boards/OLIMEX_SAM7_P256/board.mk new file mode 100644 index 000000000..e9fb6691a --- /dev/null +++ b/os/hal/boards/OLIMEX_SAM7_P256/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_SAM7_P256/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_SAM7_P256
diff --git a/os/hal/boards/OLIMEX_STM32_103STK/board.c b/os/hal/boards/OLIMEX_STM32_103STK/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_103STK/board.c @@ -0,0 +1,50 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_103STK/board.h b/os/hal/boards/OLIMEX_STM32_103STK/board.h new file mode 100644 index 000000000..df1b832d2 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_103STK/board.h @@ -0,0 +1,168 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-103STK proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_103STK
+#define BOARD_NAME "Olimex STM32-103STK"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WAKEUP 0
+#define GPIOC_BUTTON_TAMPER 13
+#define GPIOC_JOY 5
+#define GPIOC_JOY_CENTER_BUT 6
+
+#define GPIOA_SPI1NSS 4
+#define GPIOB_SPI2NSS 12
+
+#define GPIOC_MMCWP 2
+#define GPIOC_MMCCP 1
+
+#define GPIOC_USB_P 4
+#define GPIOC_LCD_RES 7
+#define GPIOC_NRF_CE 8
+#define GPIOC_NRF_IRQ 9
+#define GPIOC_LCD_E 10
+
+#define GPIOC_USB_DISC 11
+#define GPIOC_LED 12
+
+#define GPIOB_ACCEL_IRQ 5
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0 - Normal input (BUTTON).
+ * PA2 - Alternate output (USART2 TX).
+ * PA3 - Normal input (USART2 RX).
+ */
+#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB6,7 - Alternate open drain (I2C1).
+ * PB10,11 - Alternate open drain (I2C2).
+ * PB12 - Push Pull output (MMC SPI2 NSS).
+ * PB13 - Alternate output (MMC SPI2 SCK).
+ * PB14 - Normal input (MMC SPI2 MISO).
+ * PB15 - Alternate output (MMC SPI2 MOSI).
+ */
+#define VAL_GPIOBCRL 0xEE888888 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0xB4B3EE88 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC4 - Normal input because there is an external resistor.
+ * PC5 - Analog input (joystick).
+ * PC6 - Normal input because there is an external resistor.
+ * PC7 - Normal input because there is an external resistor.
+ * PC10 - Push Pull output (CAN CNTRL).
+ * PC11 - Push Pull output (USB DISC).
+ * PC12 - Open Drain output (LED).
+ */
+#define VAL_GPIOCCRL 0x44048888 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x88863388 /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0 - Normal input (XTAL).
+ * PD1 - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */
+#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
+#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_103STK/board.mk b/os/hal/boards/OLIMEX_STM32_103STK/board.mk new file mode 100644 index 000000000..383e1c490 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_103STK/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_103STK/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_103STK
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.c b/os/hal/boards/OLIMEX_STM32_E407/board.c new file mode 100644 index 000000000..a4152433a --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_E407/board.c @@ -0,0 +1,108 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ static bool_t last_status = FALSE;
+
+ if (blkIsTransferring(sdcp))
+ return last_status;
+ return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.h b/os/hal/boards/OLIMEX_STM32_E407/board.h new file mode 100644 index 000000000..505f30f7d --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_E407/board.h @@ -0,0 +1,1301 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex STM32-E407 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_E407
+#define BOARD_NAME "Olimex STM32-E407"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_KS8721_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 12000000
+#endif
+
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 330
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WKUP 0
+#define GPIOA_ETH_RMII_REF_CLK 1
+#define GPIOA_ETH_RMII_MDIO 2
+#define GPIOA_ETH_RMII_MDINT 3
+#define GPIOA_PIN4 4
+#define GPIOA_PIN5 5
+#define GPIOA_PIN6 6
+#define GPIOA_ETH_RMII_CRS_DV 7
+#define GPIOA_USB_HS_BUSON 8
+#define GPIOA_OTG_FS_VBUS 9
+#define GPIOA_OTG_FS_ID 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_JTAG_TMS 13
+#define GPIOA_JTAG_TCK 14
+#define GPIOA_JTAG_TDI 15
+
+#define GPIOB_USB_FS_BUSON 0
+#define GPIOB_USB_HS_FAULT 1
+#define GPIOB_BOOT1 2
+#define GPIOB_JTAG_TDO 3
+#define GPIOB_JTAG_TRST 4
+#define GPIOB_PIN5 5
+#define GPIOB_PIN6 6
+#define GPIOB_PIN7 7
+#define GPIOB_I2C1_SCL 8
+#define GPIOB_I2C1_SDA 9
+#define GPIOB_SPI2_SCK 10
+#define GPIOB_PIN11 11
+#define GPIOB_OTG_HS_ID 12
+#define GPIOB_OTG_HS_VBUS 13
+#define GPIOB_OTG_HS_DM 14
+#define GPIOB_OTG_HS_DP 15
+
+#define GPIOC_PIN0 0
+#define GPIOC_ETH_RMII_MDC 1
+#define GPIOC_SPI2_MISO 2
+#define GPIOC_SPI2_MOSI 3
+#define GPIOC_ETH_RMII_RXD0 4
+#define GPIOC_ETH_RMII_RXD1 5
+#define GPIOC_USART6_TX 6
+#define GPIOC_USART6_RX 7
+#define GPIOC_SD_D0 8
+#define GPIOC_SD_D1 9
+#define GPIOC_SD_D2 10
+#define GPIOC_SD_D3 11
+#define GPIOC_SD_CLK 12
+#define GPIOC_LED 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_SD_CMD 2
+#define GPIOD_PIN3 3
+#define GPIOD_PIN4 4
+#define GPIOD_PIN5 5
+#define GPIOD_PIN6 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_PIN12 12
+#define GPIOD_PIN13 13
+#define GPIOD_PIN14 14
+#define GPIOD_PIN15 15
+
+#define GPIOE_PIN0 0
+#define GPIOE_PIN1 1
+#define GPIOE_PIN2 2
+#define GPIOE_PIN3 3
+#define GPIOE_PIN4 4
+#define GPIOE_PIN5 5
+#define GPIOE_PIN6 6
+#define GPIOE_PIN7 7
+#define GPIOE_PIN8 8
+#define GPIOE_PIN9 9
+#define GPIOE_PIN10 10
+#define GPIOE_PIN11 11
+#define GPIOE_PIN12 12
+#define GPIOE_PIN13 13
+#define GPIOE_PIN14 14
+#define GPIOE_PIN15 15
+
+#define GPIOF_PIN0 0
+#define GPIOF_PIN1 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_USB_FS_FAULT 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+#define GPIOG_PIN0 0
+#define GPIOG_PIN1 1
+#define GPIOG_PIN2 2
+#define GPIOG_PIN3 3
+#define GPIOG_PIN4 4
+#define GPIOG_PIN5 5
+#define GPIOG_PIN6 6
+#define GPIOG_PIN7 7
+#define GPIOG_PIN8 8
+#define GPIOG_PIN9 9
+#define GPIOG_SPI2_CS 10
+#define GPIOG_ETH_RMII_TXEN 11
+#define GPIOG_PIN12 12
+#define GPIOG_ETH_RMII_TXD0 13
+#define GPIOG_ETH_RMII_TXD1 14
+#define GPIOG_PIN15 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+#define GPIOH_PIN2 2
+#define GPIOH_PIN3 3
+#define GPIOH_PIN4 4
+#define GPIOH_PIN5 5
+#define GPIOH_PIN6 6
+#define GPIOH_PIN7 7
+#define GPIOH_PIN8 8
+#define GPIOH_PIN9 9
+#define GPIOH_PIN10 10
+#define GPIOH_PIN11 11
+#define GPIOH_PIN12 12
+#define GPIOH_PIN13 13
+#define GPIOH_PIN14 14
+#define GPIOH_PIN15 15
+
+#define GPIOI_PIN0 0
+#define GPIOI_PIN1 1
+#define GPIOI_PIN2 2
+#define GPIOI_PIN3 3
+#define GPIOI_PIN4 4
+#define GPIOI_PIN5 5
+#define GPIOI_PIN6 6
+#define GPIOI_PIN7 7
+#define GPIOI_PIN8 8
+#define GPIOI_PIN9 9
+#define GPIOI_PIN10 10
+#define GPIOI_PIN11 11
+#define GPIOI_PIN12 12
+#define GPIOI_PIN13 13
+#define GPIOI_PIN14 14
+#define GPIOI_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON_WKUP (input floating).
+ * PA1 - ETH_RMII_REF_CLK (alternate 11).
+ * PA2 - ETH_RMII_MDIO (alternate 11).
+ * PA3 - ETH_RMII_MDINT (input floating).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - PIN5 (input pullup).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - ETH_RMII_CRS_DV (alternate 11).
+ * PA8 - USB_HS_BUSON (output pushpull maximum).
+ * PA9 - OTG_FS_VBUS (input pulldown).
+ * PA10 - OTG_FS_ID (alternate 10).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - JTAG_TMS (alternate 0).
+ * PA14 - JTAG_TCK (alternate 0).
+ * PA15 - JTAG_TDI (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) |\
+ PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_INPUT(GPIOA_PIN5) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \
+ PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_WKUP) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDIO) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_MDINT) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_HS_BUSON) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_VBUS) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON_WKUP) | \
+ PIN_OSPEED_100M(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_OSPEED_100M(GPIOA_ETH_RMII_MDIO) | \
+ PIN_OSPEED_100M(GPIOA_ETH_RMII_MDINT) |\
+ PIN_OSPEED_100M(GPIOA_PIN4) | \
+ PIN_OSPEED_100M(GPIOA_PIN5) | \
+ PIN_OSPEED_100M(GPIOA_PIN6) | \
+ PIN_OSPEED_100M(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_OSPEED_100M(GPIOA_USB_HS_BUSON) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_VBUS) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \
+ PIN_OSPEED_100M(GPIOA_JTAG_TCK) | \
+ PIN_OSPEED_100M(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_WKUP) |\
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_REF_CLK) |\
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDIO) |\
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_MDINT) |\
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOA_ETH_RMII_CRS_DV) |\
+ PIN_PUPDR_FLOATING(GPIOA_USB_HS_BUSON) |\
+ PIN_PUPDR_PULLDOWN(GPIOA_OTG_FS_VBUS) |\
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTAG_TMS) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_WKUP) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_REF_CLK) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_MDIO) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_MDINT) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_ETH_RMII_CRS_DV) | \
+ PIN_ODR_HIGH(GPIOA_USB_HS_BUSON) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_VBUS) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |\
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - USB_FS_BUSON (output pushpull maximum).
+ * PB1 - USB_HS_FAULT (input floating).
+ * PB2 - BOOT1 (input floating).
+ * PB3 - JTAG_TDO (alternate 0).
+ * PB4 - JTAG_TRST (alternate 0).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - I2C1_SCL (alternate 4).
+ * PB9 - I2C1_SDA (alternate 4).
+ * PB10 - SPI2_SCK (alternate 5).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - OTG_HS_ID (alternate 12).
+ * PB13 - OTG_HS_VBUS (input pulldown).
+ * PB14 - OTG_HS_DM (alternate 12).
+ * PB15 - OTG_HS_DP (alternate 12).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \
+ PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \
+ PIN_MODE_INPUT(GPIOB_BOOT1) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
+ PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \
+ PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_USB_FS_BUSON) |\
+ PIN_OTYPE_PUSHPULL(GPIOB_USB_HS_FAULT) |\
+ PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_VBUS) |\
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_USB_FS_BUSON) | \
+ PIN_OSPEED_100M(GPIOB_USB_HS_FAULT) | \
+ PIN_OSPEED_100M(GPIOB_BOOT1) | \
+ PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \
+ PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \
+ PIN_OSPEED_100M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_PIN6) | \
+ PIN_OSPEED_100M(GPIOB_PIN7) | \
+ PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \
+ PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \
+ PIN_OSPEED_100M(GPIOB_SPI2_SCK) | \
+ PIN_OSPEED_100M(GPIOB_PIN11) | \
+ PIN_OSPEED_100M(GPIOB_OTG_HS_ID) | \
+ PIN_OSPEED_100M(GPIOB_OTG_HS_VBUS) | \
+ PIN_OSPEED_100M(GPIOB_OTG_HS_DM) | \
+ PIN_OSPEED_100M(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_USB_FS_BUSON) |\
+ PIN_PUPDR_FLOATING(GPIOB_USB_HS_FAULT) |\
+ PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTAG_TRST) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
+ PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_ID) | \
+ PIN_PUPDR_PULLDOWN(GPIOB_OTG_HS_VBUS) |\
+ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_USB_FS_BUSON) | \
+ PIN_ODR_HIGH(GPIOB_USB_HS_FAULT) | \
+ PIN_ODR_HIGH(GPIOB_BOOT1) | \
+ PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \
+ PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
+ PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_ID) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \
+ PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) | \
+ PIN_AFIO_AF(GPIOB_USB_HS_FAULT, 0) | \
+ PIN_AFIO_AF(GPIOB_BOOT1, 0) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
+ PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - ETH_RMII_MDC (alternate 11).
+ * PC2 - SPI2_MISO (alternate 5).
+ * PC3 - SPI2_MOSI (alternate 5).
+ * PC4 - ETH_RMII_RXD0 (alternate 11).
+ * PC5 - ETH_RMII_RXD1 (alternate 11).
+ * PC6 - USART6_TX (alternate 8).
+ * PC7 - USART6_RX (alternate 8).
+ * PC8 - SD_D0 (alternate 12).
+ * PC9 - SD_D1 (alternate 12).
+ * PC10 - SD_D2 (alternate 12).
+ * PC11 - SD_D3 (alternate 12).
+ * PC12 - SD_CLK (alternate 12).
+ * PC13 - LED (output pushpull maximum).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) |\
+ PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) |\
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) |\
+ PIN_MODE_ALTERNATE(GPIOC_USART6_TX) | \
+ PIN_MODE_ALTERNATE(GPIOC_USART6_RX) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \
+ PIN_MODE_OUTPUT(GPIOC_LED) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_MDC) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI2_MOSI) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD0) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RMII_RXD1) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_LED) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \
+ PIN_OSPEED_100M(GPIOC_ETH_RMII_MDC) | \
+ PIN_OSPEED_100M(GPIOC_SPI2_MISO) | \
+ PIN_OSPEED_100M(GPIOC_SPI2_MOSI) | \
+ PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD0) | \
+ PIN_OSPEED_100M(GPIOC_ETH_RMII_RXD1) | \
+ PIN_OSPEED_100M(GPIOC_USART6_TX) | \
+ PIN_OSPEED_100M(GPIOC_USART6_RX) | \
+ PIN_OSPEED_100M(GPIOC_SD_D0) | \
+ PIN_OSPEED_100M(GPIOC_SD_D1) | \
+ PIN_OSPEED_100M(GPIOC_SD_D2) | \
+ PIN_OSPEED_100M(GPIOC_SD_D3) | \
+ PIN_OSPEED_100M(GPIOC_SD_CLK) | \
+ PIN_OSPEED_100M(GPIOC_LED) | \
+ PIN_OSPEED_100M(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_MDC) |\
+ PIN_PUPDR_FLOATING(GPIOC_SPI2_MISO) | \
+ PIN_PUPDR_FLOATING(GPIOC_SPI2_MOSI) | \
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD0) |\
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RMII_RXD1) |\
+ PIN_PUPDR_FLOATING(GPIOC_USART6_TX) | \
+ PIN_PUPDR_FLOATING(GPIOC_USART6_RX) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \
+ PIN_PUPDR_FLOATING(GPIOC_LED) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_ETH_RMII_MDC) | \
+ PIN_ODR_HIGH(GPIOC_SPI2_MISO) | \
+ PIN_ODR_HIGH(GPIOC_SPI2_MOSI) | \
+ PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD0) | \
+ PIN_ODR_HIGH(GPIOC_ETH_RMII_RXD1) | \
+ PIN_ODR_HIGH(GPIOC_USART6_TX) | \
+ PIN_ODR_HIGH(GPIOC_USART6_RX) | \
+ PIN_ODR_HIGH(GPIOC_SD_D0) | \
+ PIN_ODR_HIGH(GPIOC_SD_D1) | \
+ PIN_ODR_HIGH(GPIOC_SD_D2) | \
+ PIN_ODR_HIGH(GPIOC_SD_D3) | \
+ PIN_ODR_HIGH(GPIOC_SD_CLK) | \
+ PIN_ODR_HIGH(GPIOC_LED) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \
+ PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) | \
+ PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \
+ PIN_AFIO_AF(GPIOC_USART6_TX, 8) | \
+ PIN_AFIO_AF(GPIOC_USART6_RX, 8))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_D1, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_D2, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_D3, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \
+ PIN_AFIO_AF(GPIOC_LED, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - SD_CMD (alternate 12).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
+ PIN_OSPEED_100M(GPIOD_PIN1) | \
+ PIN_OSPEED_100M(GPIOD_SD_CMD) | \
+ PIN_OSPEED_100M(GPIOD_PIN3) | \
+ PIN_OSPEED_100M(GPIOD_PIN4) | \
+ PIN_OSPEED_100M(GPIOD_PIN5) | \
+ PIN_OSPEED_100M(GPIOD_PIN6) | \
+ PIN_OSPEED_100M(GPIOD_PIN7) | \
+ PIN_OSPEED_100M(GPIOD_PIN8) | \
+ PIN_OSPEED_100M(GPIOD_PIN9) | \
+ PIN_OSPEED_100M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_PIN11) | \
+ PIN_OSPEED_100M(GPIOD_PIN12) | \
+ PIN_OSPEED_100M(GPIOD_PIN13) | \
+ PIN_OSPEED_100M(GPIOD_PIN14) | \
+ PIN_OSPEED_100M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_SD_CMD) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input pullup).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - PIN8 (input pullup).
+ * PE9 - PIN9 (input pullup).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PIN14 (input pullup).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_PIN0) | \
+ PIN_OSPEED_100M(GPIOE_PIN1) | \
+ PIN_OSPEED_100M(GPIOE_PIN2) | \
+ PIN_OSPEED_100M(GPIOE_PIN3) | \
+ PIN_OSPEED_100M(GPIOE_PIN4) | \
+ PIN_OSPEED_100M(GPIOE_PIN5) | \
+ PIN_OSPEED_100M(GPIOE_PIN6) | \
+ PIN_OSPEED_100M(GPIOE_PIN7) | \
+ PIN_OSPEED_100M(GPIOE_PIN8) | \
+ PIN_OSPEED_100M(GPIOE_PIN9) | \
+ PIN_OSPEED_100M(GPIOE_PIN10) | \
+ PIN_OSPEED_100M(GPIOE_PIN11) | \
+ PIN_OSPEED_100M(GPIOE_PIN12) | \
+ PIN_OSPEED_100M(GPIOE_PIN13) | \
+ PIN_OSPEED_100M(GPIOE_PIN14) | \
+ PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input pullup).
+ * PF1 - PIN1 (input pullup).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - USB_FS_FAULT (input floating).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_USB_FS_FAULT) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_USB_FS_FAULT) |\
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
+ PIN_OSPEED_100M(GPIOF_PIN1) | \
+ PIN_OSPEED_100M(GPIOF_PIN2) | \
+ PIN_OSPEED_100M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_PIN4) | \
+ PIN_OSPEED_100M(GPIOF_PIN5) | \
+ PIN_OSPEED_100M(GPIOF_PIN6) | \
+ PIN_OSPEED_100M(GPIOF_PIN7) | \
+ PIN_OSPEED_100M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_PIN9) | \
+ PIN_OSPEED_100M(GPIOF_PIN10) | \
+ PIN_OSPEED_100M(GPIOF_USB_FS_FAULT) | \
+ PIN_OSPEED_100M(GPIOF_PIN12) | \
+ PIN_OSPEED_100M(GPIOF_PIN13) | \
+ PIN_OSPEED_100M(GPIOF_PIN14) | \
+ PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_USB_FS_FAULT) |\
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_USB_FS_FAULT) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_USB_FS_FAULT, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input pullup).
+ * PG1 - PIN1 (input pullup).
+ * PG2 - PIN2 (input pullup).
+ * PG3 - PIN3 (input pullup).
+ * PG4 - PIN4 (input pullup).
+ * PG5 - PIN5 (input pullup).
+ * PG6 - PIN6 (input pullup).
+ * PG7 - PIN7 (input pullup).
+ * PG8 - PIN8 (input pullup).
+ * PG9 - PIN9 (input pullup).
+ * PG10 - SPI2_CS (output pushpull maximum).
+ * PG11 - ETH_RMII_TXEN (alternate 11).
+ * PG12 - PIN12 (input pullup).
+ * PG13 - ETH_RMII_TXD0 (alternate 11).
+ * PG14 - ETH_RMII_TXD1 (alternate 11).
+ * PG15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_OUTPUT(GPIOG_SPI2_CS) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXEN) |\
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) |\
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) |\
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_SPI2_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXEN) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD0) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_RMII_TXD1) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
+ PIN_OSPEED_100M(GPIOG_PIN1) | \
+ PIN_OSPEED_100M(GPIOG_PIN2) | \
+ PIN_OSPEED_100M(GPIOG_PIN3) | \
+ PIN_OSPEED_100M(GPIOG_PIN4) | \
+ PIN_OSPEED_100M(GPIOG_PIN5) | \
+ PIN_OSPEED_100M(GPIOG_PIN6) | \
+ PIN_OSPEED_100M(GPIOG_PIN7) | \
+ PIN_OSPEED_100M(GPIOG_PIN8) | \
+ PIN_OSPEED_100M(GPIOG_PIN9) | \
+ PIN_OSPEED_100M(GPIOG_SPI2_CS) | \
+ PIN_OSPEED_100M(GPIOG_ETH_RMII_TXEN) | \
+ PIN_OSPEED_100M(GPIOG_PIN12) | \
+ PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD0) | \
+ PIN_OSPEED_100M(GPIOG_ETH_RMII_TXD1) | \
+ PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_SPI2_CS) | \
+ PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXEN) |\
+ PIN_PUPDR_PULLUP(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD0) |\
+ PIN_PUPDR_FLOATING(GPIOG_ETH_RMII_TXD1) |\
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_SPI2_CS) | \
+ PIN_ODR_HIGH(GPIOG_ETH_RMII_TXEN) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) | \
+ PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOG_SPI2_CS, 0) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_100M(GPIOH_PIN2) | \
+ PIN_OSPEED_100M(GPIOH_PIN3) | \
+ PIN_OSPEED_100M(GPIOH_PIN4) | \
+ PIN_OSPEED_100M(GPIOH_PIN5) | \
+ PIN_OSPEED_100M(GPIOH_PIN6) | \
+ PIN_OSPEED_100M(GPIOH_PIN7) | \
+ PIN_OSPEED_100M(GPIOH_PIN8) | \
+ PIN_OSPEED_100M(GPIOH_PIN9) | \
+ PIN_OSPEED_100M(GPIOH_PIN10) | \
+ PIN_OSPEED_100M(GPIOH_PIN11) | \
+ PIN_OSPEED_100M(GPIOH_PIN12) | \
+ PIN_OSPEED_100M(GPIOH_PIN13) | \
+ PIN_OSPEED_100M(GPIOH_PIN14) | \
+ PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input pullup).
+ * PI1 - PIN1 (input pullup).
+ * PI2 - PIN2 (input pullup).
+ * PI3 - PIN3 (input pullup).
+ * PI4 - PIN4 (input pullup).
+ * PI5 - PIN5 (input pullup).
+ * PI6 - PIN6 (input pullup).
+ * PI7 - PIN7 (input pullup).
+ * PI8 - PIN8 (input pullup).
+ * PI9 - PIN9 (input pullup).
+ * PI10 - PIN10 (input pullup).
+ * PI11 - PIN11 (input pullup).
+ * PI12 - PIN12 (input pullup).
+ * PI13 - PIN13 (input pullup).
+ * PI14 - PIN14 (input pullup).
+ * PI15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
+ PIN_OSPEED_100M(GPIOI_PIN1) | \
+ PIN_OSPEED_100M(GPIOI_PIN2) | \
+ PIN_OSPEED_100M(GPIOI_PIN3) | \
+ PIN_OSPEED_100M(GPIOI_PIN4) | \
+ PIN_OSPEED_100M(GPIOI_PIN5) | \
+ PIN_OSPEED_100M(GPIOI_PIN6) | \
+ PIN_OSPEED_100M(GPIOI_PIN7) | \
+ PIN_OSPEED_100M(GPIOI_PIN8) | \
+ PIN_OSPEED_100M(GPIOI_PIN9) | \
+ PIN_OSPEED_100M(GPIOI_PIN10) | \
+ PIN_OSPEED_100M(GPIOI_PIN11) | \
+ PIN_OSPEED_100M(GPIOI_PIN12) | \
+ PIN_OSPEED_100M(GPIOI_PIN13) | \
+ PIN_OSPEED_100M(GPIOI_PIN14) | \
+ PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.mk b/os/hal/boards/OLIMEX_STM32_E407/board.mk new file mode 100644 index 000000000..0f9c9e4a7 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_E407/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_E407/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_E407
diff --git a/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg b/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg new file mode 100644 index 000000000..4d4abeb04 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg @@ -0,0 +1,335 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+ <output_path>..</output_path>
+ </configuration_settings>
+ <board_name>Olimex STM32-E407</board_name>
+ <board_id>OLIMEX_STM32_E407</board_id>
+ <board_functions>
+ <sdc_lld_is_card_inserted><![CDATA[ static bool_t last_status = FALSE;
+
+ if (blkIsTransferring(sdcp))
+ return last_status;
+ return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
+ <sdc_lld_is_write_protected>
+<![CDATA[ (void)sdcp;
+ return FALSE;]]></sdc_lld_is_write_protected>
+ </board_functions>
+ <ethernet_phy>
+ <identifier>MII_KS8721_ID</identifier>
+ <bus_type>RMII</bus_type>
+ </ethernet_phy>
+ <clocks HSEFrequency="12000000" HSEBypass="false" LSEFrequency="32768"
+ VDD="330" />
+ <ports>
+ <GPIOA>
+ <pin0 ID="BUTTON_WKUP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="ETH_RMII_REF_CLK" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin2 ID="ETH_RMII_MDIO" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin3 ID="ETH_RMII_MDINT" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="ETH_RMII_CRS_DV" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin8 ID="USB_HS_BUSON" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
+ <pin9 ID="OTG_FS_VBUS" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="OTG_FS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="10" />
+ <pin11 ID="OTG_FS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="10" />
+ <pin12 ID="OTG_FS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="10" />
+ <pin13 ID="JTAG_TMS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin14 ID="JTAG_TCK" Type="PushPull" Speed="Maximum" Resistor="PullDown"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin15 ID="JTAG_TDI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0 ID="USB_FS_BUSON" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Output" Alternate="0" />
+ <pin1 ID="USB_HS_FAULT" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="BOOT1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="JTAG_TDO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin4 ID="JTAG_TRST" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="I2C1_SCL" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="4" />
+ <pin9 ID="I2C1_SDA" Type="OpenDrain" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="4" />
+ <pin10 ID="SPI2_SCK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="5" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="OTG_HS_ID" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin13 ID="OTG_HS_VBUS" Type="PushPull" Speed="Maximum"
+ Resistor="PullDown" Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="OTG_HS_DM" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin15 ID="OTG_HS_DP" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ </GPIOB>
+ <GPIOC>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="ETH_RMII_MDC" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin2 ID="SPI2_MISO" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="5" />
+ <pin3 ID="SPI2_MOSI" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="5" />
+ <pin4 ID="ETH_RMII_RXD0" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin5 ID="ETH_RMII_RXD1" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin6 ID="USART6_TX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="8" />
+ <pin7 ID="USART6_RX" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="8" />
+ <pin8 ID="SD_D0" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin9 ID="SD_D1" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin10 ID="SD_D2" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin11 ID="SD_D3" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin12 ID="SD_CLK" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin13 ID="LED" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Output" Alternate="0" />
+ <pin14 ID="OSC32_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="OSC32_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="SD_CMD" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Alternate" Alternate="12" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="USB_FS_FAULT" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="SPI2_CS" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Output" Alternate="0" />
+ <pin11 ID="ETH_RMII_TXEN" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="ETH_RMII_TXD0" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin14 ID="ETH_RMII_TXD1" Type="PushPull" Speed="Maximum"
+ Resistor="Floating" Level="High" Mode="Alternate" Alternate="11" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOG>
+ <GPIOH>
+ <pin0 ID="OSC_IN" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0"></pin0>
+ <pin1 ID="OSC_OUT" Type="PushPull" Speed="Maximum" Resistor="Floating"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOH>
+ <GPIOI>
+ <pin0 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin1 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin2 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin3 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin4 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin5 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin6 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin7 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin8 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin9 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin10 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin11 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin12 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin13 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin14 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ <pin15 ID="" Type="PushPull" Speed="Maximum" Resistor="PullUp"
+ Level="High" Mode="Input" Alternate="0" />
+ </GPIOI>
+ </ports>
+</board>
diff --git a/os/hal/boards/OLIMEX_STM32_H103/board.c b/os/hal/boards/OLIMEX_STM32_H103/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_H103/board.c @@ -0,0 +1,50 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_H103/board.h b/os/hal/boards/OLIMEX_STM32_H103/board.h new file mode 100644 index 000000000..76c66099d --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_H103/board.h @@ -0,0 +1,132 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM33-H103 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_H103
+#define BOARD_NAME "Olimex STM32-H103"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+
+#define GPIOC_USB_DISC 11
+#define GPIOC_LED 12
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0 - Normal input (BUTTON).
+ * PA2 - Alternate output (USART2 TX).
+ * PA3 - Normal input (USART2 RX).
+ */
+#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC6 - Normal input because there is an external resistor.
+ * PC7 - Normal input because there is an external resistor.
+ * PC11 - Open Drain output (USB disconnect).
+ * PC12 - Push Pull output (LED).
+ */
+#define VAL_GPIOCCRL 0x44888888 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x88837888 /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0 - Normal input (XTAL).
+ * PD1 - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */
+#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
+#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_H103/board.mk b/os/hal/boards/OLIMEX_STM32_H103/board.mk new file mode 100644 index 000000000..040374ffc --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_H103/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_H103/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_H103
diff --git a/os/hal/boards/OLIMEX_STM32_LCD/board.c b/os/hal/boards/OLIMEX_STM32_LCD/board.c new file mode 100644 index 000000000..397ed99b9 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_LCD/board.c @@ -0,0 +1,88 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+ {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
+ {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ (void)sdcp;
+
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+ (void)sdcp;
+
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+ (void)mmcp;
+
+ return TRUE;
+}
+
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+ (void)mmcp;
+
+ return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
+
diff --git a/os/hal/boards/OLIMEX_STM32_LCD/board.h b/os/hal/boards/OLIMEX_STM32_LCD/board.h new file mode 100644 index 000000000..0d510abac --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_LCD/board.h @@ -0,0 +1,196 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-LCD proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_LCD
+#define BOARD_NAME "Olimex STM32-LCD"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_HD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_SPI1NSS 4
+
+#define GPIOB_SPI2NSS 12
+
+#define GPIOA_USB_P 0
+#define GPIOD_USB_DISC 2
+
+#define GPIOE_TFT_RST 2
+#define GPIOD_TFT_LIGHT 13
+#define GPIOC_TFT_YD 0
+#define GPIOC_TFT_YU 1
+#define GPIOC_TFT_XL 2
+#define GPIOC_TFT_XR 3
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0 - Normal input (USB P).
+ * PA2 - Alternate output (USART2 TX).
+ * PA3 - Normal input (USART2 RX).
+ * PA11 - Normal input (USB DM).
+ * PA12 - Normal input (USB DP).
+ */
+#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC0 - Analog Input (TP_YD).
+ * PC1 - Analog Input (TP_YU).
+ * PC2 - Analog Input (TP_XL).
+ * PC3 - Analog Input (TP_XR).
+ * PC8 - Alternate PP 50M (SD_D0).
+ * PC9 - Alternate PP 50M (SD_D1).
+ * PC10 - Alternate PP 50M (SD_D2).
+ * PC11 - Alternate PP 50M (SD_D3).
+ * PC12 - Alternate PP 50M (SD_CLK).
+ * PC14 - Normal input (XTAL).
+ * PC15 - Normal input (XTAL).
+ */
+#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD2 - Alternate PP 50M (SD_CMD)
+ * PD0 - Alternate PP 50M (FSMC_D2)
+ * PD1 - Alternate PP 50M (FSMC_D3)
+ * PD4 - Alternate PP 50M (TFT_RD)
+ * PD5 - Alternate PP 50M (TFT_WR)
+ * PD7 - Alternate PP 50M (TFT_CS)
+ * PD8 - Alternate PP 50M (FSMC_D13)
+ * PD9 - Alternate PP 50M (FSMC_D14)
+ * PD10 - Alternate PP 50M (FSMC_D15)
+ * PD14 - Alternate PP 50M (FSMC_D0)
+ * PD15 - Alternate PP 50M (FSMC_D1)
+ */
+#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */
+#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ * PE2 - Digital Output (TFT_RST)
+ * PE3 - Alternate PP 50M (TFT_RS)
+ * PE7 - Alternate PP 50M (FSMC_D4)
+ * PE8 - Alternate PP 50M (FSMC_D5)
+ * PE9 - Alternate PP 50M (FSMC_D6)
+ * PE10 - Alternate PP 50M (FSMC_D7)
+ * PE11 - Alternate PP 50M (FSMC_D8)
+ * PE12 - Alternate PP 50M (FSMC_D9)
+ * PE13 - Alternate PP 50M (FSMC_D10)
+ * PE14 - Alternate PP 50M (FSMC_D11)
+ * PE15 - Alternate PP 50M (FSMC_D12)
+ */
+#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */
+#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+/*
+ * Port F setup.
+ * Everything input with pull-up expect:
+ */
+#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */
+#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */
+#define VAL_GPIOFODR 0xFFFFFFFF
+
+/*
+ * Port G setup.
+ * Everything input with pull-up expect:
+ */
+#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */
+#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */
+#define VAL_GPIOGODR 0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_LCD/board.mk b/os/hal/boards/OLIMEX_STM32_LCD/board.mk new file mode 100644 index 000000000..c1cc061de --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_LCD/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_LCD/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_LCD
diff --git a/os/hal/boards/OLIMEX_STM32_P103/board.c b/os/hal/boards/OLIMEX_STM32_P103/board.c new file mode 100644 index 000000000..ab992f116 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P103/board.c @@ -0,0 +1,65 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return palReadPad(GPIOC, GPIOC_MMCCP);
+}
+
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return !palReadPad(GPIOC, GPIOC_MMCWP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_P103/board.h b/os/hal/boards/OLIMEX_STM32_P103/board.h new file mode 100644 index 000000000..58f020bcc --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P103/board.h @@ -0,0 +1,156 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-P103 proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_P103
+#define BOARD_NAME "Olimex STM32-P103"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+#define GPIOA_SPI1NSS 4
+
+#define GPIOB_SPI2NSS 12
+
+#define GPIOC_USB_P 4
+#define GPIOC_MMCWP 6
+#define GPIOC_MMCCP 7
+#define GPIOC_CAN_CNTL 10
+#define GPIOC_USB_DISC 11
+#define GPIOC_LED 12
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0 - Normal input (BUTTON).
+ * PA2 - Alternate output (USART2 TX).
+ * PA3 - Normal input (USART2 RX).
+ * PA11 - Normal input (USB DM).
+ * PA12 - Normal input (USB DP).
+ */
+#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB13 - Alternate output (MMC SPI2 SCK).
+ * PB14 - Normal input (MMC SPI2 MISO).
+ * PB15 - Alternate output (MMC SPI2 MOSI).
+ */
+#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0xB4B88888 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC4 - Normal input because there is an external resistor.
+ * PC6 - Normal input because there is an external resistor.
+ * PC7 - Normal input because there is an external resistor.
+ * PC10 - Push Pull output (CAN CNTRL).
+ * PC11 - Push Pull output (USB DISC).
+ * PC12 - Push Pull output (LED).
+ */
+#define VAL_GPIOCCRL 0x44848888 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x88833388 /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0 - Normal input (XTAL).
+ * PD1 - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */
+#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
+#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOC, GPIOC_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOC, GPIOC_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_P103/board.mk b/os/hal/boards/OLIMEX_STM32_P103/board.mk new file mode 100644 index 000000000..701970e84 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P103/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P103/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P103
diff --git a/os/hal/boards/OLIMEX_STM32_P107/board.c b/os/hal/boards/OLIMEX_STM32_P107/board.c new file mode 100644 index 000000000..586c27c13 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P107/board.c @@ -0,0 +1,84 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/*
+ * Card detection through the card internal pull-up on D3.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+ static bool_t last_status = FALSE;
+
+ (void)mmcp;
+ if ((palReadLatch(GPIOA) & PAL_PORT_BIT(GPIOA_SPI3_CS_MMC)) == 0)
+ return last_status;
+ return last_status = (bool_t)palReadPad(GPIOA, GPIOA_SPI3_CS_MMC);
+}
+
+/*
+ * Card write protection detection is not possible, the card is always
+ * reported as not protected.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Several I/O pins are re-mapped:
+ * USART3 to the PD8/PD9 pins.
+ * I2C1 to the PB8/PB9 pins.
+ * SPI3 to the PC10/PC11/PC12 pins.
+ */
+ AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP |
+ AFIO_MAPR_I2C1_REMAP |
+ AFIO_MAPR_SPI3_REMAP;
+}
diff --git a/os/hal/boards/OLIMEX_STM32_P107/board.h b/os/hal/boards/OLIMEX_STM32_P107/board.h new file mode 100644 index 000000000..8bf523d33 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P107/board.h @@ -0,0 +1,193 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-P107 Rev.A evaluation board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_P107_REV_A
+#define BOARD_NAME "Olimex STM32-P107 Rev.A"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 25000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_CL
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_STE101P_ID
+#define BOARD_PHY_RMII
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_SWITCH_WKUP 0
+#define GPIOA_SPI3_CS_MMC 4
+#define GPIOC_LED_STATUS1 6
+#define GPIOC_LED_STATUS2 7
+#define GPIOC_SWITCH_TAMPER 13
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0 - Normal input (WKUP BUTTON).
+ * PA1 - Normal input (ETH_RMII_REF_CLK).
+ * PA2 - Alternate output (ETH_RMII_MDIO).
+ * PA3 - Input with PU (unconnected).
+ * PA4 - Open Drain output (CS_MMC).
+ * PA5 - Input with PU (unconnected).
+ * PA6 - Input with PU (unconnected).
+ * PA7 - Normal input (ETH_RMII_CRS_DV).
+ * PA8 - Alternate output (MCO).
+ * PA9 - Normal input (OTG_VBUS).
+ * PA10 - Normal input (OTG_ID).
+ * PA11 - Normal input (OTG_DM).
+ * PA12 - Normal input (OTG_DP).
+ * PA13 - Normal input (TMS).
+ * PA14 - Normal input (TCK).
+ * PA15 - Normal input (TDI).
+ */
+#define VAL_GPIOACRL 0x48878B44 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x4444444B /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup:
+ * PB0 - Input with PU (unconnected).
+ * PB1 - Input with PU (unconnected).
+ * PB2 - Normal input (BOOT1).
+ * PB3 - Normal input (TDO).
+ * PB4 - Normal input (TRST).
+ * PB5 - Input with PU (unconnected).
+ * PB6 - Input with PU (unconnected).
+ * PB7 - Input with PU (unconnected).
+ * PB8 - Alternate O.D. (I2C1 SCL, remapped).
+ * PB9 - Alternate O.D. (I2C1 SDA, remapped).
+ * PB10 - Input with PU (unconnected).
+ * PB11 - Alternate output (ETH_RMII_TX_EN).
+ * PB12 - Alternate output (ETH_RMII_TXD0).
+ * PB13 - Alternate output (ETH_RMII_TXD1).
+ * PB14 - Input with PU (unconnected).
+ * PB15 - Push Pull output (CS_UEXT).
+ */
+#define VAL_GPIOBCRL 0x88844488 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0x38BBB8FF /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup:
+ * PC0 - Input with PU (unconnected).
+ * PC1 - Alternate output (ETH_MDC).
+ * PC2 - Input with PU (unconnected).
+ * PC3 - Input with PU (unconnected).
+ * PC4 - Normal input (ETH_RMII_RXD0).
+ * PC5 - Normal input (ETH_RMII_RXD1).
+ * PC6 - Push Pull output (STAT1 green LED).
+ * PC7 - Push Pull output (STAT2 yellow LED).
+ * PC8 - Input with PU (unconnected).
+ * PC9 - Input with PU (unconnected).
+ * PC10 - Alternate output (SPI3 SCK).
+ * PC11 - Input with PU (SPI3 MISO).
+ * PC12 - Alternate output (SPI3 MOSI).
+ * PC13 - Normal input (TAMPER).
+ * PC14 - Normal input (OSC32 IN).
+ * PC15 - Normal input (OSC32 OUT).
+ */
+#define VAL_GPIOCCRL 0x334488B8 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x444B8B88 /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFF3F
+
+/*
+ * Port D setup:
+ * PD0 - Input with PU (unconnected).
+ * PD1 - Input with PU (unconnected).
+ * PD2 - Input with PU (unconnected).
+ * PD3 - Input with PU (unconnected).
+ * PD4 - Input with PU (unconnected).
+ * PD5 - Alternate output (USART2 TX, UEXT).
+ * PD6 - Input with PU (USART2 RX, UEXT).
+ * PD7 - Push Pull output (USB_VBUSON).
+ * PD8 - Alternate output (USART2 TX, remapped).
+ * PD9 - Normal input (USART2 RX, remapped).
+ * PD10 - Input with PU (unconnected).
+ * PD11 - Normal input (USART2 CTS, remapped).
+ * PD12 - Alternate output (USART2 RTS, remapped).
+ * PD13 - Input with PU (unconnected).
+ * PD14 - Input with PU (unconnected).
+ * PD15 - Input with PU (unconnected).
+ */
+#define VAL_GPIODCRL 0x38B88888 /* PD7...PD0 */
+#define VAL_GPIODCRH 0x888B484B /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ * PE14 - Normal input (ETH_RMII_MDINT).
+ * PE15 - Normal input (USB_FAULT).
+ */
+#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
+#define VAL_GPIOECRH 0x44888888 /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_P107/board.mk b/os/hal/boards/OLIMEX_STM32_P107/board.mk new file mode 100644 index 000000000..63f70119a --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P107/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P107/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P107
diff --git a/os/hal/boards/OLIMEX_STM32_P407/board.c b/os/hal/boards/OLIMEX_STM32_P407/board.c new file mode 100644 index 000000000..17ef1d54f --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P407/board.c @@ -0,0 +1,78 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+ static bool_t last_status = FALSE;
+ (void)mmcp;
+
+ if ((palReadLatch(GPIOD) & PAL_PORT_BIT(GPIOD_SPI3_CS)) == 0)
+ return last_status;
+ return last_status = (bool_t)palReadPad(GPIOD, GPIOD_SPI3_CS);
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/OLIMEX_STM32_P407/board.h b/os/hal/boards/OLIMEX_STM32_P407/board.h new file mode 100644 index 000000000..66279a8f9 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P407/board.h @@ -0,0 +1,651 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex STM32-P407 board.
+ * NOTE: Part of JTAG signals are used for other functions, this board can be
+ * used using SWD only.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_P407
+#define BOARD_NAME "Olimex STM32-P407"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_KS8721_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board frequencies.
+ * NOTE: The LSE crystal is not fitted by default on the board.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 25000000
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 330
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WKUP 0
+#define GPIOA_ETH_RMII_REF_CLK 1
+#define GPIOA_ETH_RMII_MDIO 2
+#define GPIOA_ETH_RMII_MDINT 3
+#define GPIOA_DCMI_HSYNC 4
+#define GPIOA_LCD_SCK 5
+#define GPIOA_DCMI_PIXCLK 6
+#define GPIOA_ETH_RMII_CRS_DV 7
+#define GPIOA_MCO1 8
+#define GPIOA_OTG_FS_VBUS 9
+#define GPIOA_DCMI_D1 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_I2S3_WS 15
+
+#define GPIOB_LCD_BL 0
+#define GPIOB_BUZ 1
+#define GPIOB_CAM_ENB 2
+#define GPIOB_I2S3_CK 3
+#define GPIOB_LCD_MISO 4
+#define GPIOB_I2S3_SD 5
+#define GPIOB_DCMI_D5 6
+#define GPIOB_DCMI_VSYNC 7
+#define GPIOB_CAN1_RX 8
+#define GPIOB_CAN1_TX 9
+#define GPIOB_USB_FS_FAULT 10
+#define GPIOB_ETH_RMII_TX_EN 11
+#define GPIOB_OTG_HS_ID 12
+#define GPIOB_OTG_HS_VBUS 13
+#define GPIOB_OTG_HS_DM 14
+#define GPIOB_OTG_HS_DP 15
+
+#define GPIOC_TRIM 0
+#define GPIOC_ETH_RMII_MDC 1
+#define GPIOC_USB_FS_VBUSON 2
+#define GPIOC_LCD_MOSI 3
+#define GPIOC_ETH_RMII_RXD0 4
+#define GPIOC_ETH_RMII_RXD1 5
+#define GPIOC_DCMI_D0_US6_TX 6
+#define GPIOC_I2S3_MCK 7
+#define GPIOC_DCMI_D2 8
+#define GPIOC_DCMI_D3 9
+#define GPIOC_SPI3_SCK 10
+#define GPIOC_SPI3_MISO 11
+#define GPIOC_SPI3_MOSI 12
+#define GPIOC_SWITCH_TAMPER 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_USELESS0 0
+#define GPIOD_USELESS1 1
+#define GPIOD_SPI3_CS 2
+#define GPIOD_LCD_RST 3
+#define GPIOD_USELESS4 4
+#define GPIOD_USELESS5 5
+#define GPIOD_LCD_CS 6
+#define GPIOD_USELESS7 7
+#define GPIOD_USART3_TX 8
+#define GPIOD_USART3_RX 9
+#define GPIOD_USELESS10 10
+#define GPIOD_USART3_CTS 11
+#define GPIOD_USART3_RTS 12
+#define GPIOD_USB_HS_FAULT 13
+#define GPIOD_USELESS14 14
+#define GPIOD_USELESS15 15
+
+#define GPIOE_0 0
+#define GPIOE_1 1
+#define GPIOE_TEMP_ALERT 2
+#define GPIOE_USB_HS_VBUSON 3
+#define GPIOE_4 4
+#define GPIOE_5 5
+#define GPIOE_6 6
+#define GPIOE_7 7
+#define GPIOE_8 8
+#define GPIOE_9 9
+#define GPIOE_10 10
+#define GPIOE_11 11
+#define GPIOE_12 12
+#define GPIOE_13 13
+#define GPIOE_14 14
+#define GPIOE_15 15
+
+#define GPIOF_0 0
+#define GPIOF_1 1
+#define GPIOF_2 2
+#define GPIOF_3 3
+#define GPIOF_4 4
+#define GPIOF_5 5
+#define GPIOF_STAT1 6
+#define GPIOF_STAT2 7
+#define GPIOF_STAT3 8
+#define GPIOF_CAM_PWR 9
+#define GPIOF_10 10
+#define GPIOF_CAM_RS 11
+#define GPIOF_12 12
+#define GPIOF_13 13
+#define GPIOF_14 14
+#define GPIOF_15 15
+
+#define GPIOG_0 0
+#define GPIOG_1 1
+#define GPIOG_2 2
+#define GPIOG_3 3
+#define GPIOG_4 4
+#define GPIOG_5 5
+#define GPIOG_RIGHT 6
+#define GPIOG_UP 7
+#define GPIOG_DOWN 8
+#define GPIOG_USART6_RX 9
+#define GPIOG_10 10
+#define GPIOG_LEFT 11
+#define GPIOG_12 12
+#define GPIOG_ETH_RMII_TXD0 13
+#define GPIOG_ETH_RMII_TXD1 14
+#define GPIOG_CENT 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ *
+ * PA0 - GPIOA_BUTTON_WKUP (input floating).
+ * PA1 - GPIOA_ETH_RMII_REF_CLK(alternate 11).
+ * PA2 - GPIOA_ETH_RMII_MDIO (alternate 11).
+ * PA3 - GPIOA_ETH_RMII_MDINT (input floating).
+ * PA4 - GPIOA_DCMI_HSYNC (input pull-up).
+ * PA5 - GPIOA_LCD_SCK (output push-pull).
+ * PA6 - GPIOA_DCMI_PIXCLK (input pull-up).
+ * PA7 - GPIOA_ETH_RMII_CRS_DV (alternate 11).
+ * PA8 - GPIOA_MCO1 (alternate 0).
+ * PA9 - GPIOA_OTG_FS_VBUS (input pull-up).
+ * PA10 - GPIOA_DCMI_D1 (input pull-up).
+ * PA11 - GPIOA_OTG_FS_DM (alternate 10).
+ * PA12 - GPIOA_OTG_FS_DP (alternate 10).
+ * PA13 - GPIOA_SWDIO (alternate 0).
+ * PA14 - GPIOA_SWCLK (alternate 0, pull-down).
+ * PA15 - GPIOA_I2S3_WS (alternate 6).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) | \
+ PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \
+ PIN_MODE_INPUT(GPIOA_DCMI_HSYNC) | \
+ PIN_MODE_OUTPUT(GPIOA_LCD_SCK) | \
+ PIN_MODE_INPUT(GPIOA_DCMI_PIXCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) | \
+ PIN_MODE_ALTERNATE(GPIOA_MCO1) | \
+ PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
+ PIN_MODE_INPUT(GPIOA_DCMI_D1) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_I2S3_WS))
+#define VAL_GPIOA_OTYPER 0x00000000
+#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOA_PUPDR (PIN_PUDR_PULLUP(GPIOA_DCMI_HSYNC) | \
+ PIN_PUDR_PULLUP(GPIOA_DCMI_PIXCLK) | \
+ PIN_PUDR_PULLDOWN(GPIOA_OTG_FS_VBUS) | \
+ PIN_PUDR_PULLUP(GPIOA_DCMI_D1) | \
+ PIN_PUDR_PULLDOWN(GPIOA_SWCLK))
+#define VAL_GPIOA_ODR 0xFFFFFFDF
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_MCO1, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_I2S3_WS, 6))
+
+/*
+ * Port B setup.
+ *
+ * PB0 - GPIOB_LCD_BL (output push-pull).
+ * PB1 - GPIOB_BUZ (output push-pull).
+ * PB2 - GPIOB_CAM_ENB (input floating).
+ * PB3 - GPIOB_I2S3_CK (alternate 6).
+ * PB4 - GPIOB_LCD_MISO (input floating).
+ * PB5 - GPIOB_I2S3_SD (alternate 6).
+ * PB6 - GPIOB_DCMI_D5 (input pull-up).
+ * PB7 - GPIOB_DCMI_VSYNC (input pull-up).
+ * PB8 - GPIOB_CAN1_RX (alternate 9).
+ * PB9 - GPIOB_CAN1_TX (alternate 9).
+ * PB10 - GPIOB_USB_FS_FAULT (input floating).
+ * PB11 - GPIOB_ETH_RMII_TX_EN (alternate 11).
+ * PB12 - GPIOB_OTG_HS_ID (alternate 12).
+ * PB13 - GPIOB_OTG_HS_VBUS (input pull-up).
+ * PB14 - GPIOB_OTG_HS_DM (alternate 12).
+ * PB15 - GPIOB_OTG_HS_DP (alternate 12).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LCD_BL) | \
+ PIN_MODE_OUTPUT(GPIOB_BUZ) | \
+ PIN_MODE_INPUT(GPIOB_CAM_ENB) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2S3_CK) | \
+ PIN_MODE_INPUT(GPIOB_LCD_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2S3_SD) | \
+ PIN_MODE_INPUT(GPIOB_DCMI_D5) | \
+ PIN_MODE_INPUT(GPIOB_DCMI_VSYNC) | \
+ PIN_MODE_ALTERNATE(GPIOB_CAN1_RX) | \
+ PIN_MODE_ALTERNATE(GPIOB_CAN1_TX) | \
+ PIN_MODE_INPUT(GPIOB_USB_FS_FAULT) | \
+ PIN_MODE_ALTERNATE(GPIOB_ETH_RMII_TX_EN) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \
+ PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER 0x00000000
+#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLUP(GPIOB_DCMI_D5) | \
+ PIN_PUDR_PULLUP(GPIOB_DCMI_VSYNC) | \
+ PIN_PUDR_PULLDOWN(GPIOB_OTG_HS_VBUS))
+#define VAL_GPIOB_ODR 0xFFFFFFFC
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_I2S3_CK, 6) | \
+ PIN_AFIO_AF(GPIOB_I2S3_SD, 6))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_CAN1_RX, 9) | \
+ PIN_AFIO_AF(GPIOB_CAN1_TX, 9) | \
+ PIN_AFIO_AF(GPIOB_ETH_RMII_TX_EN, 11) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+
+/*
+ * Port C setup.
+ *
+ * PC0 - GPIOC_TRIM (input floating).
+ * PC1 - GPIOC_ETH_RMII_MDC (alternate 11).
+ * PC2 - GPIOC_USB_FS_VBUSON (output push-pull).
+ * PC3 - GPIOC_LCD_MOSI (output push-pull).
+ * PC4 - GPIOC_ETH_RMII_RXD0 (alternate 11).
+ * PC5 - GPIOC_ETH_RMII_RXD1 (alternate 11).
+ * PC6 - GPIOC_DCMI_D0_US6_TX (alternate 8).
+ * PC7 - GPIOC_I2S3_MCK (alternate 6).
+ * PC8 - GPIOC_DCMI_D2 (input pull-up).
+ * PC9 - GPIOC_DCMI_D3 (input pull-up).
+ * PC10 - GPIOC_SPI3_SCK (alternate 6).
+ * PC11 - GPIOC_SPI3_MISO (alternate 6).
+ * PC12 - GPIOC_SPI3_MOSI (alternate 6).
+ * PC13 - GPIOC_SWITCH_TAMPER (input floating).
+ * PC14 - GPIOC_OSC32_IN (input floating).
+ * PC15 - GPIOC_OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_TRIM) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) | \
+ PIN_MODE_OUTPUT(GPIOC_USB_FS_VBUSON) | \
+ PIN_MODE_OUTPUT(GPIOC_LCD_MOSI) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) | \
+ PIN_MODE_ALTERNATE(GPIOC_DCMI_D0_US6_TX) | \
+ PIN_MODE_ALTERNATE(GPIOC_I2S3_MCK) | \
+ PIN_MODE_INPUT(GPIOC_DCMI_D2) | \
+ PIN_MODE_INPUT(GPIOC_DCMI_D3) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \
+ PIN_MODE_INPUT(GPIOC_SWITCH_TAMPER) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER 0x00000000
+#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOC_PUPDR (PIN_PUDR_PULLUP(GPIOC_DCMI_D2) | \
+ PIN_PUDR_PULLUP(GPIOC_DCMI_D3))
+#define VAL_GPIOC_ODR 0xFFFFFFF3
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \
+ PIN_AFIO_AF(GPIOC_DCMI_D0_US6_TX, 8) | \
+ PIN_AFIO_AF(GPIOC_I2S3_MCK, 6))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SPI3_SCK, 6) | \
+ PIN_AFIO_AF(GPIOC_SPI3_MISO, 6) | \
+ PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6))
+
+/*
+ * Port D setup.
+ *
+ * PD0 - GPIOD_USELESS0 (input pull-up).
+ * PD1 - GPIOD_USELESS1 (input pull-up).
+ * PD2 - GPIOD_SPI3_CS (output opendrain).
+ * PD3 - GPIOD_LCD_RST (output push-pull).
+ * PD4 - GPIOD_USELESS4 (input pull-up).
+ * PD5 - GPIOD_USELESS5 (input pull-up).
+ * PD6 - GPIOD_LCD_CS (output push-pull).
+ * PD7 - GPIOD_USELESS7 (input pull-up).
+ * PD8 - GPIOD_USART3_TX (alternate 8).
+ * PD9 - GPIOD_USART3_RX (alternate 8).
+ * PD10 - GPIOD_USELESS10 (input pull-up).
+ * PD11 - GPIOD_USART3_CTS (alternate 8).
+ * PD12 - GPIOD_USART3_RTS (alternate 8).
+ * PD13 - GPIOD_USB_HS_FAULT (input floating).
+ * PD14 - GPIOD_USELESS14 (input pull-up).
+ * PD15 - GPIOD_USELESS15 (input pull-up).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_USELESS0) | \
+ PIN_MODE_INPUT(GPIOD_USELESS1) | \
+ PIN_MODE_OUTPUT(GPIOD_SPI3_CS) | \
+ PIN_MODE_OUTPUT(GPIOD_LCD_RST) | \
+ PIN_MODE_INPUT(GPIOD_USELESS4) | \
+ PIN_MODE_INPUT(GPIOD_USELESS5) | \
+ PIN_MODE_OUTPUT(GPIOD_LCD_CS) | \
+ PIN_MODE_INPUT(GPIOD_USELESS7) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \
+ PIN_MODE_INPUT(GPIOD_USELESS10) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_CTS) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RTS) | \
+ PIN_MODE_INPUT(GPIOD_USB_HS_FAULT) | \
+ PIN_MODE_INPUT(GPIOD_USELESS14) | \
+ PIN_MODE_INPUT(GPIOD_USELESS15))
+#define VAL_GPIOD_OTYPER PIN_OTYPE_OPENDRAIN(GPIOD_SPI3_CS)
+#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(GPIOD_USELESS0) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS1) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS4) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS5) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS7) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS10) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS14) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS15))
+#define VAL_GPIOD_ODR 0xFFFFFFFF
+#define VAL_GPIOD_AFRL 0x00000000
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 7) | \
+ PIN_AFIO_AF(GPIOD_USART3_RX, 7) | \
+ PIN_AFIO_AF(GPIOD_USART3_CTS, 7) | \
+ PIN_AFIO_AF(GPIOD_USART3_RTS, 7))
+
+/*
+ * Port E setup.
+ *
+ * PE0 - GPIOE_0 (input pull-up).
+ * PE1 - GPIOE_1 (input pull-up).
+ * PE2 - GPIOE_TEMP_ALERT (input floating).
+ * PE3 - GPIOE_USB_HS_VBUSON (output push-pull).
+ * PE4 - GPIOE_4 (input pull-up).
+ * PE5 - GPIOE_5 (input pull-up).
+ * PE6 - GPIOE_6 (input pull-up).
+ * PE7 - GPIOE_7 (input pull-up).
+ * PE8 - GPIOE_8 (input pull-up).
+ * PE9 - GPIOE_9 (input pull-up).
+ * PE10 - GPIOE_10 (input pull-up).
+ * PE11 - GPIOE_11 (input pull-up).
+ * PE12 - GPIOE_12 (input pull-up).
+ * PE13 - GPIOE_13 (input pull-up).
+ * PE14 - GPIOE_14 (input pull-up).
+ * PE15 - GPIOE_15 (input pull-up).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_0) | \
+ PIN_MODE_INPUT(GPIOE_1) | \
+ PIN_MODE_INPUT(GPIOE_TEMP_ALERT) | \
+ PIN_MODE_OUTPUT(GPIOE_USB_HS_VBUSON) | \
+ PIN_MODE_INPUT(GPIOE_4) | \
+ PIN_MODE_INPUT(GPIOE_5) | \
+ PIN_MODE_INPUT(GPIOE_6) | \
+ PIN_MODE_INPUT(GPIOE_7) | \
+ PIN_MODE_INPUT(GPIOE_8) | \
+ PIN_MODE_INPUT(GPIOE_9) | \
+ PIN_MODE_INPUT(GPIOE_10) | \
+ PIN_MODE_INPUT(GPIOE_11) | \
+ PIN_MODE_INPUT(GPIOE_12) | \
+ PIN_MODE_INPUT(GPIOE_13) | \
+ PIN_MODE_INPUT(GPIOE_14) | \
+ PIN_MODE_INPUT(GPIOE_15))
+#define VAL_GPIOE_OTYPER 0x00000000
+#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOE_PUPDR (PIN_PUDR_PULLUP(GPIOE_0) | \
+ PIN_PUDR_PULLUP(GPIOE_1) | \
+ PIN_PUDR_PULLUP(GPIOE_4) | \
+ PIN_PUDR_PULLUP(GPIOE_5) | \
+ PIN_PUDR_PULLUP(GPIOE_6) | \
+ PIN_PUDR_PULLUP(GPIOE_7) | \
+ PIN_PUDR_PULLUP(GPIOE_8) | \
+ PIN_PUDR_PULLUP(GPIOE_9) | \
+ PIN_PUDR_PULLUP(GPIOE_10) | \
+ PIN_PUDR_PULLUP(GPIOE_11) | \
+ PIN_PUDR_PULLUP(GPIOE_12) | \
+ PIN_PUDR_PULLUP(GPIOE_13) | \
+ PIN_PUDR_PULLUP(GPIOE_14) | \
+ PIN_PUDR_PULLUP(GPIOE_15))
+#define VAL_GPIOE_ODR 0xFFFFFFF7
+#define VAL_GPIOE_AFRL 0x00000000
+#define VAL_GPIOE_AFRH 0x00000000
+
+/*
+ * Port F setup.
+ *
+ * PF0 - GPIOF_0 (input pull-up).
+ * PF1 - GPIOF_1 (input pull-up).
+ * PF2 - GPIOF_2 (input pull-up).
+ * PF3 - GPIOF_3 (input pull-up).
+ * PF4 - GPIOF_4 (input pull-up).
+ * PF5 - GPIOF_5 (input pull-up).
+ * PF6 - GPIOF_STAT1 (output push-pull).
+ * PF7 - GPIOF_STAT2 (output push-pull).
+ * PF8 - GPIOF_STAT3 (output push-pull).
+ * PF9 - GPIOF_CAM_PWR (output push-pull).
+ * PF10 - GPIOF_10 (input pull-up).
+ * PF11 - GPIOF_CAM_RS (output push-pull).
+ * PF12 - GPIOF_12 (input pull-up).
+ * PF13 - GPIOF_13 (input pull-up).
+ * PF14 - GPIOF_14 (input pull-up).
+ * PF15 - GPIOF_15 (input pull-up).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_0) | \
+ PIN_MODE_INPUT(GPIOF_1) | \
+ PIN_MODE_INPUT(GPIOF_2) | \
+ PIN_MODE_INPUT(GPIOF_3) | \
+ PIN_MODE_INPUT(GPIOF_4) | \
+ PIN_MODE_INPUT(GPIOF_5) | \
+ PIN_MODE_OUTPUT(GPIOF_STAT1) | \
+ PIN_MODE_OUTPUT(GPIOF_STAT2) | \
+ PIN_MODE_OUTPUT(GPIOF_STAT3) | \
+ PIN_MODE_OUTPUT(GPIOF_CAM_PWR) | \
+ PIN_MODE_INPUT(GPIOF_10) | \
+ PIN_MODE_OUTPUT(GPIOF_CAM_RS) | \
+ PIN_MODE_INPUT(GPIOF_12) | \
+ PIN_MODE_INPUT(GPIOF_13) | \
+ PIN_MODE_INPUT(GPIOF_14) | \
+ PIN_MODE_INPUT(GPIOF_15))
+#define VAL_GPIOF_OTYPER 0x00000000
+#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOF_PUPDR (PIN_PUDR_PULLUP(GPIOF_0) | \
+ PIN_PUDR_PULLUP(GPIOF_1) | \
+ PIN_PUDR_PULLUP(GPIOF_2) | \
+ PIN_PUDR_PULLUP(GPIOF_3) | \
+ PIN_PUDR_PULLUP(GPIOF_4) | \
+ PIN_PUDR_PULLUP(GPIOF_5) | \
+ PIN_PUDR_PULLUP(GPIOF_10) | \
+ PIN_PUDR_PULLUP(GPIOF_12) | \
+ PIN_PUDR_PULLUP(GPIOF_13) | \
+ PIN_PUDR_PULLUP(GPIOF_14) | \
+ PIN_PUDR_PULLUP(GPIOF_15))
+#define VAL_GPIOF_ODR 0xFFFFFC3F
+#define VAL_GPIOF_AFRL 0x00000000
+#define VAL_GPIOF_AFRH 0x00000000
+
+/*
+ * Port G setup.
+ *
+ * PG0 - GPIOG_0 (input pull-up).
+ * PG1 - GPIOG_1 (input pull-up).
+ * PG2 - GPIOG_2 (input pull-up).
+ * PG3 - GPIOG_3 (input pull-up).
+ * PG4 - GPIOG_4 (input pull-up).
+ * PG5 - GPIOG_5 (input pull-up).
+ * PG6 - GPIOG_RIGHT (input floating).
+ * PG7 - GPIOG_UP (input floating).
+ * PG8 - GPIOG_DOWN (input floating).
+ * PG9 - GPIOG_USART6_RX (alternate 8).
+ * PG10 - GPIOG_10 (input pull-up).
+ * PG11 - GPIOG_LEFT (input floating).
+ * PG12 - GPIOG_12 (input pull-up).
+ * PG13 - GPIOG_ETH_RMII_TXD0 (alternate 11).
+ * PG14 - GPIOG_ETH_RMII_TXD1 (alternate 11).
+ * PG15 - GPIOG_CENT (input pull-up).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_0) | \
+ PIN_MODE_INPUT(GPIOG_1) | \
+ PIN_MODE_INPUT(GPIOG_2) | \
+ PIN_MODE_INPUT(GPIOG_3) | \
+ PIN_MODE_INPUT(GPIOG_4) | \
+ PIN_MODE_INPUT(GPIOG_5) | \
+ PIN_MODE_INPUT(GPIOG_RIGHT) | \
+ PIN_MODE_INPUT(GPIOG_UP) | \
+ PIN_MODE_INPUT(GPIOG_DOWN) | \
+ PIN_MODE_ALTERNATE(GPIOG_USART6_RX) | \
+ PIN_MODE_INPUT(GPIOG_10) | \
+ PIN_MODE_INPUT(GPIOG_LEFT) | \
+ PIN_MODE_INPUT(GPIOG_12) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) | \
+ PIN_MODE_INPUT(GPIOG_CENT))
+#define VAL_GPIOG_OTYPER 0x00000000
+#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOG_PUPDR (PIN_PUDR_PULLUP(GPIOG_0) | \
+ PIN_PUDR_PULLUP(GPIOG_1) | \
+ PIN_PUDR_PULLUP(GPIOG_2) | \
+ PIN_PUDR_PULLUP(GPIOG_3) | \
+ PIN_PUDR_PULLUP(GPIOG_4) | \
+ PIN_PUDR_PULLUP(GPIOG_5) | \
+ PIN_PUDR_PULLUP(GPIOG_10) | \
+ PIN_PUDR_PULLUP(GPIOG_12))
+#define VAL_GPIOG_ODR 0xFFFFFFFF
+#define VAL_GPIOG_AFRL 0x00000000
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_USART6_RX, 8) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11))
+
+/*
+ * Port H setup.
+ * All input with pull-up except:
+ * PH0 - GPIOH_OSC_IN (input floating).
+ * PH1 - GPIOH_OSC_OUT (input floating).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(2) | \
+ PIN_MODE_INPUT(3) | \
+ PIN_MODE_INPUT(4) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_INPUT(8) | \
+ PIN_MODE_INPUT(9) | \
+ PIN_MODE_INPUT(10) | \
+ PIN_MODE_INPUT(11) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_INPUT(13) | \
+ PIN_MODE_INPUT(14) | \
+ PIN_MODE_INPUT(15))
+#define VAL_GPIOH_OTYPER 0x00000000
+#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(8) | \
+ PIN_PUDR_PULLUP(9) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+#define VAL_GPIOH_ODR 0xFFFFFFFF
+#define VAL_GPIOH_AFRL 0x00000000
+#define VAL_GPIOH_AFRH 0x00000000
+
+/*
+ * Port I setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOI_MODER 0x00000000
+#define VAL_GPIOI_OTYPER 0x00000000
+#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOI_PUPDR (PIN_PUDR_PULLUP(0) | \
+ PIN_PUDR_PULLUP(1) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(8) | \
+ PIN_PUDR_PULLUP(9) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+#define VAL_GPIOI_ODR 0xFFFFFFFF
+#define VAL_GPIOI_AFRL 0x00000000
+#define VAL_GPIOI_AFRH 0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/OLIMEX_STM32_P407/board.mk b/os/hal/boards/OLIMEX_STM32_P407/board.mk new file mode 100644 index 000000000..b1e5aafe2 --- /dev/null +++ b/os/hal/boards/OLIMEX_STM32_P407/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P407/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P407
diff --git a/os/hal/boards/RAISONANCE_REVA_STM8S/board.c b/os/hal/boards/RAISONANCE_REVA_STM8S/board.c new file mode 100644 index 000000000..33e1fa1e9 --- /dev/null +++ b/os/hal/boards/RAISONANCE_REVA_STM8S/board.c @@ -0,0 +1,78 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+ROMCONST PALConfig pal_default_config =
+{
+ {
+ {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
+ {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
+ {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
+ {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
+ {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
+ {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+ {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
+ }
+};
+#endif
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK (SYSCLK / 16)
+#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * TIM2 interrupt handler.
+ */
+CH_IRQ_HANDLER(13) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ TIM2->SR1 = 0;
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * TIM2 initialization as system tick.
+ */
+ CLK->PCKENR1 |= CLK_PCKENR1_TIM2;
+ TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/
+ TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8);
+ TIM2->ARRL = (uint8_t)(TIM2_ARR);
+ TIM2->CNTRH = 0;
+ TIM2->CNTRL = 0;
+ TIM2->SR1 = 0;
+ TIM2->IER = TIM2_IER_UIE;
+ TIM2->CR1 = TIM2_CR1_CEN;
+}
diff --git a/os/hal/boards/RAISONANCE_REVA_STM8S/board.h b/os/hal/boards/RAISONANCE_REVA_STM8S/board.h new file mode 100644 index 000000000..d61e50513 --- /dev/null +++ b/os/hal/boards/RAISONANCE_REVA_STM8S/board.h @@ -0,0 +1,184 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Raisonance REva V3 + STM8S208RB daughter board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_REVA_V3_STM8S208RB
+#define BOARD_NAME "Raisonance REva V3 + STM8S208RB"
+
+/*
+ * Board frequencies.
+ */
+#define HSECLK 0
+
+/*
+ * MCU model used on the board.
+ */
+#define STM8S208
+
+/*
+ * Pin definitions.
+ */
+#define PA_OSCIN 1
+#define PA_J2_25 2 /* It is also OSCOUT. */
+#define PA_J2_27 3
+#define PA_RX 4
+#define PA_TX 5
+
+#define PB_LED(n) (n)
+#define PB_LCD_D0 0
+#define PB_LCD_D1 1
+#define PB_LCD_CSB 2
+#define PB_LCD_RESB 3
+
+#define PC_ADC_ETR 0
+#define PC_J2_51 1
+#define PC_J2_53 2
+#define PC_J2_55 3
+#define PC_J2_57 4
+#define PC_SCK 5
+#define PC_MOSI 6
+#define PC_MISO 7
+
+#define PD_J2_69 0
+#define PD_J2_21 1
+#define PD_J2_67 2
+#define PD_J2_65 3
+#define PD_PWM 4
+#define PD_J2_63 5
+#define PD_J2_61 6
+#define PD_J2_59 7
+
+#define PE_P2_49 0
+#define PE_SCL 1
+#define PE_SDA 2
+#define PE_P2_47 3
+#define PE_P2_45 4
+#define PE_P2_43 5
+#define PE_P2_41 6
+#define PE_P2_39 7
+
+#define PF_J2_37 0
+#define PF_J2_35 1
+#define PF_J2_33 2
+#define PF_J2_31 3
+#define PF_ANA_IN1 4
+#define PF_ANA_IN2 5
+#define PF_ANA_TEMP 6
+#define PF_ANA_POT 7
+
+#define PG_CAN_TX 0
+#define PG_CAN_RX 1
+#define PG_BT5 2
+#define PG_BT6 3
+#define PG_SW4 4
+#define PG_SW3 5
+#define PG_SW2 6
+#define PG_SW1 7
+
+#define PI_J2_71 0
+
+/*
+ * Port A initial setup.
+ */
+#define VAL_GPIOAODR (1 << PA_TX) /* PA_TX initially to 1. */
+#define VAL_GPIOADDR (1 << PA_TX) /* PA_TX output, others inputs. */
+#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */
+#define VAL_GPIOACR2 0
+
+/*
+ * Port B initial setup.
+ */
+#define VAL_GPIOBODR 0xFF /* Initially all set to high. */
+#define VAL_GPIOBDDR 0xFF /* All outputs. */
+#define VAL_GPIOBCR1 0xFF /* All push-pull. */
+#define VAL_GPIOBCR2 0
+
+/*
+ * Port C initial setup.
+ */
+#define VAL_GPIOCODR 0
+#define VAL_GPIOCDDR 0 /* All inputs. */
+#define VAL_GPIOCCR1 0xFF /* All pull-up. */
+#define VAL_GPIOCCR2 0
+
+/*
+ * Port D initial setup.
+ */
+#define VAL_GPIODODR 0
+#define VAL_GPIODDDR 0 /* All inputs. */
+#define VAL_GPIODCR1 0xFF /* All pull-up. */
+#define VAL_GPIODCR2 0
+
+/*
+ * Port E initial setup.
+ */
+#define VAL_GPIOEODR 0
+#define VAL_GPIOEDDR 0 /* All inputs. */
+#define VAL_GPIOECR1 0xFF /* All pull-up. */
+#define VAL_GPIOECR2 0
+
+/*
+ * Port F initial setup.
+ */
+#define VAL_GPIOFODR 0
+#define VAL_GPIOFDDR 0 /* All inputs. */
+#define VAL_GPIOFCR1 0xFF /* All pull-up. */
+#define VAL_GPIOFCR2 0
+
+/*
+ * Port G initial setup.
+ */
+#define VAL_GPIOGODR (1 << PG_CAN_TX)/* CAN_TX initially to 1. */
+#define VAL_GPIOGDDR (1 << PG_CAN_TX)/* CAN_TX output, others inputs. */
+#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */
+#define VAL_GPIOGCR2 0
+
+/*
+ * Port H initial setup (dummy, not present).
+ */
+#define VAL_GPIOHODR 0
+#define VAL_GPIOHDDR 0 /* All inputs. */
+#define VAL_GPIOHCR1 0xFF /* All pull-up. */
+#define VAL_GPIOHCR2 0
+
+/*
+ * Port I initial setup.
+ */
+#define VAL_GPIOIODR 0
+#define VAL_GPIOIDDR 0 /* All inputs. */
+#define VAL_GPIOICR1 0xFF /* All pull-up. */
+#define VAL_GPIOICR2 0
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.c b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.c new file mode 100644 index 000000000..2a3dc015b --- /dev/null +++ b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.c @@ -0,0 +1,109 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
+#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+ (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
+ {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
+#endif
+};
+#endif
+
+/*
+ * SYS IRQ handling here.
+ */
+static CH_IRQ_HANDLER(SYSIrqHandler) {
+
+ CH_IRQ_PROLOGUE();
+
+ if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
+ (void) AT91C_BASE_PITC->PITC_PIVR;
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+ }
+
+#if USE_SAM7_DBGU_UART
+ if (AT91C_BASE_DBGU->DBGU_CSR &
+ (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE | AT91C_US_RXBRK)) {
+ sd_lld_serve_interrupt(&SDDBG);
+ }
+#endif
+ AT91C_BASE_AIC->AIC_EOICR = 0;
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ /* Watchdog disabled.*/
+ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+ at91sam7_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return !palReadPad(IOPORT2, PIOB_MMC_CP);
+}
+
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return palReadPad(IOPORT2, PIOB_MMC_WP);
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * PIT Initialization.
+ */
+ AIC_ConfigureIT(AT91C_ID_SYS,
+ AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1),
+ SYSIrqHandler);
+ AIC_EnableIT(AT91C_ID_SYS);
+ AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1;
+ AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+
+ /*
+ * RTS/CTS pins enabled for USART0 only.
+ */
+ AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0;
+ AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+ AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+}
diff --git a/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.h b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.h new file mode 100644 index 000000000..1bb61e40c --- /dev/null +++ b/os/hal/boards/STUDIEL_AT91SAM7A3_EK/board.h @@ -0,0 +1,93 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Studiel AT91SAM7A3-EK board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_STUDIEL_AT91SAM7A3_EK
+#define BOARD_NAME "Studiel AT91SAM7A3-EK eval. board"
+
+/*
+ * Select your platform by modifying the following line.
+ */
+#if !defined(SAM7A3_PLATFORM)
+#define SAM7_PLATFORM SAM7A3
+#endif
+
+#include "at91sam7.h"
+
+#define CLK 18432000
+#define MCK 48054857
+
+/*
+ * I/O definitions.
+ */
+#define PIOA_RXD0 2
+#define PIOA_RXD0_MASK (1 << PIOA_RXD0)
+#define PIOA_TXD0 3
+#define PIOA_TXD0_MASK (1 << PIOA_TXD0)
+#define PIOA_LED1 20
+#define PIOA_LED1_MASK (1 << PIOA_LED1)
+#define PIOA_LED2 21
+#define PIOA_LED2_MASK (1 << PIOA_LED2)
+#define PIOA_LED3 24
+#define PIOA_LED3_MASK (1 << PIOA_LED3)
+#define PIOA_LED4 25
+#define PIOA_LED4_MASK (1 << PIOA_LED4)
+// mmc-spi
+#define PIOA_SPI0_NSS 14
+#define PIOA_SPI0_NSS_MASK (1 << PIOA_SPI0_NSS)
+#define PIOA_SPI0_MISO 15
+#define PIOA_SPI0_MISO_MASK (1 << PIOA_SPI0_MISO)
+#define PIOA_SPI0_MOSI 16
+#define PIOA_SPI0_MOSI_MASK (1 << PIOA_SPI0_MOSI)
+#define PIOA_SPI0_CLK 17
+#define PIOA_SPI0_CLK_MASK (1 << PIOA_SPI0_CLK)
+
+/*
+ * Initial I/O setup.
+ */
+/* Output data. */
+#define VAL_PIOA_ODSR 0x00000000
+/* Direction. */
+#define VAL_PIOA_OSR 0x00000000 | PIOA_LED1_MASK | PIOA_LED2_MASK | \
+ PIOA_LED3_MASK | PIOA_LED4_MASK
+/* Pull-up. */
+#define VAL_PIOA_PUSR 0xFFFFFFFF
+
+#define VAL_PIOB_ODSR 0x00000000 /* Output data. */
+#define VAL_PIOB_OSR 0x00000000 /* Direction. */
+#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560BC/board.c b/os/hal/boards/ST_EVB_SPC560BC/board.c new file mode 100644 index 000000000..5c067606b --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560BC/board.c @@ -0,0 +1,67 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+ {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_E, PE_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_E, PE_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_E, PE_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/**
+ * @brief PAL setup.
+ */
+const PALConfig pal_default_config = {
+ PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
+ spc_siu_init,
+ spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_EVB_SPC560BC/board.h b/os/hal/boards/ST_EVB_SPC560BC/board.h new file mode 100644 index 000000000..70e3ee548 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560BC/board.h @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560B/Cxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC560BC
+#define BOARD_NAME "Generic SPC560B/Cxx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK 8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX 2
+#define PB_LIN0_RDX 3
+
+#define PE_BUTTON1 0
+#define PE_BUTTON2 1
+#define PE_BUTTON3 2
+#define PE_BUTTON4 3
+
+#define PE_LED1 4
+#define PE_LED2 5
+#define PE_LED3 6
+#define PE_LED4 7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin) (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560BC/board.mk b/os/hal/boards/ST_EVB_SPC560BC/board.mk new file mode 100644 index 000000000..92aadc984 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560BC/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC560BC/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC560BC
diff --git a/os/hal/boards/ST_EVB_SPC560D/board.c b/os/hal/boards/ST_EVB_SPC560D/board.c new file mode 100644 index 000000000..fc5f2c6bc --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560D/board.c @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+ {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_E, PE_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_E, PE_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_E, PE_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_E, PE_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0
+};
+
+/**
+ * @brief PAL setup.
+ */
+const PALConfig pal_default_config = {
+ PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
+ spc_siu_init,
+ spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_EVB_SPC560D/board.h b/os/hal/boards/ST_EVB_SPC560D/board.h new file mode 100644 index 000000000..bca6f7245 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560D/board.h @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560Dxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC560D
+#define BOARD_NAME "Generic SPC560Dxx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK 8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX 2
+#define PB_LIN0_RDX 3
+
+#define PE_BUTTON1 0
+#define PE_BUTTON2 1
+#define PE_BUTTON3 2
+#define PE_BUTTON4 3
+
+#define PE_LED1 4
+#define PE_LED2 5
+#define PE_LED3 6
+#define PE_LED4 7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin) (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560D/board.mk b/os/hal/boards/ST_EVB_SPC560D/board.mk new file mode 100644 index 000000000..8a18b37df --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560D/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC560D/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC560D
diff --git a/os/hal/boards/ST_EVB_SPC560P/board.c b/os/hal/boards/ST_EVB_SPC560P/board.c new file mode 100644 index 000000000..5410436bb --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560P/board.c @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+ {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_D, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_D, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_D, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0
+};
+
+/**
+ * @brief PAL setup.
+ */
+const PALConfig pal_default_config = {
+ PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
+ spc_siu_init,
+ spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_EVB_SPC560P/board.h b/os/hal/boards/ST_EVB_SPC560P/board.h new file mode 100644 index 000000000..a02225c13 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560P/board.h @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560Pxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC560P
+#define BOARD_NAME "Generic SPC560Pxx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK 40000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX 2
+#define PB_LIN0_RDX 3
+
+#define PD_BUTTON1 0
+#define PD_BUTTON2 1
+#define PD_BUTTON3 2
+#define PD_BUTTON4 3
+
+#define PD_LED1 4
+#define PD_LED2 5
+#define PD_LED3 6
+#define PD_LED4 7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin) (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC560P/board.mk b/os/hal/boards/ST_EVB_SPC560P/board.mk new file mode 100644 index 000000000..01d5f533b --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC560P/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC560P/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC560P
diff --git a/os/hal/boards/ST_EVB_SPC563M/board.c b/os/hal/boards/ST_EVB_SPC563M/board.c new file mode 100644 index 000000000..523d1d7e5 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC563M/board.c @@ -0,0 +1,59 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+ {PCR(PORT5, P5_ESCI_A_TX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT5, P5_ESCI_A_RX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT11, P11_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT11, P11_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT11, P11_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT11, P11_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {-1, 0, 0}
+};
+
+/**
+ * @brief PAL setup.
+ */
+const PALConfig pal_default_config = {
+ spc_siu_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_EVB_SPC563M/board.h b/os/hal/boards/ST_EVB_SPC563M/board.h new file mode 100644 index 000000000..3a258f2f9 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC563M/board.h @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC563Mxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC563M
+#define BOARD_NAME "Generic SPC563Mxx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK 8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define P5_ESCI_A_TX 9
+#define P5_ESCI_A_RX 10
+
+#define P11_BUTTON1 3
+#define P11_BUTTON2 5
+#define P11_BUTTON3 7
+#define P11_BUTTON4 9
+
+#define P11_LED1 12
+#define P11_LED2 13
+#define P11_LED3 14
+#define P11_LED4 15
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin) (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC563M/board.mk b/os/hal/boards/ST_EVB_SPC563M/board.mk new file mode 100644 index 000000000..63b4368ec --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC563M/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC563M/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC563M
diff --git a/os/hal/boards/ST_EVB_SPC564A/board.c b/os/hal/boards/ST_EVB_SPC564A/board.c new file mode 100644 index 000000000..523d1d7e5 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC564A/board.c @@ -0,0 +1,59 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+ {PCR(PORT5, P5_ESCI_A_TX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT5, P5_ESCI_A_RX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT11, P11_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT11, P11_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT11, P11_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT11, P11_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT11, P11_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {-1, 0, 0}
+};
+
+/**
+ * @brief PAL setup.
+ */
+const PALConfig pal_default_config = {
+ spc_siu_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ spc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_EVB_SPC564A/board.h b/os/hal/boards/ST_EVB_SPC564A/board.h new file mode 100644 index 000000000..67084dd79 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC564A/board.h @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC564Axx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC564A
+#define BOARD_NAME "Generic SPC564Axx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK 8000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define P5_ESCI_A_TX 9
+#define P5_ESCI_A_RX 10
+
+#define P11_BUTTON1 3
+#define P11_BUTTON2 5
+#define P11_BUTTON3 7
+#define P11_BUTTON4 9
+
+#define P11_LED1 12
+#define P11_LED2 13
+#define P11_LED3 14
+#define P11_LED4 15
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin) (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC564A/board.mk b/os/hal/boards/ST_EVB_SPC564A/board.mk new file mode 100644 index 000000000..1dc4a1117 --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC564A/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC564A/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC564A
diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.c b/os/hal/boards/ST_EVB_SPC56EL/board.c new file mode 100644 index 000000000..7373f595d --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC56EL/board.c @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {-1, 0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+ {PCR(PORT_B, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PORT_B, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PORT_D, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_D, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_D, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PORT_D, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {-1, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIUL_NUM_PADSELS] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/**
+ * @brief PAL setup.
+ */
+const PALConfig pal_default_config = {
+ PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
+ spc_siu_init,
+ spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ spc_early_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.h b/os/hal/boards/ST_EVB_SPC56EL/board.h new file mode 100644 index 000000000..5c64e99bb --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC56EL/board.h @@ -0,0 +1,68 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560Pxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC56EL
+#define BOARD_NAME "Generic SPC56ELxx"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK 40000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX 2
+#define PB_LIN0_RDX 3
+
+#define PD_BUTTON1 0
+#define PD_BUTTON2 1
+#define PD_BUTTON3 2
+#define PD_BUTTON4 3
+
+#define PD_LED1 4
+#define PD_LED2 5
+#define PD_LED3 6
+#define PD_LED4 7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin) (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_EVB_SPC56EL/board.mk b/os/hal/boards/ST_EVB_SPC56EL/board.mk new file mode 100644 index 000000000..8e5c03bce --- /dev/null +++ b/os/hal/boards/ST_EVB_SPC56EL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_EVB_SPC56EL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_EVB_SPC56EL
diff --git a/os/hal/boards/ST_STM3210C_EVAL/board.c b/os/hal/boards/ST_STM3210C_EVAL/board.c new file mode 100644 index 000000000..030d2f9ae --- /dev/null +++ b/os/hal/boards/ST_STM3210C_EVAL/board.c @@ -0,0 +1,55 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * Remap USART2 to the PD5/PD6 pins.
+ */
+ AFIO->MAPR |= AFIO_MAPR_USART2_REMAP;
+}
diff --git a/os/hal/boards/ST_STM3210C_EVAL/board.h b/os/hal/boards/ST_STM3210C_EVAL/board.h new file mode 100644 index 000000000..2193179b8 --- /dev/null +++ b/os/hal/boards/ST_STM3210C_EVAL/board.h @@ -0,0 +1,128 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the STMicroelectronics STM3210C-EVAL evaluation board.
+ */
+
+#define GPIOD_LED1 7
+#define GPIOD_LED2 13
+#define GPIOD_LED3 3
+#define GPIOD_LED4 4
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM3210C_EVAL
+#define BOARD_NAME "ST STM3210C-EVAL"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 25000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_CL
+
+/*
+ * IO pins assignments.
+ * *********************TO BE COMPLETED*********************
+ */
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input except:
+ */
+#define VAL_GPIOACRL 0x44444444 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x44444444 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input except:
+ */
+#define VAL_GPIOBCRL 0x44444444 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0x44444444 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input except:
+ */
+#define VAL_GPIOCCRL 0x44444444 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x44444444 /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input except:
+ * PD5 - USART2TX (remapped) AF PP Output
+ * PD6 - USART2RX (remapped) Digital Input
+ * PD7 - LED (LD1) PP Output
+ */
+#define VAL_GPIODCRL 0x34B33444 /* PD7...PD0 */
+#define VAL_GPIODCRH 0x44344444 /* PD15...PD8 */
+#define VAL_GPIODODR 0x0000DF67
+
+/*
+ * Port E setup.
+ * Everything input except:
+ */
+#define VAL_GPIOECRL 0x44444444 /* PE7...PE0 */
+#define VAL_GPIOECRH 0x44344444 /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM3210C_EVAL/board.mk b/os/hal/boards/ST_STM3210C_EVAL/board.mk new file mode 100644 index 000000000..eaa17162b --- /dev/null +++ b/os/hal/boards/ST_STM3210C_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM3210C_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM3210C_EVAL
diff --git a/os/hal/boards/ST_STM3210E_EVAL/board.c b/os/hal/boards/ST_STM3210E_EVAL/board.c new file mode 100644 index 000000000..95f58e3b0 --- /dev/null +++ b/os/hal/boards/ST_STM3210E_EVAL/board.c @@ -0,0 +1,68 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+ {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
+ {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC
+/* Board-related functions related to the SDC driver.*/
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ return !palReadPad(GPIOF, GPIOF_SD_DETECT);
+}
+
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_STM3210E_EVAL/board.h b/os/hal/boards/ST_STM3210E_EVAL/board.h new file mode 100644 index 000000000..739b3e089 --- /dev/null +++ b/os/hal/boards/ST_STM3210E_EVAL/board.h @@ -0,0 +1,251 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the STMicroelectronics STM3210E-EVAL evaluation board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM3210E_EVAL
+#define BOARD_NAME "ST STM3210E-EVAL"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ * Note: Older board revisions should define STM32F10X_HD instead, please
+ * verify the STM32 model mounted on your board. The change also
+ * affects your linker script.
+ */
+#define STM32F10X_XL
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_WAKEUP_BUTTON 0
+
+#define GPIOB_SC_3V_5V 0
+#define GPIOB_SPI1_CS 2
+#define GPIOB_TEMP_INT 5
+#define GPIOB_USB_DISC 14
+
+#define GPIOC_SC_CMDVCC 6
+#define GPIOC_SC_OFF 7
+#define GPIOC_TAMPER_BUTTON 13
+
+#define GPIOD_JOY_DOWN 3
+
+#define GPIOF_LED1 6
+#define GPIOF_LED2 7
+#define GPIOF_LED3 8
+#define GPIOF_LED4 9
+#define GPIOF_SD_DETECT 11
+
+#define GPIOG_JOY_SEL 7
+#define GPIOG_USER_BUTTON 8
+#define GPIOG_JOY_RIGHT 13
+#define GPIOG_JOY_LEFT 14
+#define GPIOG_JOY_UP 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_ANALOG(n) (0 << (((n) & 7) * 4))
+#define PIN_OUTPUT_PP_10(n) (1 << (((n) & 7) * 4))
+#define PIN_OUTPUT_PP_2(n) (2 << (((n) & 7) * 4))
+#define PIN_OUTPUT_PP_50(n) (3 << (((n) & 7) * 4))
+#define PIN_INPUT(n) (4 << (((n) & 7) * 4))
+#define PIN_OUTPUT_OD_10(n) (5 << (((n) & 7) * 4))
+#define PIN_OUTPUT_OD_2(n) (6 << (((n) & 7) * 4))
+#define PIN_OUTPUT_OD_50(n) (7 << (((n) & 7) * 4))
+#define PIN_INPUT_PUD(n) (8 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_PP_10(n) (9 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_PP_2(n) (10 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_PP_50(n) (11 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_OD_10(n) (13 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_OD_2(n) (14 << (((n) & 7) * 4))
+#define PIN_ALTERNATE_OD_50(n) (15 << (((n) & 7) * 4))
+#define PIN_UNDEFINED(n) PIN_INPUT_PUD(n)
+
+/*
+ * Port A setup.
+ */
+#define VAL_GPIOACRL (PIN_INPUT(0) | /* Wakeup Button. */ \
+ PIN_OUTPUT_PP_50(1) | /* USART2_RTS. */ \
+ PIN_ALTERNATE_PP_50(2) | /* USART2_TX. */ \
+ PIN_INPUT(3) | /* USART2_RX. */ \
+ PIN_UNDEFINED(4) | \
+ PIN_ALTERNATE_PP_50(5) | /* SPI1_SCK. */ \
+ PIN_INPUT(6) | /* SPI1_MISO. */ \
+ PIN_ALTERNATE_PP_50(7)) /* SPI1_MOSI. */
+#define VAL_GPIOACRH (PIN_ALTERNATE_PP_50(8) | /* MCO. */ \
+ PIN_ALTERNATE_PP_50(9) | /* USART1_TX. */ \
+ PIN_INPUT(10) | /* USART1_RX. */ \
+ PIN_INPUT_PUD(11) | /* USB_DM. */ \
+ PIN_INPUT_PUD(12) | /* USB_DP. */ \
+ PIN_INPUT(13) | /* TMS. */ \
+ PIN_INPUT(14) | /* TCK. */ \
+ PIN_INPUT(15)) /* TDI. */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ */
+#define VAL_GPIOBCRL (PIN_OUTPUT_PP_50(0) | /* SmartCard_3/5V. */ \
+ PIN_INPUT_PUD(1) | /* Unconnected. */ \
+ PIN_OUTPUT_PP_50(2) | /* SPI1_CS. */ \
+ PIN_INPUT(3) | /* TDO. */ \
+ PIN_INPUT(4) | /* TRST. */ \
+ PIN_INPUT_PUD(5) | /* Temp.Sensor INT. */ \
+ PIN_ALTERNATE_OD_50(6) | /* I2C1_SCK. */ \
+ PIN_ALTERNATE_OD_50(7)) /* I2C1_SDA. */
+#define VAL_GPIOBCRH (PIN_INPUT(8) | /* CAN_RX. */ \
+ PIN_ALTERNATE_PP_50(9) | /* CAN_TX. */ \
+ PIN_ALTERNATE_OD_50(10)| /* SmartCard IO. */ \
+ PIN_OUTPUT_PP_50(11) | /* SmartCard RST. */ \
+ PIN_ALTERNATE_PP_50(12)| /* SmartCard CLK. */ \
+ PIN_UNDEFINED(13) | \
+ PIN_OUTPUT_PP_50(14) | /* USB disconnect. */ \
+ PIN_UNDEFINED(15))
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ */
+#define VAL_GPIOCCRL (PIN_UNDEFINED(0) | \
+ PIN_UNDEFINED(1) | \
+ PIN_UNDEFINED(2) | \
+ PIN_UNDEFINED(3) | \
+ PIN_ANALOG(4) | /* Potentiometer. */ \
+ PIN_UNDEFINED(5) | \
+ PIN_OUTPUT_PP_50(6) | /* SmartCard CMDVCC. */ \
+ PIN_INPUT(7)) /* SmartCard OFF. */
+#define VAL_GPIOCCRH (PIN_ALTERNATE_PP_50(8) | /* SDIO D0. */ \
+ PIN_ALTERNATE_PP_50(9) | /* SDIO D1. */ \
+ PIN_ALTERNATE_PP_50(10)| /* SDIO D2. */ \
+ PIN_ALTERNATE_PP_50(11)| /* SDIO D3. */ \
+ PIN_ALTERNATE_PP_50(12)| /* SDIO CLK. */ \
+ PIN_INPUT(13) | /* Tamper Button. */ \
+ PIN_INPUT(14) | /* OSC IN. */ \
+ PIN_INPUT(15)) /* OSC OUT. */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup
+ */
+#define VAL_GPIODCRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_D2. */ \
+ PIN_ALTERNATE_PP_50(1) | /* FSMC_D3. */ \
+ PIN_ALTERNATE_PP_50(2) | /* SDIO CMD. */ \
+ PIN_INPUT(3) | /* Joy Down. */ \
+ PIN_ALTERNATE_PP_50(4) | /* FSMC_NOE. */ \
+ PIN_ALTERNATE_PP_50(5) | /* FSMC_NWE. */ \
+ PIN_INPUT(6) | /* FSMC_NWAIT. */ \
+ PIN_ALTERNATE_PP_50(7)) /* FSMC_NCE2. */
+#define VAL_GPIODCRH (PIN_ALTERNATE_PP_50(8) | /* FSMC_D13. */ \
+ PIN_ALTERNATE_PP_50(9) | /* FSMC_D14. */ \
+ PIN_ALTERNATE_PP_50(10)| /* FSMC_D15. */ \
+ PIN_ALTERNATE_PP_50(11)| /* FSMC_A16. */ \
+ PIN_ALTERNATE_PP_50(12)| /* FSMC_A17. */ \
+ PIN_ALTERNATE_PP_50(13)| /* FSMC_A18. */ \
+ PIN_ALTERNATE_PP_50(14)| /* FSMC_D0. */ \
+ PIN_ALTERNATE_PP_50(15)) /* FSMC_D1. */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ */
+#define VAL_GPIOECRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_NBL0. */ \
+ PIN_ALTERNATE_PP_50(1) | /* FSMC_NBL1. */ \
+ PIN_ALTERNATE_PP_50(2) | /* FSMC_A23. */ \
+ PIN_ALTERNATE_PP_50(3) | /* FSMC_A19. */ \
+ PIN_ALTERNATE_PP_50(4) | /* FSMC_A20. */ \
+ PIN_ALTERNATE_PP_50(5) | /* FSMC_A21. */ \
+ PIN_ALTERNATE_PP_50(6) | /* FSMC_A22. */ \
+ PIN_ALTERNATE_PP_50(7)) /* FSMC_D4. */
+#define VAL_GPIOECRH (PIN_ALTERNATE_PP_50(8) | /* FSMC_D5. */ \
+ PIN_ALTERNATE_PP_50(9) | /* FSMC_D6. */ \
+ PIN_ALTERNATE_PP_50(10)| /* FSMC_D7. */ \
+ PIN_ALTERNATE_PP_50(11)| /* FSMC_D8. */ \
+ PIN_ALTERNATE_PP_50(12)| /* FSMC_D9. */ \
+ PIN_ALTERNATE_PP_50(13)| /* FSMC_D10. */ \
+ PIN_ALTERNATE_PP_50(14)| /* FSMC_D11. */ \
+ PIN_ALTERNATE_PP_50(15)) /* FSMC_D12. */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+/*
+ * Port F setup.
+ */
+#define VAL_GPIOFCRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_A0. */ \
+ PIN_ALTERNATE_PP_50(1) | /* FSMC_A1. */ \
+ PIN_ALTERNATE_PP_50(2) | /* FSMC_A2. */ \
+ PIN_ALTERNATE_PP_50(3) | /* FSMC_A3. */ \
+ PIN_ALTERNATE_PP_50(4) | /* FSMC_A4. */ \
+ PIN_ALTERNATE_PP_50(5) | /* FSMC_A5. */ \
+ PIN_OUTPUT_PP_50(6) | /* LED1. */ \
+ PIN_OUTPUT_PP_50(7)) /* LED2. */
+#define VAL_GPIOFCRH (PIN_OUTPUT_PP_50(8) | /* LED3. */ \
+ PIN_OUTPUT_PP_50(9) | /* LED4. */ \
+ PIN_UNDEFINED(10) | \
+ PIN_INPUT_PUD(11) | /* SDCard detect. */ \
+ PIN_ALTERNATE_PP_50(12)| /* FSMC_A6. */ \
+ PIN_ALTERNATE_PP_50(13)| /* FSMC_A7. */ \
+ PIN_ALTERNATE_PP_50(14)| /* FSMC_A8. */ \
+ PIN_ALTERNATE_PP_50(15)) /* FSMC_A9. */
+#define VAL_GPIOFODR 0xFFFFFC3F
+
+/*
+ * Port G setup.
+ */
+#define VAL_GPIOGCRL (PIN_ALTERNATE_PP_50(0) | /* FSMC_A10. */ \
+ PIN_ALTERNATE_PP_50(1) | /* FSMC_A11. */ \
+ PIN_ALTERNATE_PP_50(2) | /* FSMC_A12. */ \
+ PIN_ALTERNATE_PP_50(3) | /* FSMC_A13. */ \
+ PIN_ALTERNATE_PP_50(4) | /* FSMC_A14. */ \
+ PIN_ALTERNATE_PP_50(5) | /* FSMC_A15. */ \
+ PIN_INPUT(6) | /* FSMC_INT2. */ \
+ PIN_INPUT(7)) /* Joy Select. */
+#define VAL_GPIOGCRH (PIN_INPUT(8) | /* User Button. */ \
+ PIN_ALTERNATE_PP_50(9) | /* FSMC_NE2. */ \
+ PIN_ALTERNATE_PP_50(10)| /* FSMC_NE3. */ \
+ PIN_OUTPUT_PP_50(11) | /* Audio PDN. */ \
+ PIN_ALTERNATE_PP_50(12)| /* FSMC_NE4. */ \
+ PIN_INPUT(13) | /* Joy Right. */ \
+ PIN_INPUT(14) | /* Joy Left. */ \
+ PIN_INPUT(15)) /* Joy Up. */
+#define VAL_GPIOGODR 0xFFFFF7FF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM3210E_EVAL/board.mk b/os/hal/boards/ST_STM3210E_EVAL/board.mk new file mode 100644 index 000000000..edd0baf21 --- /dev/null +++ b/os/hal/boards/ST_STM3210E_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM3210E_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM3210E_EVAL
diff --git a/os/hal/boards/ST_STM3220G_EVAL/board.c b/os/hal/boards/ST_STM3220G_EVAL/board.c new file mode 100644 index 000000000..c78a97b8d --- /dev/null +++ b/os/hal/boards/ST_STM3220G_EVAL/board.c @@ -0,0 +1,54 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM3220G_EVAL/board.h b/os/hal/boards/ST_STM3220G_EVAL/board.h new file mode 100644 index 000000000..07cfc5dea --- /dev/null +++ b/os/hal/boards/ST_STM3220G_EVAL/board.h @@ -0,0 +1,226 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM3220G-EVAL board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM3220G_EVAL
+#define BOARD_NAME "ST STM3220G-EVAL"
+
+/*
+ * Board frequencies.
+ * NOTE: The HSE crystal is not fitted by default on the board.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 25000000
+
+/*
+ * MCU type as defined in the ST header file stm32f2xx.h.
+ */
+#define STM32F2XX
+
+/*
+ * IO pins assignments.
+ */
+
+#define GPIOA_WAKEUP_BUTTON 0
+
+#define GPIOB_ETHER_INT 14
+#define GPIOB_NAND_INT 15
+
+#define GPIOC_TAMPER_BUTTON 0
+#define GPIOC_LED4 7
+
+#define GPIOF_POT 9
+
+#define GPIOG_LED1 6
+#define GPIOG_LED2 8
+#define GPIOG_USER_BUTTON 15
+
+#define GPIOH_EXPANDER_INT 12
+#define GPIOH_SD_DETECT 13
+
+#define GPIOI_LED3 9
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0 << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1 << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2 << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3 << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n) (0 << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1 << (n))
+#define PIN_OSPEED_2M(n) (0 << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1 << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2 << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3 << ((n) * 2))
+#define PIN_PUDR_FLOATING(n) (0 << ((n) * 2))
+#define PIN_PUDR_PULLUP(n) (1 << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n) (2 << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ * All input with pull-up except:
+ * PA8 - MCO 1 (alternate 0).
+ * PA13 - JTMS/SWDAT (alternate 0).
+ * PA14 - JTCK/SWCLK (alternate 0).
+ * PA15 - JTDI (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(8) | \
+ PIN_MODE_ALTERNATE(13) | \
+ PIN_MODE_ALTERNATE(14) | \
+ PIN_MODE_ALTERNATE(15))
+#define VAL_GPIOA_OTYPER 0x00000000
+#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(13) | \
+ PIN_PUDR_FLOATING(14) | \
+ PIN_PUDR_FLOATING(15))
+#define VAL_GPIOA_ODR 0xFFFFFFFF
+#define VAL_GPIOA_AFRL 0x00000000
+#define VAL_GPIOA_AFRH 0x00000000
+
+/*
+ * Port B setup.
+ * All input with pull-up except:
+ * PB3 - JTDO (alternate 0).
+ * PB4 - JNTRST (alternate 0).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(3) | \
+ PIN_MODE_ALTERNATE(4))
+#define VAL_GPIOB_OTYPER 0x00000000
+#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOB_PUPDR (~(PIN_PUDR_FLOATING(3) | \
+ PIN_PUDR_FLOATING(4)))
+#define VAL_GPIOB_ODR 0xFFFFFFFF
+#define VAL_GPIOB_AFRL 0x00000000
+#define VAL_GPIOB_AFRH 0x00000000
+
+/*
+ * Port C setup.
+ * All input with pull-up except:
+ * PC9 - MCO2 (alternate 0).
+ * PC10 - USART3_TX (alternate 7).
+ * PC11 - USART3_RX (alternate 7).
+ * PC14 - OSC32_INT (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(9) | \
+ PIN_MODE_ALTERNATE(10) | \
+ PIN_MODE_ALTERNATE(11))
+#define VAL_GPIOC_OTYPER 0x00000000
+#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOC_PUPDR (~(PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_FLOATING(14) | \
+ PIN_PUDR_FLOATING(15)))
+#define VAL_GPIOC_ODR 0xFFFFFFFF
+#define VAL_GPIOC_AFRL 0x00000000
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(7, 10) | \
+ PIN_AFIO_AF(7, 11))
+
+/*
+ * Port D setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOD_MODER 0x00000000
+#define VAL_GPIOD_OTYPER 0x00000000
+#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOD_PUPDR 0xFFFFFFFF
+#define VAL_GPIOD_ODR 0xFFFFFFFF
+#define VAL_GPIOD_AFRL 0x00000000
+#define VAL_GPIOD_AFRH 0x00000000
+
+/*
+ * Port E setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOE_MODER 0x00000000
+#define VAL_GPIOE_OTYPER 0x00000000
+#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOE_PUPDR 0xFFFFFFFF
+#define VAL_GPIOE_ODR 0xFFFFFFFF
+#define VAL_GPIOE_AFRL 0x00000000
+#define VAL_GPIOE_AFRH 0x00000000
+
+/*
+ * Port F setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOF_MODER 0x00000000
+#define VAL_GPIOF_OTYPER 0x00000000
+#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOF_PUPDR 0xFFFFFFFF
+#define VAL_GPIOF_ODR 0xFFFFFFFF
+#define VAL_GPIOF_AFRL 0x00000000
+#define VAL_GPIOF_AFRH 0x00000000
+
+/*
+ * Port G setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_OUTPUT(GPIOG_LED1))
+#define VAL_GPIOG_OTYPER 0x00000000
+#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOG_PUPDR (~(PIN_PUDR_FLOATING(GPIOG_LED1)))
+#define VAL_GPIOG_ODR 0xFFFFFFBF
+#define VAL_GPIOG_AFRL 0x00000000
+#define VAL_GPIOG_AFRH 0x00000000
+
+/*
+ * Port H setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOH_MODER 0x00000000
+#define VAL_GPIOH_OTYPER 0x00000000
+#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOH_PUPDR 0xFFFFFFFF
+#define VAL_GPIOH_ODR 0xFFFFFFFF
+#define VAL_GPIOH_AFRL 0x00000000
+#define VAL_GPIOH_AFRH 0x00000000
+
+/*
+ * Port I setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOI_MODER 0x00000000
+#define VAL_GPIOI_OTYPER 0x00000000
+#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOI_PUPDR 0xFFFFFFFF
+#define VAL_GPIOI_ODR 0xFFFFFFFF
+#define VAL_GPIOI_AFRL 0x00000000
+#define VAL_GPIOI_AFRH 0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM3220G_EVAL/board.mk b/os/hal/boards/ST_STM3220G_EVAL/board.mk new file mode 100644 index 000000000..3121594a6 --- /dev/null +++ b/os/hal/boards/ST_STM3220G_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM3220G_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM3220G_EVAL
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.c b/os/hal/boards/ST_STM32373C_EVAL/board.c new file mode 100644 index 000000000..baafd6550 --- /dev/null +++ b/os/hal/boards/ST_STM32373C_EVAL/board.c @@ -0,0 +1,102 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.h b/os/hal/boards/ST_STM32373C_EVAL/board.h new file mode 100644 index 000000000..13676e7e6 --- /dev/null +++ b/os/hal/boards/ST_STM32373C_EVAL/board.h @@ -0,0 +1,888 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32373C-EVAL board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32373C_EVAL
+#define BOARD_NAME "STMicroelectronics STM32373C-EVAL"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768
+#endif
+
+#define STM32_LSEDRV (3 << 3)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000
+#endif
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F37X
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_WKUP_BUTTON 0
+#define GPIOA_LDR_OUT 1
+#define GPIOA_KEY_BUTTON 2
+#define GPIOA_PIN3 3
+#define GPIOA_PIN4 4
+#define GPIOA_PIN5 5
+#define GPIOA_PIN6 6
+#define GPIOA_COMP2_OUT 7
+#define GPIOA_I2C2_SMB 8
+#define GPIOA_I2C2_SCL 9
+#define GPIOA_I2C2_SDA 10
+#define GPIOA_USB_DM 11
+#define GPIOA_USB_DP 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_JTDI 15
+
+#define GPIOB_MIC_IN 0
+#define GPIOB_ADC_POT_IN 1
+#define GPIOB_PIN2 2
+#define GPIOB_SWO 3
+#define GPIOB_JTRST 4
+#define GPIOB_PIN5 5
+#define GPIOB_I2C1_SCL 6
+#define GPIOB_I2C1_SDA 7
+#define GPIOB_PIN8 8
+#define GPIOB_PIN9 9
+#define GPIOB_PIN10 10
+#define GPIOB_PIN11 11
+#define GPIOB_PIN12 12
+#define GPIOB_PIN13 13
+#define GPIOB_PIN14 14
+#define GPIOB_PIN15 15
+
+#define GPIOC_LED1 0
+#define GPIOC_LED2 1
+#define GPIOC_LED3 2
+#define GPIOC_LED4 3
+#define GPIOC_PIN4 4
+#define GPIOC_USB_DISCONNECT 5
+#define GPIOC_PIN6 6
+#define GPIOC_PIN7 7
+#define GPIOC_PIN8 8
+#define GPIOC_PIN9 9
+#define GPIOC_SPI3_SCK 10
+#define GPIOC_SPI3_MISO 11
+#define GPIOC_SPI3_MOSI 12
+#define GPIOC_PIN13 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_CAN_RX 0
+#define GPIOD_CAN_TX 1
+#define GPIOD_LCD_CS 2
+#define GPIOD_USART2_CTS 3
+#define GPIOD_USART2_RST 4
+#define GPIOD_USART2_TX 5
+#define GPIOD_USART2_RX 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_AUDIO_RST 11
+#define GPIOD_PIN12 12
+#define GPIOD_PIN13 13
+#define GPIOD_PIN14 14
+#define GPIOD_PIN15 15
+
+#define GPIOE_PIN0 0
+#define GPIOE_PIN1 1
+#define GPIOE_SD_CS 2
+#define GPIOE_SD_DETECT 3
+#define GPIOE_PIN4 4
+#define GPIOE_PIN5 5
+#define GPIOE_JOY_SEL 6
+#define GPIOE_RTD_IN 7
+#define GPIOE_PRESSUREP 8
+#define GPIOE_PRESSUREN 9
+#define GPIOE_PIN10 10
+#define GPIOE_PIN11 11
+#define GPIOE_PIN12 12
+#define GPIOE_PIN13 13
+#define GPIOE_PRESSURE_TEPM 14
+#define GPIOE_PIN15 15
+
+#define GPIOF_OSC_IN 0
+#define GPIOF_OSC_OUT 1
+#define GPIOF_JOY_DOWN 2
+#define GPIOF_PIN3 3
+#define GPIOF_JOY_LEFT 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_JOY_RIGHT 9
+#define GPIOF_JOY_UP 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - WKUP_BUTTON (input floating).
+ * PA1 - LDR_OUT (analog).
+ * PA2 - KEY_BUTTON (input floating).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - PIN5 (input floating).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - COMP2_OUT (output pushpull maximum).
+ * PA8 - I2C2_SMB (input floating).
+ * PA9 - I2C2_SCL (alternate 4).
+ * PA10 - I2C2_SDA (alternate 4).
+ * PA11 - USB_DM (alternate 14).
+ * PA12 - USB_DP (alternate 14).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - JTDI (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_WKUP_BUTTON) | \
+ PIN_MODE_ANALOG(GPIOA_LDR_OUT) | \
+ PIN_MODE_INPUT(GPIOA_KEY_BUTTON) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_INPUT(GPIOA_PIN5) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_OUTPUT(GPIOA_COMP2_OUT) | \
+ PIN_MODE_INPUT(GPIOA_I2C2_SMB) | \
+ PIN_MODE_ALTERNATE(GPIOA_I2C2_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOA_I2C2_SDA) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_WKUP_BUTTON) |\
+ PIN_OTYPE_PUSHPULL(GPIOA_LDR_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_KEY_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_COMP2_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_I2C2_SMB) | \
+ PIN_OTYPE_OPENDRAIN(GPIOA_I2C2_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOA_I2C2_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_WKUP_BUTTON) | \
+ PIN_OSPEED_2M(GPIOA_LDR_OUT) | \
+ PIN_OSPEED_2M(GPIOA_KEY_BUTTON) | \
+ PIN_OSPEED_2M(GPIOA_PIN3) | \
+ PIN_OSPEED_2M(GPIOA_PIN4) | \
+ PIN_OSPEED_100M(GPIOA_PIN5) | \
+ PIN_OSPEED_2M(GPIOA_PIN6) | \
+ PIN_OSPEED_100M(GPIOA_COMP2_OUT) | \
+ PIN_OSPEED_2M(GPIOA_I2C2_SMB) | \
+ PIN_OSPEED_100M(GPIOA_I2C2_SCL) | \
+ PIN_OSPEED_100M(GPIOA_I2C2_SDA) | \
+ PIN_OSPEED_100M(GPIOA_USB_DM) | \
+ PIN_OSPEED_2M(GPIOA_USB_DP) | \
+ PIN_OSPEED_100M(GPIOA_SWDIO) | \
+ PIN_OSPEED_100M(GPIOA_SWCLK) | \
+ PIN_OSPEED_100M(GPIOA_JTDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_WKUP_BUTTON) |\
+ PIN_PUPDR_FLOATING(GPIOA_LDR_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOA_KEY_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOA_COMP2_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOA_I2C2_SMB) | \
+ PIN_PUPDR_FLOATING(GPIOA_I2C2_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOA_I2C2_SDA) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_WKUP_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_LDR_OUT) | \
+ PIN_ODR_HIGH(GPIOA_KEY_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_LOW(GPIOA_COMP2_OUT) | \
+ PIN_ODR_HIGH(GPIOA_I2C2_SMB) | \
+ PIN_ODR_HIGH(GPIOA_I2C2_SCL) | \
+ PIN_ODR_HIGH(GPIOA_I2C2_SDA) | \
+ PIN_ODR_HIGH(GPIOA_USB_DM) | \
+ PIN_ODR_HIGH(GPIOA_USB_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_JTDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_WKUP_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_LDR_OUT, 0) | \
+ PIN_AFIO_AF(GPIOA_KEY_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 5) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOA_COMP2_OUT, 0))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_I2C2_SMB, 0) | \
+ PIN_AFIO_AF(GPIOA_I2C2_SCL, 4) | \
+ PIN_AFIO_AF(GPIOA_I2C2_SDA, 4) | \
+ PIN_AFIO_AF(GPIOA_USB_DM, 14) | \
+ PIN_AFIO_AF(GPIOA_USB_DP, 14) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_JTDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - MIC_IN (analog).
+ * PB1 - ADC_POT_IN (analog).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - JTRST (input floating).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - I2C1_SCL (alternate 4).
+ * PB7 - I2C1_SDA (alternate 4).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_MIC_IN) | \
+ PIN_MODE_ANALOG(GPIOB_ADC_POT_IN) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_JTRST) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_MIC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ADC_POT_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTRST) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_MIC_IN) | \
+ PIN_OSPEED_2M(GPIOB_ADC_POT_IN) | \
+ PIN_OSPEED_2M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_SWO) | \
+ PIN_OSPEED_100M(GPIOB_JTRST) | \
+ PIN_OSPEED_2M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \
+ PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \
+ PIN_OSPEED_2M(GPIOB_PIN8) | \
+ PIN_OSPEED_2M(GPIOB_PIN9) | \
+ PIN_OSPEED_2M(GPIOB_PIN10) | \
+ PIN_OSPEED_2M(GPIOB_PIN11) | \
+ PIN_OSPEED_2M(GPIOB_PIN12) | \
+ PIN_OSPEED_2M(GPIOB_PIN13) | \
+ PIN_OSPEED_2M(GPIOB_PIN14) | \
+ PIN_OSPEED_2M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_MIC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOB_ADC_POT_IN) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_SWO) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTRST) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_MIC_IN) | \
+ PIN_ODR_HIGH(GPIOB_ADC_POT_IN) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_JTRST) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_MIC_IN, 0) | \
+ PIN_AFIO_AF(GPIOB_ADC_POT_IN, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0) | \
+ PIN_AFIO_AF(GPIOB_JTRST, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SDA, 4))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - LED1 (output opendrain maximum).
+ * PC1 - LED2 (output opendrain maximum).
+ * PC2 - LED3 (output opendrain maximum).
+ * PC3 - LED4 (output opendrain maximum).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - USB_DISCONNECT (output pushpull maximum).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - SPI3_SCK (alternate 6).
+ * PC11 - SPI3_MISO (alternate 6).
+ * PC12 - SPI3_MOSI (alternate 6).
+ * PC13 - PIN13 (input pullup).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_LED1) | \
+ PIN_MODE_OUTPUT(GPIOC_LED2) | \
+ PIN_MODE_OUTPUT(GPIOC_LED3) | \
+ PIN_MODE_OUTPUT(GPIOC_LED4) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_OUTPUT(GPIOC_USB_DISCONNECT) |\
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOC_LED1) | \
+ PIN_OTYPE_OPENDRAIN(GPIOC_LED2) | \
+ PIN_OTYPE_OPENDRAIN(GPIOC_LED3) | \
+ PIN_OTYPE_OPENDRAIN(GPIOC_LED4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_USB_DISCONNECT) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI3_SCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_LED1) | \
+ PIN_OSPEED_100M(GPIOC_LED2) | \
+ PIN_OSPEED_100M(GPIOC_LED3) | \
+ PIN_OSPEED_100M(GPIOC_LED4) | \
+ PIN_OSPEED_2M(GPIOC_PIN4) | \
+ PIN_OSPEED_100M(GPIOC_USB_DISCONNECT) |\
+ PIN_OSPEED_2M(GPIOC_PIN6) | \
+ PIN_OSPEED_2M(GPIOC_PIN7) | \
+ PIN_OSPEED_2M(GPIOC_PIN8) | \
+ PIN_OSPEED_2M(GPIOC_PIN9) | \
+ PIN_OSPEED_100M(GPIOC_SPI3_SCK) | \
+ PIN_OSPEED_100M(GPIOC_SPI3_MISO) | \
+ PIN_OSPEED_100M(GPIOC_SPI3_MOSI) | \
+ PIN_OSPEED_2M(GPIOC_PIN13) | \
+ PIN_OSPEED_100M(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_LED1) | \
+ PIN_PUPDR_FLOATING(GPIOC_LED2) | \
+ PIN_PUPDR_FLOATING(GPIOC_LED3) | \
+ PIN_PUPDR_FLOATING(GPIOC_LED4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOC_USB_DISCONNECT) |\
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOC_SPI3_SCK) | \
+ PIN_PUPDR_PULLUP(GPIOC_SPI3_MISO) | \
+ PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_LED1) | \
+ PIN_ODR_HIGH(GPIOC_LED2) | \
+ PIN_ODR_HIGH(GPIOC_LED3) | \
+ PIN_ODR_HIGH(GPIOC_LED4) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_USB_DISCONNECT) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_SPI3_SCK) | \
+ PIN_ODR_HIGH(GPIOC_SPI3_MISO) | \
+ PIN_ODR_HIGH(GPIOC_SPI3_MOSI) | \
+ PIN_ODR_HIGH(GPIOC_PIN13) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_LED1, 0) | \
+ PIN_AFIO_AF(GPIOC_LED2, 0) | \
+ PIN_AFIO_AF(GPIOC_LED3, 0) | \
+ PIN_AFIO_AF(GPIOC_LED4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_USB_DISCONNECT, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOC_SPI3_SCK, 6) | \
+ PIN_AFIO_AF(GPIOC_SPI3_MISO, 6) | \
+ PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - CAN_RX (alternate 7).
+ * PD1 - CAN_TX (alternate 7).
+ * PD2 - LCD_CS (output pushpull maximum).
+ * PD3 - USART2_CTS (alternate 7).
+ * PD4 - USART2_RST (alternate 7).
+ * PD5 - USART2_TX (alternate 7).
+ * PD6 - USART2_RX (alternate 7).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - AUDIO_RST (output pushpull maximum).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_CAN_RX) | \
+ PIN_MODE_ALTERNATE(GPIOD_CAN_TX) | \
+ PIN_MODE_OUTPUT(GPIOD_LCD_CS) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART2_CTS) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART2_RST) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART2_TX) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART2_RX) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_OUTPUT(GPIOD_AUDIO_RST) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_CAN_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_CAN_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LCD_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART2_CTS) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART2_RST) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART2_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART2_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_AUDIO_RST) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_CAN_RX) | \
+ PIN_OSPEED_100M(GPIOD_CAN_TX) | \
+ PIN_OSPEED_100M(GPIOD_LCD_CS) | \
+ PIN_OSPEED_100M(GPIOD_USART2_CTS) | \
+ PIN_OSPEED_100M(GPIOD_USART2_RST) | \
+ PIN_OSPEED_100M(GPIOD_USART2_TX) | \
+ PIN_OSPEED_100M(GPIOD_USART2_RX) | \
+ PIN_OSPEED_2M(GPIOD_PIN7) | \
+ PIN_OSPEED_2M(GPIOD_PIN8) | \
+ PIN_OSPEED_2M(GPIOD_PIN9) | \
+ PIN_OSPEED_2M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_AUDIO_RST) | \
+ PIN_OSPEED_2M(GPIOD_PIN12) | \
+ PIN_OSPEED_2M(GPIOD_PIN13) | \
+ PIN_OSPEED_2M(GPIOD_PIN14) | \
+ PIN_OSPEED_2M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_CAN_RX) | \
+ PIN_PUPDR_FLOATING(GPIOD_CAN_TX) | \
+ PIN_PUPDR_FLOATING(GPIOD_LCD_CS) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART2_CTS) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART2_RST) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART2_TX) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART2_RX) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOD_AUDIO_RST) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_CAN_RX) | \
+ PIN_ODR_HIGH(GPIOD_CAN_TX) | \
+ PIN_ODR_HIGH(GPIOD_LCD_CS) | \
+ PIN_ODR_HIGH(GPIOD_USART2_CTS) | \
+ PIN_ODR_HIGH(GPIOD_USART2_RST) | \
+ PIN_ODR_HIGH(GPIOD_USART2_TX) | \
+ PIN_ODR_HIGH(GPIOD_USART2_RX) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_LOW(GPIOD_AUDIO_RST) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_CAN_RX, 7) | \
+ PIN_AFIO_AF(GPIOD_CAN_TX, 7) | \
+ PIN_AFIO_AF(GPIOD_LCD_CS, 0) | \
+ PIN_AFIO_AF(GPIOD_USART2_CTS, 7) | \
+ PIN_AFIO_AF(GPIOD_USART2_RST, 7) | \
+ PIN_AFIO_AF(GPIOD_USART2_TX, 7) | \
+ PIN_AFIO_AF(GPIOD_USART2_RX, 7) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_AUDIO_RST, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - SD_CS (output opendrain maximum).
+ * PE3 - SD_DETECT (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - JOY_SEL (input pulldown).
+ * PE7 - RTD_IN (analog).
+ * PE8 - PRESSUREP (analog).
+ * PE9 - PRESSUREN (analog).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PRESSURE_TEPM (input floating).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_OUTPUT(GPIOE_SD_CS) | \
+ PIN_MODE_INPUT(GPIOE_SD_DETECT) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_JOY_SEL) | \
+ PIN_MODE_ANALOG(GPIOE_RTD_IN) | \
+ PIN_MODE_ANALOG(GPIOE_PRESSUREP) | \
+ PIN_MODE_ANALOG(GPIOE_PRESSUREN) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PRESSURE_TEPM) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_OPENDRAIN(GPIOE_SD_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_SD_DETECT) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_JOY_SEL) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_RTD_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PRESSUREP) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PRESSUREN) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PRESSURE_TEPM) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_2M(GPIOE_PIN0) | \
+ PIN_OSPEED_2M(GPIOE_PIN1) | \
+ PIN_OSPEED_100M(GPIOE_SD_CS) | \
+ PIN_OSPEED_100M(GPIOE_SD_DETECT) | \
+ PIN_OSPEED_2M(GPIOE_PIN4) | \
+ PIN_OSPEED_2M(GPIOE_PIN5) | \
+ PIN_OSPEED_100M(GPIOE_JOY_SEL) | \
+ PIN_OSPEED_2M(GPIOE_RTD_IN) | \
+ PIN_OSPEED_100M(GPIOE_PRESSUREP) | \
+ PIN_OSPEED_100M(GPIOE_PRESSUREN) | \
+ PIN_OSPEED_2M(GPIOE_PIN10) | \
+ PIN_OSPEED_2M(GPIOE_PIN11) | \
+ PIN_OSPEED_2M(GPIOE_PIN12) | \
+ PIN_OSPEED_2M(GPIOE_PIN13) | \
+ PIN_OSPEED_2M(GPIOE_PRESSURE_TEPM) | \
+ PIN_OSPEED_2M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOE_SD_CS) | \
+ PIN_PUPDR_PULLUP(GPIOE_SD_DETECT) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLDOWN(GPIOE_JOY_SEL) | \
+ PIN_PUPDR_FLOATING(GPIOE_RTD_IN) | \
+ PIN_PUPDR_FLOATING(GPIOE_PRESSUREP) | \
+ PIN_PUPDR_FLOATING(GPIOE_PRESSUREN) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PRESSURE_TEPM) |\
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_SD_CS) | \
+ PIN_ODR_HIGH(GPIOE_SD_DETECT) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_JOY_SEL) | \
+ PIN_ODR_HIGH(GPIOE_RTD_IN) | \
+ PIN_ODR_HIGH(GPIOE_PRESSUREP) | \
+ PIN_ODR_HIGH(GPIOE_PRESSUREN) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_LOW(GPIOE_PIN13) | \
+ PIN_ODR_LOW(GPIOE_PRESSURE_TEPM) | \
+ PIN_ODR_LOW(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOE_SD_CS, 0) | \
+ PIN_AFIO_AF(GPIOE_SD_DETECT, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_JOY_SEL, 0) | \
+ PIN_AFIO_AF(GPIOE_RTD_IN, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PRESSUREP, 0) | \
+ PIN_AFIO_AF(GPIOE_PRESSUREN, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PRESSURE_TEPM, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - OSC_IN (input floating).
+ * PF1 - OSC_OUT (input floating).
+ * PF2 - JOY_DOWN (input pulldown).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - JOY_LEFT (input pulldown).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - JOY_RIGHT (input pulldown).
+ * PF10 - JOY_UP (input pulldown).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOF_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOF_JOY_DOWN) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_JOY_LEFT) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_JOY_RIGHT) | \
+ PIN_MODE_INPUT(GPIOF_JOY_UP) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_JOY_DOWN) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_JOY_LEFT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_JOY_RIGHT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_JOY_UP) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOF_OSC_OUT) | \
+ PIN_OSPEED_100M(GPIOF_JOY_DOWN) | \
+ PIN_OSPEED_2M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_JOY_LEFT) | \
+ PIN_OSPEED_2M(GPIOF_PIN5) | \
+ PIN_OSPEED_2M(GPIOF_PIN6) | \
+ PIN_OSPEED_2M(GPIOF_PIN7) | \
+ PIN_OSPEED_2M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_JOY_RIGHT) | \
+ PIN_OSPEED_100M(GPIOF_JOY_UP) | \
+ PIN_OSPEED_2M(GPIOF_PIN11) | \
+ PIN_OSPEED_2M(GPIOF_PIN12) | \
+ PIN_OSPEED_2M(GPIOF_PIN13) | \
+ PIN_OSPEED_2M(GPIOF_PIN14) | \
+ PIN_OSPEED_2M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
+ PIN_PUPDR_PULLDOWN(GPIOF_JOY_DOWN) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLDOWN(GPIOF_JOY_LEFT) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLDOWN(GPIOF_JOY_RIGHT) | \
+ PIN_PUPDR_PULLDOWN(GPIOF_JOY_UP) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOF_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOF_JOY_DOWN) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_JOY_LEFT) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_JOY_RIGHT) | \
+ PIN_ODR_HIGH(GPIOF_JOY_UP) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOF_JOY_DOWN, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_JOY_LEFT, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_JOY_RIGHT, 0) | \
+ PIN_AFIO_AF(GPIOF_JOY_UP, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.mk b/os/hal/boards/ST_STM32373C_EVAL/board.mk new file mode 100644 index 000000000..98a37d006 --- /dev/null +++ b/os/hal/boards/ST_STM32373C_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM32373C_EVAL/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM32373C_EVAL
diff --git a/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg b/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg new file mode 100644 index 000000000..85f428ef8 --- /dev/null +++ b/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg @@ -0,0 +1,798 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F3xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f3xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32f3xx/templates</templates_path>
+ <output_path>..</output_path>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32373C-EVAL</board_name>
+ <board_id>ST_STM32373C_EVAL</board_id>
+ <board_functions></board_functions>
+ <subtype>STM32F37X</subtype>
+ <clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="32768"
+ LSEBypass="false" LSEDrive="3 High Drive (default)" />
+ <ports>
+ <GPIOA>
+ <pin0
+ ID="WKUP_BUTTON"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="LDR_OUT"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID="KEY_BUTTON"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin2>
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="5" ></pin5>
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="COMP2_OUT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin8
+ ID="I2C2_SMB"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="I2C2_SCL"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="4" />
+ <pin10
+ ID="I2C2_SDA"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="4" ></pin10>
+ <pin11
+ ID="USB_DM"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="14" />
+ <pin12
+ ID="USB_DP"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="14" ></pin12>
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="High"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID="JTDI"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID="MIC_IN"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Analog"
+ Alternate="0" />
+ <pin1
+ ID="ADC_POT_IN"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Analog"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="SWO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin4
+ ID="JTRST"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin5>
+ <pin6
+ ID="I2C1_SCL"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="4" />
+ <pin7
+ ID="I2C1_SDA"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="4" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID="LED1"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" />
+ <pin1
+ ID="LED2"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" />
+ <pin2
+ ID="LED3"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" />
+ <pin3
+ ID="LED4"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" ></pin3>
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="USB_DISCONNECT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID="SPI3_SCK"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="6" />
+ <pin11
+ ID="SPI3_MISO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Alternate"
+ Alternate="6" />
+ <pin12
+ ID="SPI3_MOSI"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="6" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="OSC32_IN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="OSC32_OUT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID="CAN_RX"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin1
+ ID="CAN_TX"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin2
+ ID="LCD_CS"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" />
+ <pin3
+ ID="USART2_CTS"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="7" ></pin3>
+ <pin4
+ ID="USART2_RST"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin5
+ ID="USART2_TX"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin6
+ ID="USART2_RX"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="AUDIO_RST"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="SD_CS"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" ></pin2>
+ <pin3
+ ID="SD_DETECT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin3>
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin5>
+ <pin6
+ ID="JOY_SEL"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="RTD_IN"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Analog"
+ Alternate="0" />
+ <pin8
+ ID="PRESSUREP"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Analog"
+ Alternate="0" />
+ <pin9
+ ID="PRESSUREN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin10>
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Input"
+ Alternate="0" ></pin13>
+ <pin14
+ ID="PRESSURE_TEPM"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin1>
+ <pin2
+ ID="JOY_DOWN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin3>
+ <pin4
+ ID="JOY_LEFT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="JOY_RIGHT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID="JOY_UP"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOF>
+ </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0_DISCOVERY/board.c new file mode 100644 index 000000000..0393835ad --- /dev/null +++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.c @@ -0,0 +1,78 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h new file mode 100644 index 000000000..088cf38e3 --- /dev/null +++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h @@ -0,0 +1,757 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for ST STM32F0-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F0_DISCOVERY
+#define BOARD_NAME "ST STM32F0-Discovery"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ * NOTE: HSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 0
+#endif
+
+#define STM32_LSEDRV (3 << 3)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 0
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header file stm32f0xx.h.
+ */
+#define STM32F0XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+#define GPIOA_PIN1 1
+#define GPIOA_PIN2 2
+#define GPIOA_PIN3 3
+#define GPIOA_PIN4 4
+#define GPIOA_PIN5 5
+#define GPIOA_PIN6 6
+#define GPIOA_PIN7 7
+#define GPIOA_PIN8 8
+#define GPIOA_PIN9 9
+#define GPIOA_PIN10 10
+#define GPIOA_PIN11 11
+#define GPIOA_PIN12 12
+#define GPIOA_SWDAT 13
+#define GPIOA_SWCLK 14
+#define GPIOA_PIN15 15
+
+#define GPIOB_PIN0 0
+#define GPIOB_PIN1 1
+#define GPIOB_PIN2 2
+#define GPIOB_PIN3 3
+#define GPIOB_PIN4 4
+#define GPIOB_PIN5 5
+#define GPIOB_PIN6 6
+#define GPIOB_PIN7 7
+#define GPIOB_PIN8 8
+#define GPIOB_PIN9 9
+#define GPIOB_PIN10 10
+#define GPIOB_PIN11 11
+#define GPIOB_PIN12 12
+#define GPIOB_PIN13 13
+#define GPIOB_PIN14 14
+#define GPIOB_PIN15 15
+
+#define GPIOC_PIN0 0
+#define GPIOC_PIN1 1
+#define GPIOC_PIN2 2
+#define GPIOC_PIN3 3
+#define GPIOC_PIN4 4
+#define GPIOC_PIN5 5
+#define GPIOC_PIN6 6
+#define GPIOC_PIN7 7
+#define GPIOC_LED4 8
+#define GPIOC_LED3 9
+#define GPIOC_PIN10 10
+#define GPIOC_PIN11 11
+#define GPIOC_PIN12 12
+#define GPIOC_PIN13 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_PIN2 2
+#define GPIOD_PIN3 3
+#define GPIOD_PIN4 4
+#define GPIOD_PIN5 5
+#define GPIOD_PIN6 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_PIN12 12
+#define GPIOD_PIN13 13
+#define GPIOD_PIN14 14
+#define GPIOD_PIN15 15
+
+#define GPIOF_OSC_IN 0
+#define GPIOF_OSC_OUT 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_10M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_40M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON (input floating).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - PIN2 (input pullup).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - PIN5 (input pullup).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - PIN7 (input pullup).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - PIN9 (input pullup).
+ * PA10 - PIN10 (input pullup).
+ * PA11 - PIN11 (input pullup).
+ * PA12 - PIN12 (input pullup).
+ * PA13 - SWDAT (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_PIN2) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_INPUT(GPIOA_PIN5) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_INPUT(GPIOA_PIN7) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_PIN9) | \
+ PIN_MODE_INPUT(GPIOA_PIN10) | \
+ PIN_MODE_INPUT(GPIOA_PIN11) | \
+ PIN_MODE_INPUT(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDAT) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDAT) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \
+ PIN_OSPEED_2M(GPIOA_PIN1) | \
+ PIN_OSPEED_2M(GPIOA_PIN2) | \
+ PIN_OSPEED_2M(GPIOA_PIN3) | \
+ PIN_OSPEED_2M(GPIOA_PIN4) | \
+ PIN_OSPEED_2M(GPIOA_PIN5) | \
+ PIN_OSPEED_2M(GPIOA_PIN6) | \
+ PIN_OSPEED_2M(GPIOA_PIN7) | \
+ PIN_OSPEED_2M(GPIOA_PIN8) | \
+ PIN_OSPEED_2M(GPIOA_PIN9) | \
+ PIN_OSPEED_2M(GPIOA_PIN10) | \
+ PIN_OSPEED_2M(GPIOA_PIN11) | \
+ PIN_OSPEED_2M(GPIOA_PIN12) | \
+ PIN_OSPEED_40M(GPIOA_SWDAT) | \
+ PIN_OSPEED_40M(GPIOA_SWCLK) | \
+ PIN_OSPEED_40M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDAT) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_PIN2) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_PIN7) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_PIN9) | \
+ PIN_ODR_HIGH(GPIOA_PIN10) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
+ PIN_ODR_HIGH(GPIOA_SWDAT) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOA_SWDAT, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - PIN3 (input pullup).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_INPUT(GPIOB_PIN3) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_PIN0) | \
+ PIN_OSPEED_2M(GPIOB_PIN1) | \
+ PIN_OSPEED_40M(GPIOB_PIN2) | \
+ PIN_OSPEED_40M(GPIOB_PIN3) | \
+ PIN_OSPEED_40M(GPIOB_PIN4) | \
+ PIN_OSPEED_2M(GPIOB_PIN5) | \
+ PIN_OSPEED_2M(GPIOB_PIN6) | \
+ PIN_OSPEED_2M(GPIOB_PIN7) | \
+ PIN_OSPEED_2M(GPIOB_PIN8) | \
+ PIN_OSPEED_2M(GPIOB_PIN9) | \
+ PIN_OSPEED_2M(GPIOB_PIN10) | \
+ PIN_OSPEED_2M(GPIOB_PIN11) | \
+ PIN_OSPEED_2M(GPIOB_PIN12) | \
+ PIN_OSPEED_2M(GPIOB_PIN13) | \
+ PIN_OSPEED_2M(GPIOB_PIN14) | \
+ PIN_OSPEED_2M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_PIN3) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - LED4 (output pushpull maximum).
+ * PC9 - LED3 (output pushpull maximum).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - PIN13 (input pullup).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_OUTPUT(GPIOC_LED4) | \
+ PIN_MODE_OUTPUT(GPIOC_LED3) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_LED4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) | \
+ PIN_OSPEED_2M(GPIOC_PIN1) | \
+ PIN_OSPEED_2M(GPIOC_PIN2) | \
+ PIN_OSPEED_2M(GPIOC_PIN3) | \
+ PIN_OSPEED_2M(GPIOC_PIN4) | \
+ PIN_OSPEED_2M(GPIOC_PIN5) | \
+ PIN_OSPEED_2M(GPIOC_PIN6) | \
+ PIN_OSPEED_2M(GPIOC_PIN7) | \
+ PIN_OSPEED_40M(GPIOC_LED4) | \
+ PIN_OSPEED_40M(GPIOC_LED3) | \
+ PIN_OSPEED_2M(GPIOC_PIN10) | \
+ PIN_OSPEED_2M(GPIOC_PIN11) | \
+ PIN_OSPEED_2M(GPIOC_PIN12) | \
+ PIN_OSPEED_2M(GPIOC_PIN13) | \
+ PIN_OSPEED_40M(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_40M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOC_LED4) | \
+ PIN_PUPDR_FLOATING(GPIOC_LED3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_LOW(GPIOC_LED4) | \
+ PIN_ODR_LOW(GPIOC_LED3) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_PIN13) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_LED4, 0) | \
+ PIN_AFIO_AF(GPIOC_LED3, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_2M(GPIOD_PIN0) | \
+ PIN_OSPEED_2M(GPIOD_PIN1) | \
+ PIN_OSPEED_2M(GPIOD_PIN2) | \
+ PIN_OSPEED_2M(GPIOD_PIN3) | \
+ PIN_OSPEED_2M(GPIOD_PIN4) | \
+ PIN_OSPEED_2M(GPIOD_PIN5) | \
+ PIN_OSPEED_2M(GPIOD_PIN6) | \
+ PIN_OSPEED_2M(GPIOD_PIN7) | \
+ PIN_OSPEED_2M(GPIOD_PIN8) | \
+ PIN_OSPEED_2M(GPIOD_PIN9) | \
+ PIN_OSPEED_2M(GPIOD_PIN10) | \
+ PIN_OSPEED_2M(GPIOD_PIN11) | \
+ PIN_OSPEED_2M(GPIOD_PIN12) | \
+ PIN_OSPEED_2M(GPIOD_PIN13) | \
+ PIN_OSPEED_2M(GPIOD_PIN14) | \
+ PIN_OSPEED_2M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - OSC_IN (input floating).
+ * PF1 - OSC_OUT (input floating).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOF_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_2M(GPIOF_OSC_IN) | \
+ PIN_OSPEED_2M(GPIOF_OSC_OUT) | \
+ PIN_OSPEED_2M(GPIOF_PIN2) | \
+ PIN_OSPEED_2M(GPIOF_PIN3) | \
+ PIN_OSPEED_2M(GPIOF_PIN4) | \
+ PIN_OSPEED_2M(GPIOF_PIN5) | \
+ PIN_OSPEED_2M(GPIOF_PIN6) | \
+ PIN_OSPEED_2M(GPIOF_PIN7) | \
+ PIN_OSPEED_2M(GPIOF_PIN8) | \
+ PIN_OSPEED_2M(GPIOF_PIN9) | \
+ PIN_OSPEED_2M(GPIOF_PIN10) | \
+ PIN_OSPEED_2M(GPIOF_PIN11) | \
+ PIN_OSPEED_2M(GPIOF_PIN12) | \
+ PIN_OSPEED_2M(GPIOF_PIN13) | \
+ PIN_OSPEED_2M(GPIOF_PIN14) | \
+ PIN_OSPEED_2M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOF_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F0_DISCOVERY/board.mk new file mode 100644 index 000000000..144ae4963 --- /dev/null +++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..3773f03d1 --- /dev/null +++ b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,667 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32F0xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f0xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path> + <output_path>..</output_path> + </configuration_settings> + <board_name>ST STM32F0-Discovery</board_name> + <board_id>ST_STM32F0_DISCOVERY</board_id> + <board_functions></board_functions> + <clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0" + LSEBypass="false" LSEDrive="3 High Drive (default)" /> + <ports> + <GPIOA> + <pin0 + ID="BUTTON" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="SWDAT" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Speed="Maximum" + Resistor="PullDown" + Level="High" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOB> + <GPIOC> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="LED4" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="Low" + Mode="Output" + Alternate="0" /> + <pin9 + ID="LED3" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="Low" + Mode="Output" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOD> + <GPIOF> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOF> + </ports> +</board> diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.c b/os/hal/boards/ST_STM32F3_DISCOVERY/board.c new file mode 100644 index 000000000..baafd6550 --- /dev/null +++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.c @@ -0,0 +1,102 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.h b/os/hal/boards/ST_STM32F3_DISCOVERY/board.h new file mode 100644 index 000000000..147dfb9b1 --- /dev/null +++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.h @@ -0,0 +1,891 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F3-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F3_DISCOVERY
+#define BOARD_NAME "STMicroelectronics STM32F3-Discovery"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 0
+#endif
+
+#define STM32_LSEDRV (3 << 3)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F30X
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+#define GPIOA_PIN1 1
+#define GPIOA_PIN2 2
+#define GPIOA_PIN3 3
+#define GPIOA_PIN4 4
+#define GPIOA_SPI1_SCK 5
+#define GPIOA_SPI1_MISO 6
+#define GPIOA_SPI1_MOSI 7
+#define GPIOA_PIN8 8
+#define GPIOA_PIN9 9
+#define GPIOA_PIN10 10
+#define GPIOA_USB_DM 11
+#define GPIOA_USB_DP 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_PIN15 15
+
+#define GPIOB_PIN0 0
+#define GPIOB_PIN1 1
+#define GPIOB_PIN2 2
+#define GPIOB_SWO 3
+#define GPIOB_PIN4 4
+#define GPIOB_PIN5 5
+#define GPIOB_I2C1_SCL 6
+#define GPIOB_I2C1_SDA 7
+#define GPIOB_PIN8 8
+#define GPIOB_PIN9 9
+#define GPIOB_PIN10 10
+#define GPIOB_PIN11 11
+#define GPIOB_PIN12 12
+#define GPIOB_PIN13 13
+#define GPIOB_PIN14 14
+#define GPIOB_PIN15 15
+
+#define GPIOC_PIN0 0
+#define GPIOC_PIN1 1
+#define GPIOC_PIN2 2
+#define GPIOC_PIN3 3
+#define GPIOC_PIN4 4
+#define GPIOC_PIN5 5
+#define GPIOC_PIN6 6
+#define GPIOC_PIN7 7
+#define GPIOC_PIN8 8
+#define GPIOC_PIN9 9
+#define GPIOC_PIN10 10
+#define GPIOC_PIN11 11
+#define GPIOC_PIN12 12
+#define GPIOC_PIN13 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_PIN2 2
+#define GPIOD_PIN3 3
+#define GPIOD_PIN4 4
+#define GPIOD_PIN5 5
+#define GPIOD_PIN6 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_PIN12 12
+#define GPIOD_PIN13 13
+#define GPIOD_PIN14 14
+#define GPIOD_PIN15 15
+
+#define GPIOE_L3GD20_INT1 0
+#define GPIOE_L3GD20_INT2 1
+#define GPIOE_LSM303_DRDY 2
+#define GPIOE_SPI1_CS 3
+#define GPIOE_LSM303_INT1 4
+#define GPIOE_LSM303_INT2 5
+#define GPIOE_PIN6 6
+#define GPIOE_PIN7 7
+#define GPIOE_LED4_BLUE 8
+#define GPIOE_LED3_RED 9
+#define GPIOE_LED5_ORANGE 10
+#define GPIOE_LED7_GREEN 11
+#define GPIOE_LED9_BLUE 12
+#define GPIOE_LED10_RED 13
+#define GPIOE_LED8_ORANGE 14
+#define GPIOE_LED6_GREEN 15
+
+#define GPIOF_OSC_IN 0
+#define GPIOF_OSC_OUT 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON (input floating).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - PIN2 (input pullup).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - SPI1_SCK (alternate 5).
+ * PA6 - SPI1_MISO (alternate 5).
+ * PA7 - SPI1_MOSI (alternate 5).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - PIN9 (input pullup).
+ * PA10 - PIN10 (input pullup).
+ * PA11 - USB_DM (alternate 14).
+ * PA12 - USB_DP (alternate 14).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_PIN2) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_PIN9) | \
+ PIN_MODE_INPUT(GPIOA_PIN10) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_BUTTON) | \
+ PIN_OSPEED_2M(GPIOA_PIN1) | \
+ PIN_OSPEED_2M(GPIOA_PIN2) | \
+ PIN_OSPEED_2M(GPIOA_PIN3) | \
+ PIN_OSPEED_2M(GPIOA_PIN4) | \
+ PIN_OSPEED_100M(GPIOA_SPI1_SCK) | \
+ PIN_OSPEED_100M(GPIOA_SPI1_MISO) | \
+ PIN_OSPEED_100M(GPIOA_SPI1_MOSI) | \
+ PIN_OSPEED_2M(GPIOA_PIN8) | \
+ PIN_OSPEED_2M(GPIOA_PIN9) | \
+ PIN_OSPEED_2M(GPIOA_PIN10) | \
+ PIN_OSPEED_100M(GPIOA_USB_DM) | \
+ PIN_OSPEED_2M(GPIOA_USB_DP) | \
+ PIN_OSPEED_100M(GPIOA_SWDIO) | \
+ PIN_OSPEED_100M(GPIOA_SWCLK) | \
+ PIN_OSPEED_2M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \
+ PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SPI1_MOSI) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_PIN2) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \
+ PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \
+ PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_PIN9) | \
+ PIN_ODR_HIGH(GPIOA_PIN10) | \
+ PIN_ODR_HIGH(GPIOA_USB_DM) | \
+ PIN_ODR_HIGH(GPIOA_USB_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) | \
+ PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) | \
+ PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOA_USB_DM, 14) | \
+ PIN_AFIO_AF(GPIOA_USB_DP, 14) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - I2C1_SCL (alternate 4).
+ * PB7 - I2C1_SDA (alternate 4).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_PIN0) | \
+ PIN_OSPEED_2M(GPIOB_PIN1) | \
+ PIN_OSPEED_2M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_SWO) | \
+ PIN_OSPEED_2M(GPIOB_PIN4) | \
+ PIN_OSPEED_2M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \
+ PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \
+ PIN_OSPEED_2M(GPIOB_PIN8) | \
+ PIN_OSPEED_2M(GPIOB_PIN9) | \
+ PIN_OSPEED_2M(GPIOB_PIN10) | \
+ PIN_OSPEED_2M(GPIOB_PIN11) | \
+ PIN_OSPEED_2M(GPIOB_PIN12) | \
+ PIN_OSPEED_2M(GPIOB_PIN13) | \
+ PIN_OSPEED_2M(GPIOB_PIN14) | \
+ PIN_OSPEED_2M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
+ PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SDA, 4))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - PIN13 (input pullup).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) | \
+ PIN_OSPEED_2M(GPIOC_PIN1) | \
+ PIN_OSPEED_2M(GPIOC_PIN2) | \
+ PIN_OSPEED_2M(GPIOC_PIN3) | \
+ PIN_OSPEED_2M(GPIOC_PIN4) | \
+ PIN_OSPEED_2M(GPIOC_PIN5) | \
+ PIN_OSPEED_2M(GPIOC_PIN6) | \
+ PIN_OSPEED_2M(GPIOC_PIN7) | \
+ PIN_OSPEED_2M(GPIOC_PIN8) | \
+ PIN_OSPEED_2M(GPIOC_PIN9) | \
+ PIN_OSPEED_2M(GPIOC_PIN10) | \
+ PIN_OSPEED_2M(GPIOC_PIN11) | \
+ PIN_OSPEED_2M(GPIOC_PIN12) | \
+ PIN_OSPEED_2M(GPIOC_PIN13) | \
+ PIN_OSPEED_100M(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_100M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_PIN13) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_2M(GPIOD_PIN0) | \
+ PIN_OSPEED_2M(GPIOD_PIN1) | \
+ PIN_OSPEED_2M(GPIOD_PIN2) | \
+ PIN_OSPEED_2M(GPIOD_PIN3) | \
+ PIN_OSPEED_2M(GPIOD_PIN4) | \
+ PIN_OSPEED_2M(GPIOD_PIN5) | \
+ PIN_OSPEED_2M(GPIOD_PIN6) | \
+ PIN_OSPEED_2M(GPIOD_PIN7) | \
+ PIN_OSPEED_2M(GPIOD_PIN8) | \
+ PIN_OSPEED_2M(GPIOD_PIN9) | \
+ PIN_OSPEED_2M(GPIOD_PIN10) | \
+ PIN_OSPEED_2M(GPIOD_PIN11) | \
+ PIN_OSPEED_2M(GPIOD_PIN12) | \
+ PIN_OSPEED_2M(GPIOD_PIN13) | \
+ PIN_OSPEED_2M(GPIOD_PIN14) | \
+ PIN_OSPEED_2M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - L3GD20_INT1 (input pullup).
+ * PE1 - L3GD20_INT2 (input pullup).
+ * PE2 - LSM303_DRDY (input pullup).
+ * PE3 - SPI1_CS (output pushpull maximum).
+ * PE4 - LSM303_INT1 (input pullup).
+ * PE5 - LSM303_INT2 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - LED4_BLUE (output pushpull maximum).
+ * PE9 - LED3_RED (output pushpull maximum).
+ * PE10 - LED5_ORANGE (output pushpull maximum).
+ * PE11 - LED7_GREEN (output pushpull maximum).
+ * PE12 - LED9_BLUE (output pushpull maximum).
+ * PE13 - LED10_RED (output pushpull maximum).
+ * PE14 - LED8_ORANGE (output pushpull maximum).
+ * PE15 - LED6_GREEN (output pushpull maximum).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_L3GD20_INT1) | \
+ PIN_MODE_INPUT(GPIOE_L3GD20_INT2) | \
+ PIN_MODE_INPUT(GPIOE_LSM303_DRDY) | \
+ PIN_MODE_OUTPUT(GPIOE_SPI1_CS) | \
+ PIN_MODE_INPUT(GPIOE_LSM303_INT1) | \
+ PIN_MODE_INPUT(GPIOE_LSM303_INT2) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_OUTPUT(GPIOE_LED4_BLUE) | \
+ PIN_MODE_OUTPUT(GPIOE_LED3_RED) | \
+ PIN_MODE_OUTPUT(GPIOE_LED5_ORANGE) | \
+ PIN_MODE_OUTPUT(GPIOE_LED7_GREEN) | \
+ PIN_MODE_OUTPUT(GPIOE_LED9_BLUE) | \
+ PIN_MODE_OUTPUT(GPIOE_LED10_RED) | \
+ PIN_MODE_OUTPUT(GPIOE_LED8_ORANGE) | \
+ PIN_MODE_OUTPUT(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT1) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_L3GD20_INT2) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_LSM303_DRDY) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_SPI1_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LSM303_INT1) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_LSM303_INT2) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED4_BLUE) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED3_RED) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED5_ORANGE) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_LED7_GREEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED9_BLUE) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED10_RED) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED8_ORANGE) |\
+ PIN_OTYPE_PUSHPULL(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_2M(GPIOE_L3GD20_INT1) | \
+ PIN_OSPEED_2M(GPIOE_L3GD20_INT2) | \
+ PIN_OSPEED_2M(GPIOE_LSM303_DRDY) | \
+ PIN_OSPEED_100M(GPIOE_SPI1_CS) | \
+ PIN_OSPEED_2M(GPIOE_LSM303_INT1) | \
+ PIN_OSPEED_2M(GPIOE_LSM303_INT2) | \
+ PIN_OSPEED_2M(GPIOE_PIN6) | \
+ PIN_OSPEED_2M(GPIOE_PIN7) | \
+ PIN_OSPEED_100M(GPIOE_LED4_BLUE) | \
+ PIN_OSPEED_100M(GPIOE_LED3_RED) | \
+ PIN_OSPEED_100M(GPIOE_LED5_ORANGE) | \
+ PIN_OSPEED_100M(GPIOE_LED7_GREEN) | \
+ PIN_OSPEED_100M(GPIOE_LED9_BLUE) | \
+ PIN_OSPEED_100M(GPIOE_LED10_RED) | \
+ PIN_OSPEED_100M(GPIOE_LED8_ORANGE) | \
+ PIN_OSPEED_100M(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT1) | \
+ PIN_PUPDR_PULLUP(GPIOE_L3GD20_INT2) | \
+ PIN_PUPDR_PULLUP(GPIOE_LSM303_DRDY) | \
+ PIN_PUPDR_FLOATING(GPIOE_SPI1_CS) | \
+ PIN_PUPDR_PULLUP(GPIOE_LSM303_INT1) | \
+ PIN_PUPDR_PULLUP(GPIOE_LSM303_INT2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_LED4_BLUE) | \
+ PIN_PUPDR_PULLUP(GPIOE_LED3_RED) | \
+ PIN_PUPDR_PULLUP(GPIOE_LED5_ORANGE) | \
+ PIN_PUPDR_FLOATING(GPIOE_LED7_GREEN) | \
+ PIN_PUPDR_PULLUP(GPIOE_LED9_BLUE) | \
+ PIN_PUPDR_FLOATING(GPIOE_LED10_RED) | \
+ PIN_PUPDR_FLOATING(GPIOE_LED8_ORANGE) |\
+ PIN_PUPDR_FLOATING(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_L3GD20_INT1) | \
+ PIN_ODR_HIGH(GPIOE_L3GD20_INT2) | \
+ PIN_ODR_HIGH(GPIOE_LSM303_DRDY) | \
+ PIN_ODR_HIGH(GPIOE_SPI1_CS) | \
+ PIN_ODR_HIGH(GPIOE_LSM303_INT1) | \
+ PIN_ODR_HIGH(GPIOE_LSM303_INT2) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_LOW(GPIOE_LED4_BLUE) | \
+ PIN_ODR_LOW(GPIOE_LED3_RED) | \
+ PIN_ODR_LOW(GPIOE_LED5_ORANGE) | \
+ PIN_ODR_LOW(GPIOE_LED7_GREEN) | \
+ PIN_ODR_LOW(GPIOE_LED9_BLUE) | \
+ PIN_ODR_LOW(GPIOE_LED10_RED) | \
+ PIN_ODR_LOW(GPIOE_LED8_ORANGE) | \
+ PIN_ODR_LOW(GPIOE_LED6_GREEN))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_L3GD20_INT1, 0) | \
+ PIN_AFIO_AF(GPIOE_L3GD20_INT2, 0) | \
+ PIN_AFIO_AF(GPIOE_LSM303_DRDY, 0) | \
+ PIN_AFIO_AF(GPIOE_SPI1_CS, 0) | \
+ PIN_AFIO_AF(GPIOE_LSM303_INT1, 0) | \
+ PIN_AFIO_AF(GPIOE_LSM303_INT2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_LED4_BLUE, 0) | \
+ PIN_AFIO_AF(GPIOE_LED3_RED, 0) | \
+ PIN_AFIO_AF(GPIOE_LED5_ORANGE, 0) | \
+ PIN_AFIO_AF(GPIOE_LED7_GREEN, 0) | \
+ PIN_AFIO_AF(GPIOE_LED9_BLUE, 0) | \
+ PIN_AFIO_AF(GPIOE_LED10_RED, 0) | \
+ PIN_AFIO_AF(GPIOE_LED8_ORANGE, 0) | \
+ PIN_AFIO_AF(GPIOE_LED6_GREEN, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - OSC_IN (input floating).
+ * PF1 - OSC_OUT (input floating).
+ * PF2 - PIN2 (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - PIN7 (input pullup).
+ * PF8 - PIN8 (input pullup).
+ * PF9 - PIN9 (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - PIN12 (input pullup).
+ * PF13 - PIN13 (input pullup).
+ * PF14 - PIN14 (input pullup).
+ * PF15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOF_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOF_OSC_OUT) | \
+ PIN_OSPEED_2M(GPIOF_PIN2) | \
+ PIN_OSPEED_2M(GPIOF_PIN3) | \
+ PIN_OSPEED_2M(GPIOF_PIN4) | \
+ PIN_OSPEED_2M(GPIOF_PIN5) | \
+ PIN_OSPEED_2M(GPIOF_PIN6) | \
+ PIN_OSPEED_2M(GPIOF_PIN7) | \
+ PIN_OSPEED_2M(GPIOF_PIN8) | \
+ PIN_OSPEED_2M(GPIOF_PIN9) | \
+ PIN_OSPEED_2M(GPIOF_PIN10) | \
+ PIN_OSPEED_2M(GPIOF_PIN11) | \
+ PIN_OSPEED_2M(GPIOF_PIN12) | \
+ PIN_OSPEED_2M(GPIOF_PIN13) | \
+ PIN_OSPEED_2M(GPIOF_PIN14) | \
+ PIN_OSPEED_2M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOF_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOF_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk new file mode 100644 index 000000000..522082fe9 --- /dev/null +++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM32F3_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM32F3_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..cbd264d03 --- /dev/null +++ b/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,798 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F3xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f3xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32f3xx/templates</templates_path>
+ <output_path>..</output_path>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32F3-Discovery</board_name>
+ <board_id>ST_STM32F3_DISCOVERY</board_id>
+ <board_functions></board_functions>
+ <subtype>STM32F30X</subtype>
+ <clocks HSEFrequency="8000000" HSEBypass="true" LSEFrequency="0"
+ LSEBypass="false" LSEDrive="3 High Drive (default)" />
+ <ports>
+ <GPIOA>
+ <pin0
+ ID="BUTTON"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="SPI1_SCK"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="5" ></pin5>
+ <pin6
+ ID="SPI1_MISO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Alternate"
+ Alternate="5" />
+ <pin7
+ ID="SPI1_MOSI"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="5" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="USB_DM"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="14" />
+ <pin12
+ ID="USB_DP"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="14" ></pin12>
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullDown"
+ Level="High"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="SWO"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin5>
+ <pin6
+ ID="I2C1_SCL"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="4" />
+ <pin7
+ ID="I2C1_SDA"
+ Type="OpenDrain"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Alternate"
+ Alternate="4" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="OSC32_IN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="OSC32_OUT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID="L3GD20_INT1"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="L3GD20_INT2"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="LSM303_DRDY"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="SPI1_CS"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Output"
+ Alternate="0" ></pin3>
+ <pin4
+ ID="LSM303_INT1"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="LSM303_INT2"
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="LED4_BLUE"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin9
+ ID="LED3_RED"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin10
+ ID="LED5_ORANGE"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin11
+ ID="LED7_GREEN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin12
+ ID="LED9_BLUE"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin13
+ ID="LED10_RED"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" ></pin13>
+ <pin14
+ ID="LED8_ORANGE"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ <pin15
+ ID="LED6_GREEN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="Low"
+ Mode="Output"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Speed="Maximum"
+ Resistor="Floating"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin1>
+ <pin2
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" ></pin3>
+ <pin4
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Level="High"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOF>
+ </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.c b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c new file mode 100644 index 000000000..99569f695 --- /dev/null +++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c @@ -0,0 +1,108 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.h b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h new file mode 100644 index 000000000..6e636db9e --- /dev/null +++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.h @@ -0,0 +1,1297 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F4_DISCOVERY
+#define BOARD_NAME "STMicroelectronics STM32F4-Discovery"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 0
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000
+#endif
+
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+#define GPIOA_PIN1 1
+#define GPIOA_PIN2 2
+#define GPIOA_PIN3 3
+#define GPIOA_LRCK 4
+#define GPIOA_SPC 5
+#define GPIOA_SDO 6
+#define GPIOA_SDI 7
+#define GPIOA_PIN8 8
+#define GPIOA_VBUS_FS 9
+#define GPIOA_OTG_FS_ID 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_PIN15 15
+
+#define GPIOB_PIN0 0
+#define GPIOB_PIN1 1
+#define GPIOB_PIN2 2
+#define GPIOB_SWO 3
+#define GPIOB_PIN4 4
+#define GPIOB_PIN5 5
+#define GPIOB_SCL 6
+#define GPIOB_PIN7 7
+#define GPIOB_PIN8 8
+#define GPIOB_SDA 9
+#define GPIOB_CLK_IN 10
+#define GPIOB_PIN11 11
+#define GPIOB_PIN12 12
+#define GPIOB_PIN13 13
+#define GPIOB_PIN14 14
+#define GPIOB_PIN15 15
+
+#define GPIOC_OTG_FS_POWER_ON 0
+#define GPIOC_PIN1 1
+#define GPIOC_PIN2 2
+#define GPIOC_PDM_OUT 3
+#define GPIOC_PIN4 4
+#define GPIOC_PIN5 5
+#define GPIOC_PIN6 6
+#define GPIOC_MCLK 7
+#define GPIOC_PIN8 8
+#define GPIOC_PIN9 9
+#define GPIOC_SCLK 10
+#define GPIOC_PIN11 11
+#define GPIOC_SDIN 12
+#define GPIOC_PIN13 13
+#define GPIOC_PIN14 14
+#define GPIOC_PIN15 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_PIN2 2
+#define GPIOD_PIN3 3
+#define GPIOD_RESET 4
+#define GPIOD_OVER_CURRENT 5
+#define GPIOD_PIN6 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_LED4 12
+#define GPIOD_LED3 13
+#define GPIOD_LED5 14
+#define GPIOD_LED6 15
+
+#define GPIOE_INT1 0
+#define GPIOE_INT2 1
+#define GPIOE_PIN2 2
+#define GPIOE_CS_SPI 3
+#define GPIOE_PIN4 4
+#define GPIOE_PIN5 5
+#define GPIOE_PIN6 6
+#define GPIOE_PIN7 7
+#define GPIOE_PIN8 8
+#define GPIOE_PIN9 9
+#define GPIOE_PIN10 10
+#define GPIOE_PIN11 11
+#define GPIOE_PIN12 12
+#define GPIOE_PIN13 13
+#define GPIOE_PIN14 14
+#define GPIOE_PIN15 15
+
+#define GPIOF_PIN0 0
+#define GPIOF_PIN1 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+#define GPIOG_PIN0 0
+#define GPIOG_PIN1 1
+#define GPIOG_PIN2 2
+#define GPIOG_PIN3 3
+#define GPIOG_PIN4 4
+#define GPIOG_PIN5 5
+#define GPIOG_PIN6 6
+#define GPIOG_PIN7 7
+#define GPIOG_PIN8 8
+#define GPIOG_PIN9 9
+#define GPIOG_PIN10 10
+#define GPIOG_PIN11 11
+#define GPIOG_PIN12 12
+#define GPIOG_PIN13 13
+#define GPIOG_PIN14 14
+#define GPIOG_PIN15 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+#define GPIOH_PIN2 2
+#define GPIOH_PIN3 3
+#define GPIOH_PIN4 4
+#define GPIOH_PIN5 5
+#define GPIOH_PIN6 6
+#define GPIOH_PIN7 7
+#define GPIOH_PIN8 8
+#define GPIOH_PIN9 9
+#define GPIOH_PIN10 10
+#define GPIOH_PIN11 11
+#define GPIOH_PIN12 12
+#define GPIOH_PIN13 13
+#define GPIOH_PIN14 14
+#define GPIOH_PIN15 15
+
+#define GPIOI_PIN0 0
+#define GPIOI_PIN1 1
+#define GPIOI_PIN2 2
+#define GPIOI_PIN3 3
+#define GPIOI_PIN4 4
+#define GPIOI_PIN5 5
+#define GPIOI_PIN6 6
+#define GPIOI_PIN7 7
+#define GPIOI_PIN8 8
+#define GPIOI_PIN9 9
+#define GPIOI_PIN10 10
+#define GPIOI_PIN11 11
+#define GPIOI_PIN12 12
+#define GPIOI_PIN13 13
+#define GPIOI_PIN14 14
+#define GPIOI_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON (input floating).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - PIN2 (input pullup).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - LRCK (alternate 6).
+ * PA5 - SPC (alternate 5).
+ * PA6 - SDO (alternate 5).
+ * PA7 - SDI (alternate 5).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - VBUS_FS (input floating).
+ * PA10 - OTG_FS_ID (alternate 10).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_PIN2) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_ALTERNATE(GPIOA_LRCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPC) | \
+ PIN_MODE_ALTERNATE(GPIOA_SDO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SDI) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_VBUS_FS) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \
+ PIN_OSPEED_100M(GPIOA_PIN1) | \
+ PIN_OSPEED_100M(GPIOA_PIN2) | \
+ PIN_OSPEED_100M(GPIOA_PIN3) | \
+ PIN_OSPEED_100M(GPIOA_LRCK) | \
+ PIN_OSPEED_50M(GPIOA_SPC) | \
+ PIN_OSPEED_50M(GPIOA_SDO) | \
+ PIN_OSPEED_50M(GPIOA_SDI) | \
+ PIN_OSPEED_100M(GPIOA_PIN8) | \
+ PIN_OSPEED_100M(GPIOA_VBUS_FS) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_100M(GPIOA_SWDIO) | \
+ PIN_OSPEED_100M(GPIOA_SWCLK) | \
+ PIN_OSPEED_100M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOA_LRCK) | \
+ PIN_PUPDR_FLOATING(GPIOA_SPC) | \
+ PIN_PUPDR_FLOATING(GPIOA_SDO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SDI) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_PIN2) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_LRCK) | \
+ PIN_ODR_HIGH(GPIOA_SPC) | \
+ PIN_ODR_HIGH(GPIOA_SDO) | \
+ PIN_ODR_HIGH(GPIOA_SDI) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_VBUS_FS) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_LRCK, 6) | \
+ PIN_AFIO_AF(GPIOA_SPC, 5) | \
+ PIN_AFIO_AF(GPIOA_SDO, 5) | \
+ PIN_AFIO_AF(GPIOA_SDI, 5))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - SCL (alternate 4).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - SDA (alternate 4).
+ * PB10 - CLK_IN (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_ALTERNATE(GPIOB_SCL) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_ALTERNATE(GPIOB_SDA) | \
+ PIN_MODE_INPUT(GPIOB_CLK_IN) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \
+ PIN_OSPEED_100M(GPIOB_PIN1) | \
+ PIN_OSPEED_100M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_SWO) | \
+ PIN_OSPEED_100M(GPIOB_PIN4) | \
+ PIN_OSPEED_100M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_SCL) | \
+ PIN_OSPEED_100M(GPIOB_PIN7) | \
+ PIN_OSPEED_100M(GPIOB_PIN8) | \
+ PIN_OSPEED_100M(GPIOB_SDA) | \
+ PIN_OSPEED_100M(GPIOB_CLK_IN) | \
+ PIN_OSPEED_100M(GPIOB_PIN11) | \
+ PIN_OSPEED_100M(GPIOB_PIN12) | \
+ PIN_OSPEED_100M(GPIOB_PIN13) | \
+ PIN_OSPEED_100M(GPIOB_PIN14) | \
+ PIN_OSPEED_100M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_SCL) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOB_SDA) | \
+ PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_SCL) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_SDA) | \
+ PIN_ODR_HIGH(GPIOB_CLK_IN) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_SDA, 4) | \
+ PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - OTG_FS_POWER_ON (output pushpull maximum).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PDM_OUT (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - MCLK (alternate 6).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - SCLK (alternate 6).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - SDIN (alternate 6).
+ * PC13 - PIN13 (input pullup).
+ * PC14 - PIN14 (input pullup).
+ * PC15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PDM_OUT) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOC_MCLK) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_ALTERNATE(GPIOC_SCLK) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIN) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDIN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_OSPEED_100M(GPIOC_PIN1) | \
+ PIN_OSPEED_100M(GPIOC_PIN2) | \
+ PIN_OSPEED_100M(GPIOC_PDM_OUT) | \
+ PIN_OSPEED_100M(GPIOC_PIN4) | \
+ PIN_OSPEED_100M(GPIOC_PIN5) | \
+ PIN_OSPEED_100M(GPIOC_PIN6) | \
+ PIN_OSPEED_100M(GPIOC_MCLK) | \
+ PIN_OSPEED_100M(GPIOC_PIN8) | \
+ PIN_OSPEED_100M(GPIOC_PIN9) | \
+ PIN_OSPEED_100M(GPIOC_SCLK) | \
+ PIN_OSPEED_100M(GPIOC_PIN11) | \
+ PIN_OSPEED_100M(GPIOC_SDIN) | \
+ PIN_OSPEED_100M(GPIOC_PIN13) | \
+ PIN_OSPEED_100M(GPIOC_PIN14) | \
+ PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOC_MCLK) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOC_SCLK) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDIN) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PDM_OUT) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_MCLK) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_SCLK) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_SDIN) | \
+ PIN_ODR_HIGH(GPIOC_PIN13) | \
+ PIN_ODR_HIGH(GPIOC_PIN14) | \
+ PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_MCLK, 6))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOC_SCLK, 6) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOC_SDIN, 6) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - RESET (output pushpull maximum).
+ * PD5 - OVER_CURRENT (input floating).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - LED4 (output pushpull maximum).
+ * PD13 - LED3 (output pushpull maximum).
+ * PD14 - LED5 (output pushpull maximum).
+ * PD15 - LED6 (output pushpull maximum).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_OUTPUT(GPIOD_RESET) | \
+ PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_OUTPUT(GPIOD_LED4) | \
+ PIN_MODE_OUTPUT(GPIOD_LED3) | \
+ PIN_MODE_OUTPUT(GPIOD_LED5) | \
+ PIN_MODE_OUTPUT(GPIOD_LED6))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED6))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
+ PIN_OSPEED_100M(GPIOD_PIN1) | \
+ PIN_OSPEED_100M(GPIOD_PIN2) | \
+ PIN_OSPEED_100M(GPIOD_PIN3) | \
+ PIN_OSPEED_100M(GPIOD_RESET) | \
+ PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \
+ PIN_OSPEED_100M(GPIOD_PIN6) | \
+ PIN_OSPEED_100M(GPIOD_PIN7) | \
+ PIN_OSPEED_100M(GPIOD_PIN8) | \
+ PIN_OSPEED_100M(GPIOD_PIN9) | \
+ PIN_OSPEED_100M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_PIN11) | \
+ PIN_OSPEED_100M(GPIOD_LED4) | \
+ PIN_OSPEED_100M(GPIOD_LED3) | \
+ PIN_OSPEED_100M(GPIOD_LED5) | \
+ PIN_OSPEED_100M(GPIOD_LED6))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOD_RESET) | \
+ PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED4) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED3) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED5) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED6))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_RESET) | \
+ PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_LOW(GPIOD_LED4) | \
+ PIN_ODR_LOW(GPIOD_LED3) | \
+ PIN_ODR_LOW(GPIOD_LED5) | \
+ PIN_ODR_LOW(GPIOD_LED6))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_RESET, 0) | \
+ PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_LED4, 0) | \
+ PIN_AFIO_AF(GPIOD_LED3, 0) | \
+ PIN_AFIO_AF(GPIOD_LED5, 0) | \
+ PIN_AFIO_AF(GPIOD_LED6, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - INT1 (input floating).
+ * PE1 - INT2 (input floating).
+ * PE2 - PIN2 (input floating).
+ * PE3 - CS_SPI (output pushpull maximum).
+ * PE4 - PIN4 (input floating).
+ * PE5 - PIN5 (input floating).
+ * PE6 - PIN6 (input floating).
+ * PE7 - PIN7 (input floating).
+ * PE8 - PIN8 (input floating).
+ * PE9 - PIN9 (input floating).
+ * PE10 - PIN10 (input floating).
+ * PE11 - PIN11 (input floating).
+ * PE12 - PIN12 (input floating).
+ * PE13 - PIN13 (input floating).
+ * PE14 - PIN14 (input floating).
+ * PE15 - PIN15 (input floating).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \
+ PIN_MODE_INPUT(GPIOE_INT2) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \
+ PIN_OSPEED_100M(GPIOE_INT2) | \
+ PIN_OSPEED_100M(GPIOE_PIN2) | \
+ PIN_OSPEED_100M(GPIOE_CS_SPI) | \
+ PIN_OSPEED_100M(GPIOE_PIN4) | \
+ PIN_OSPEED_100M(GPIOE_PIN5) | \
+ PIN_OSPEED_100M(GPIOE_PIN6) | \
+ PIN_OSPEED_100M(GPIOE_PIN7) | \
+ PIN_OSPEED_100M(GPIOE_PIN8) | \
+ PIN_OSPEED_100M(GPIOE_PIN9) | \
+ PIN_OSPEED_100M(GPIOE_PIN10) | \
+ PIN_OSPEED_100M(GPIOE_PIN11) | \
+ PIN_OSPEED_100M(GPIOE_PIN12) | \
+ PIN_OSPEED_100M(GPIOE_PIN13) | \
+ PIN_OSPEED_100M(GPIOE_PIN14) | \
+ PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \
+ PIN_PUPDR_FLOATING(GPIOE_INT2) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \
+ PIN_ODR_HIGH(GPIOE_INT2) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_CS_SPI) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \
+ PIN_AFIO_AF(GPIOE_INT2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input floating).
+ * PF1 - PIN1 (input floating).
+ * PF2 - PIN2 (input floating).
+ * PF3 - PIN3 (input floating).
+ * PF4 - PIN4 (input floating).
+ * PF5 - PIN5 (input floating).
+ * PF6 - PIN6 (input floating).
+ * PF7 - PIN7 (input floating).
+ * PF8 - PIN8 (input floating).
+ * PF9 - PIN9 (input floating).
+ * PF10 - PIN10 (input floating).
+ * PF11 - PIN11 (input floating).
+ * PF12 - PIN12 (input floating).
+ * PF13 - PIN13 (input floating).
+ * PF14 - PIN14 (input floating).
+ * PF15 - PIN15 (input floating).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
+ PIN_OSPEED_100M(GPIOF_PIN1) | \
+ PIN_OSPEED_100M(GPIOF_PIN2) | \
+ PIN_OSPEED_100M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_PIN4) | \
+ PIN_OSPEED_100M(GPIOF_PIN5) | \
+ PIN_OSPEED_100M(GPIOF_PIN6) | \
+ PIN_OSPEED_100M(GPIOF_PIN7) | \
+ PIN_OSPEED_100M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_PIN9) | \
+ PIN_OSPEED_100M(GPIOF_PIN10) | \
+ PIN_OSPEED_100M(GPIOF_PIN11) | \
+ PIN_OSPEED_100M(GPIOF_PIN12) | \
+ PIN_OSPEED_100M(GPIOF_PIN13) | \
+ PIN_OSPEED_100M(GPIOF_PIN14) | \
+ PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input floating).
+ * PG1 - PIN1 (input floating).
+ * PG2 - PIN2 (input floating).
+ * PG3 - PIN3 (input floating).
+ * PG4 - PIN4 (input floating).
+ * PG5 - PIN5 (input floating).
+ * PG6 - PIN6 (input floating).
+ * PG7 - PIN7 (input floating).
+ * PG8 - PIN8 (input floating).
+ * PG9 - PIN9 (input floating).
+ * PG10 - PIN10 (input floating).
+ * PG11 - PIN11 (input floating).
+ * PG12 - PIN12 (input floating).
+ * PG13 - PIN13 (input floating).
+ * PG14 - PIN14 (input floating).
+ * PG15 - PIN15 (input floating).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_INPUT(GPIOG_PIN11) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_INPUT(GPIOG_PIN13) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
+ PIN_OSPEED_100M(GPIOG_PIN1) | \
+ PIN_OSPEED_100M(GPIOG_PIN2) | \
+ PIN_OSPEED_100M(GPIOG_PIN3) | \
+ PIN_OSPEED_100M(GPIOG_PIN4) | \
+ PIN_OSPEED_100M(GPIOG_PIN5) | \
+ PIN_OSPEED_100M(GPIOG_PIN6) | \
+ PIN_OSPEED_100M(GPIOG_PIN7) | \
+ PIN_OSPEED_100M(GPIOG_PIN8) | \
+ PIN_OSPEED_100M(GPIOG_PIN9) | \
+ PIN_OSPEED_100M(GPIOG_PIN10) | \
+ PIN_OSPEED_100M(GPIOG_PIN11) | \
+ PIN_OSPEED_100M(GPIOG_PIN12) | \
+ PIN_OSPEED_100M(GPIOG_PIN13) | \
+ PIN_OSPEED_100M(GPIOG_PIN14) | \
+ PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input floating).
+ * PH3 - PIN3 (input floating).
+ * PH4 - PIN4 (input floating).
+ * PH5 - PIN5 (input floating).
+ * PH6 - PIN6 (input floating).
+ * PH7 - PIN7 (input floating).
+ * PH8 - PIN8 (input floating).
+ * PH9 - PIN9 (input floating).
+ * PH10 - PIN10 (input floating).
+ * PH11 - PIN11 (input floating).
+ * PH12 - PIN12 (input floating).
+ * PH13 - PIN13 (input floating).
+ * PH14 - PIN14 (input floating).
+ * PH15 - PIN15 (input floating).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_100M(GPIOH_PIN2) | \
+ PIN_OSPEED_100M(GPIOH_PIN3) | \
+ PIN_OSPEED_100M(GPIOH_PIN4) | \
+ PIN_OSPEED_100M(GPIOH_PIN5) | \
+ PIN_OSPEED_100M(GPIOH_PIN6) | \
+ PIN_OSPEED_100M(GPIOH_PIN7) | \
+ PIN_OSPEED_100M(GPIOH_PIN8) | \
+ PIN_OSPEED_100M(GPIOH_PIN9) | \
+ PIN_OSPEED_100M(GPIOH_PIN10) | \
+ PIN_OSPEED_100M(GPIOH_PIN11) | \
+ PIN_OSPEED_100M(GPIOH_PIN12) | \
+ PIN_OSPEED_100M(GPIOH_PIN13) | \
+ PIN_OSPEED_100M(GPIOH_PIN14) | \
+ PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input floating).
+ * PI1 - PIN1 (input floating).
+ * PI2 - PIN2 (input floating).
+ * PI3 - PIN3 (input floating).
+ * PI4 - PIN4 (input floating).
+ * PI5 - PIN5 (input floating).
+ * PI6 - PIN6 (input floating).
+ * PI7 - PIN7 (input floating).
+ * PI8 - PIN8 (input floating).
+ * PI9 - PIN9 (input floating).
+ * PI10 - PIN10 (input floating).
+ * PI11 - PIN11 (input floating).
+ * PI12 - PIN12 (input floating).
+ * PI13 - PIN13 (input floating).
+ * PI14 - PIN14 (input floating).
+ * PI15 - PIN15 (input floating).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
+ PIN_OSPEED_100M(GPIOI_PIN1) | \
+ PIN_OSPEED_100M(GPIOI_PIN2) | \
+ PIN_OSPEED_100M(GPIOI_PIN3) | \
+ PIN_OSPEED_100M(GPIOI_PIN4) | \
+ PIN_OSPEED_100M(GPIOI_PIN5) | \
+ PIN_OSPEED_100M(GPIOI_PIN6) | \
+ PIN_OSPEED_100M(GPIOI_PIN7) | \
+ PIN_OSPEED_100M(GPIOI_PIN8) | \
+ PIN_OSPEED_100M(GPIOI_PIN9) | \
+ PIN_OSPEED_100M(GPIOI_PIN10) | \
+ PIN_OSPEED_100M(GPIOI_PIN11) | \
+ PIN_OSPEED_100M(GPIOI_PIN12) | \
+ PIN_OSPEED_100M(GPIOI_PIN13) | \
+ PIN_OSPEED_100M(GPIOI_PIN14) | \
+ PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk new file mode 100644 index 000000000..eb47aa2af --- /dev/null +++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM32F4_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..e30de70e6 --- /dev/null +++ b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,1186 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+ <output_path>..</output_path>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32F4-Discovery</board_name>
+ <board_id>ST_STM32F4_DISCOVERY</board_id>
+ <board_functions></board_functions>
+ <clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="0" VDD="300" />
+ <ports>
+ <GPIOA>
+ <pin0
+ ID="BUTTON"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="LRCK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="6" />
+ <pin5
+ ID="SPC"
+ Type="PushPull"
+ Level="High"
+ Speed="High"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="5" />
+ <pin6
+ ID="SDO"
+ Type="PushPull"
+ Level="High"
+ Speed="High"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="5" />
+ <pin7
+ ID="SDI"
+ Type="PushPull"
+ Level="High"
+ Speed="High"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="5" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" ></pin8>
+ <pin9
+ ID="VBUS_FS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID="OTG_FS_ID"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin11
+ ID="OTG_FS_DM"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin12
+ ID="OTG_FS_DP"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="SWO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" ></pin3>
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="SCL"
+ Type="OpenDrain"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="4" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="SDA"
+ Type="OpenDrain"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="4" ></pin9>
+ <pin10
+ ID="CLK_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID="OTG_FS_POWER_ON"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="PDM_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" ></pin3>
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="MCLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="6" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID="SCLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="6" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID="SDIN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="6" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="RESET"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin5
+ ID="OVER_CURRENT"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" ></pin5>
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID="LED4"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin13
+ ID="LED3"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin14
+ ID="LED5"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" ></pin14>
+ <pin15
+ ID="LED6"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID="INT1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="INT2"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="CS_SPI"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOG>
+ <GPIOH>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" ></pin2>
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOH>
+ <GPIOI>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOI>
+ </ports>
+</board>
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.c b/os/hal/boards/ST_STM32L_DISCOVERY/board.c new file mode 100644 index 000000000..3d5ff42d9 --- /dev/null +++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.c @@ -0,0 +1,102 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.h b/os/hal/boards/ST_STM32L_DISCOVERY/board.h new file mode 100644 index 000000000..efbd86dae --- /dev/null +++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.h @@ -0,0 +1,890 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for ST STM32L-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32L_DISCOVERY
+#define BOARD_NAME "ST STM32L-Discovery"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: HSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 0
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header file stm32l1xx.h.
+ */
+#define STM32L1XX_MD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+#define GPIOA_PIN1 1
+#define GPIOA_PIN2 2
+#define GPIOA_PIN3 3
+#define GPIOA_PIN4 4
+#define GPIOA_PIN5 5
+#define GPIOA_PIN6 6
+#define GPIOA_PIN7 7
+#define GPIOA_PIN8 8
+#define GPIOA_PIN9 9
+#define GPIOA_PIN10 10
+#define GPIOA_PIN11 11
+#define GPIOA_PIN12 12
+#define GPIOA_JTAG_TMS 13
+#define GPIOA_JTAG_TCK 14
+#define GPIOA_JTAG_TDI 15
+
+#define GPIOB_PIN0 0
+#define GPIOB_PIN1 1
+#define GPIOB_BOOT1 2
+#define GPIOB_JTAG_TDO 3
+#define GPIOB_JTAG_TRST 4
+#define GPIOB_PIN5 5
+#define GPIOB_LED4 6
+#define GPIOB_LED3 7
+#define GPIOB_PIN8 8
+#define GPIOB_PIN9 9
+#define GPIOB_PIN10 10
+#define GPIOB_PIN11 11
+#define GPIOB_PIN12 12
+#define GPIOB_PIN13 13
+#define GPIOB_PIN14 14
+#define GPIOB_PIN15 15
+
+#define GPIOC_PIN0 0
+#define GPIOC_PIN1 1
+#define GPIOC_PIN2 2
+#define GPIOC_PIN3 3
+#define GPIOC_PIN4 4
+#define GPIOC_PIN5 5
+#define GPIOC_PIN6 6
+#define GPIOC_PIN7 7
+#define GPIOC_PIN8 8
+#define GPIOC_PIN9 9
+#define GPIOC_PIN10 10
+#define GPIOC_PIN11 11
+#define GPIOC_PIN12 12
+#define GPIOC_PIN13 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_PIN2 2
+#define GPIOD_PIN3 3
+#define GPIOD_PIN4 4
+#define GPIOD_PIN5 5
+#define GPIOD_PIN6 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_PIN12 12
+#define GPIOD_PIN13 13
+#define GPIOD_PIN14 14
+#define GPIOD_PIN15 15
+
+#define GPIOE_PIN0 0
+#define GPIOE_PIN1 1
+#define GPIOE_PIN2 2
+#define GPIOE_PIN3 3
+#define GPIOE_PIN4 4
+#define GPIOE_PIN5 5
+#define GPIOE_PIN6 6
+#define GPIOE_PIN7 7
+#define GPIOE_PIN8 8
+#define GPIOE_PIN9 9
+#define GPIOE_PIN10 10
+#define GPIOE_PIN11 11
+#define GPIOE_PIN12 12
+#define GPIOE_PIN13 13
+#define GPIOE_PIN14 14
+#define GPIOE_PIN15 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+#define GPIOH_PIN2 2
+#define GPIOH_PIN3 3
+#define GPIOH_PIN4 4
+#define GPIOH_PIN5 5
+#define GPIOH_PIN6 6
+#define GPIOH_PIN7 7
+#define GPIOH_PIN8 8
+#define GPIOH_PIN9 9
+#define GPIOH_PIN10 10
+#define GPIOH_PIN11 11
+#define GPIOH_PIN12 12
+#define GPIOH_PIN13 13
+#define GPIOH_PIN14 14
+#define GPIOH_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_400K(n) (0U << ((n) * 2))
+#define PIN_OSPEED_2M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_10M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_40M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON (input floating).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - PIN2 (input pullup).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - PIN5 (input pullup).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - PIN7 (input pullup).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - PIN9 (input pullup).
+ * PA10 - PIN10 (input pullup).
+ * PA11 - PIN11 (input pullup).
+ * PA12 - PIN12 (input pullup).
+ * PA13 - JTAG_TMS (alternate 0).
+ * PA14 - JTAG_TCK (alternate 0).
+ * PA15 - JTAG_TDI (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_PIN2) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_INPUT(GPIOA_PIN5) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_INPUT(GPIOA_PIN7) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_PIN9) | \
+ PIN_MODE_INPUT(GPIOA_PIN10) | \
+ PIN_MODE_INPUT(GPIOA_PIN11) | \
+ PIN_MODE_INPUT(GPIOA_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_400K(GPIOA_BUTTON) | \
+ PIN_OSPEED_400K(GPIOA_PIN1) | \
+ PIN_OSPEED_400K(GPIOA_PIN2) | \
+ PIN_OSPEED_400K(GPIOA_PIN3) | \
+ PIN_OSPEED_400K(GPIOA_PIN4) | \
+ PIN_OSPEED_400K(GPIOA_PIN5) | \
+ PIN_OSPEED_400K(GPIOA_PIN6) | \
+ PIN_OSPEED_400K(GPIOA_PIN7) | \
+ PIN_OSPEED_400K(GPIOA_PIN8) | \
+ PIN_OSPEED_400K(GPIOA_PIN9) | \
+ PIN_OSPEED_400K(GPIOA_PIN10) | \
+ PIN_OSPEED_400K(GPIOA_PIN11) | \
+ PIN_OSPEED_400K(GPIOA_PIN12) | \
+ PIN_OSPEED_40M(GPIOA_JTAG_TMS) | \
+ PIN_OSPEED_40M(GPIOA_JTAG_TCK) | \
+ PIN_OSPEED_40M(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOA_JTAG_TMS) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \
+ PIN_PUPDR_PULLUP(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_PIN2) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_PIN7) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_PIN9) | \
+ PIN_ODR_HIGH(GPIOA_PIN10) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \
+ PIN_ODR_HIGH(GPIOA_JTAG_TDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - BOOT1 (input floating).
+ * PB3 - JTAG_TDO (alternate 0).
+ * PB4 - JTAG_TRST (alternate 0).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - LED4 (output pushpull maximum).
+ * PB7 - LED3 (output pushpull maximum).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_BOOT1) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_OUTPUT(GPIOB_LED4) | \
+ PIN_MODE_OUTPUT(GPIOB_LED3) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LED4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_400K(GPIOB_PIN0) | \
+ PIN_OSPEED_400K(GPIOB_PIN1) | \
+ PIN_OSPEED_40M(GPIOB_BOOT1) | \
+ PIN_OSPEED_40M(GPIOB_JTAG_TDO) | \
+ PIN_OSPEED_40M(GPIOB_JTAG_TRST) | \
+ PIN_OSPEED_400K(GPIOB_PIN5) | \
+ PIN_OSPEED_40M(GPIOB_LED4) | \
+ PIN_OSPEED_40M(GPIOB_LED3) | \
+ PIN_OSPEED_400K(GPIOB_PIN8) | \
+ PIN_OSPEED_400K(GPIOB_PIN9) | \
+ PIN_OSPEED_400K(GPIOB_PIN10) | \
+ PIN_OSPEED_400K(GPIOB_PIN11) | \
+ PIN_OSPEED_400K(GPIOB_PIN12) | \
+ PIN_OSPEED_400K(GPIOB_PIN13) | \
+ PIN_OSPEED_400K(GPIOB_PIN14) | \
+ PIN_OSPEED_400K(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \
+ PIN_PUPDR_PULLUP(GPIOB_JTAG_TRST) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_LED4) | \
+ PIN_PUPDR_FLOATING(GPIOB_LED3) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_BOOT1) | \
+ PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \
+ PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_LOW(GPIOB_LED4) | \
+ PIN_ODR_LOW(GPIOB_LED3) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_BOOT1, 0) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_LED4, 0) | \
+ PIN_AFIO_AF(GPIOB_LED3, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - PIN13 (input pullup).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_400K(GPIOC_PIN0) | \
+ PIN_OSPEED_400K(GPIOC_PIN1) | \
+ PIN_OSPEED_400K(GPIOC_PIN2) | \
+ PIN_OSPEED_400K(GPIOC_PIN3) | \
+ PIN_OSPEED_400K(GPIOC_PIN4) | \
+ PIN_OSPEED_400K(GPIOC_PIN5) | \
+ PIN_OSPEED_400K(GPIOC_PIN6) | \
+ PIN_OSPEED_400K(GPIOC_PIN7) | \
+ PIN_OSPEED_400K(GPIOC_PIN8) | \
+ PIN_OSPEED_400K(GPIOC_PIN9) | \
+ PIN_OSPEED_400K(GPIOC_PIN10) | \
+ PIN_OSPEED_400K(GPIOC_PIN11) | \
+ PIN_OSPEED_400K(GPIOC_PIN12) | \
+ PIN_OSPEED_400K(GPIOC_PIN13) | \
+ PIN_OSPEED_40M(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_40M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_PIN13) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_400K(GPIOD_PIN0) | \
+ PIN_OSPEED_400K(GPIOD_PIN1) | \
+ PIN_OSPEED_400K(GPIOD_PIN2) | \
+ PIN_OSPEED_400K(GPIOD_PIN3) | \
+ PIN_OSPEED_400K(GPIOD_PIN4) | \
+ PIN_OSPEED_400K(GPIOD_PIN5) | \
+ PIN_OSPEED_400K(GPIOD_PIN6) | \
+ PIN_OSPEED_400K(GPIOD_PIN7) | \
+ PIN_OSPEED_400K(GPIOD_PIN8) | \
+ PIN_OSPEED_400K(GPIOD_PIN9) | \
+ PIN_OSPEED_400K(GPIOD_PIN10) | \
+ PIN_OSPEED_400K(GPIOD_PIN11) | \
+ PIN_OSPEED_400K(GPIOD_PIN12) | \
+ PIN_OSPEED_400K(GPIOD_PIN13) | \
+ PIN_OSPEED_400K(GPIOD_PIN14) | \
+ PIN_OSPEED_400K(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input pullup).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input pullup).
+ * PE5 - PIN5 (input pullup).
+ * PE6 - PIN6 (input pullup).
+ * PE7 - PIN7 (input pullup).
+ * PE8 - PIN8 (input pullup).
+ * PE9 - PIN9 (input pullup).
+ * PE10 - PIN10 (input pullup).
+ * PE11 - PIN11 (input pullup).
+ * PE12 - PIN12 (input pullup).
+ * PE13 - PIN13 (input pullup).
+ * PE14 - PIN14 (input pullup).
+ * PE15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_400K(GPIOE_PIN0) | \
+ PIN_OSPEED_400K(GPIOE_PIN1) | \
+ PIN_OSPEED_400K(GPIOE_PIN2) | \
+ PIN_OSPEED_400K(GPIOE_PIN3) | \
+ PIN_OSPEED_400K(GPIOE_PIN4) | \
+ PIN_OSPEED_400K(GPIOE_PIN5) | \
+ PIN_OSPEED_400K(GPIOE_PIN6) | \
+ PIN_OSPEED_400K(GPIOE_PIN7) | \
+ PIN_OSPEED_400K(GPIOE_PIN8) | \
+ PIN_OSPEED_400K(GPIOE_PIN9) | \
+ PIN_OSPEED_400K(GPIOE_PIN10) | \
+ PIN_OSPEED_400K(GPIOE_PIN11) | \
+ PIN_OSPEED_400K(GPIOE_PIN12) | \
+ PIN_OSPEED_400K(GPIOE_PIN13) | \
+ PIN_OSPEED_400K(GPIOE_PIN14) | \
+ PIN_OSPEED_400K(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_40M(GPIOH_OSC_IN) | \
+ PIN_OSPEED_40M(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_400K(GPIOH_PIN2) | \
+ PIN_OSPEED_400K(GPIOH_PIN3) | \
+ PIN_OSPEED_400K(GPIOH_PIN4) | \
+ PIN_OSPEED_400K(GPIOH_PIN5) | \
+ PIN_OSPEED_400K(GPIOH_PIN6) | \
+ PIN_OSPEED_400K(GPIOH_PIN7) | \
+ PIN_OSPEED_400K(GPIOH_PIN8) | \
+ PIN_OSPEED_400K(GPIOH_PIN9) | \
+ PIN_OSPEED_400K(GPIOH_PIN10) | \
+ PIN_OSPEED_400K(GPIOH_PIN11) | \
+ PIN_OSPEED_400K(GPIOH_PIN12) | \
+ PIN_OSPEED_400K(GPIOH_PIN13) | \
+ PIN_OSPEED_400K(GPIOH_PIN14) | \
+ PIN_OSPEED_400K(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.mk b/os/hal/boards/ST_STM32L_DISCOVERY/board.mk new file mode 100644 index 000000000..7e3fdd8e3 --- /dev/null +++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM32L_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM32L_DISCOVERY
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..b42e09289 --- /dev/null +++ b/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,799 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32L1xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l1xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32l1xx/templates</templates_path> + <output_path>..</output_path> + </configuration_settings> + <board_name>ST STM32L-Discovery</board_name> + <board_id>ST_STM32L_DISCOVERY</board_id> + <board_functions></board_functions> + <clocks + HSEFrequency="0" + HSEBypass="true" + LSEFrequency="32768" /> + <ports> + <GPIOA> + <pin0 + ID="BUTTON" + Type="PushPull" + Speed="Minimum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" ></pin1> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" ></pin4> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="JTAG_TMS" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="JTAG_TCK" + Type="PushPull" + Speed="Maximum" + Resistor="PullDown" + Level="High" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="JTAG_TDI" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Alternate" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="BOOT1" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="JTAG_TDO" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Alternate" + Alternate="0" /> + <pin4 + ID="JTAG_TRST" + Type="PushPull" + Speed="Maximum" + Resistor="PullUp" + Level="High" + Mode="Alternate" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="LED4" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="Low" + Mode="Output" + Alternate="0" /> + <pin7 + ID="LED3" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="Low" + Mode="Output" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOB> + <GPIOC> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOC> + <GPIOD> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOD> + <GPIOE> + <pin0 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOE> + <GPIOH> + <pin0 + ID="OSC_IN" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0"></pin0> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Speed="Maximum" + Resistor="Floating" + Level="High" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Speed="Minimum" + Resistor="PullUp" + Level="High" + Mode="Input" + Alternate="0" /> + </GPIOH> + </ports> +</board> diff --git a/os/hal/boards/ST_STM32VL_DISCOVERY/board.c b/os/hal/boards/ST_STM32VL_DISCOVERY/board.c new file mode 100644 index 000000000..91ae5c34a --- /dev/null +++ b/os/hal/boards/ST_STM32VL_DISCOVERY/board.c @@ -0,0 +1,50 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_STM32VL_DISCOVERY/board.h b/os/hal/boards/ST_STM32VL_DISCOVERY/board.h new file mode 100644 index 000000000..36e157d48 --- /dev/null +++ b/os/hal/boards/ST_STM32VL_DISCOVERY/board.h @@ -0,0 +1,143 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32VL-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32VL_DISCOVERY
+#define BOARD_NAME "ST STM32VL-Discovery"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_MD_VL
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+#define GPIOA_SPI1NSS 4
+
+#define GPIOB_SPI2NSS 12
+
+#define GPIOC_LED4 8
+#define GPIOC_LED3 9
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0 - Normal input (BUTTON).
+ * PA2 - Alternate output (USART2 TX).
+ * PA3 - Normal input (USART2 RX).
+ * PA4 - Push pull output (SPI1 NSS), initially high state.
+ * PA5 - Alternate output (SPI1 SCK).
+ * PA6 - Normal input (SPI1 MISO).
+ * PA7 - Alternate output (SPI1 MOSI).
+ * PA9 - Alternate output (USART1 TX).
+ * PA10 - Normal input (USART1 RX).
+ */
+#define VAL_GPIOACRL 0xB4B34B84 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x888884B8 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB12 - Push pull output (SPI2 NSS), initially high state.
+ * PB13 - Alternate output (SPI2 SCK).
+ * PB14 - Normal input (SPI2 MISO).
+ * PB15 - Alternate output (SPI2 MOSI).
+ */
+#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0xB4B38888 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC8 - Push-pull output (LED4), initially low state.
+ * PC9 - Push-pull output (LED3), initially low state.
+ */
+#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x88888833 /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFCFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0 - Normal input (XTAL).
+ * PD1 - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */
+#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
+#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM32VL_DISCOVERY/board.mk b/os/hal/boards/ST_STM32VL_DISCOVERY/board.mk new file mode 100644 index 000000000..36467943c --- /dev/null +++ b/os/hal/boards/ST_STM32VL_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM32VL_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM32VL_DISCOVERY
diff --git a/os/hal/boards/ST_STM8L_DISCOVERY/board.c b/os/hal/boards/ST_STM8L_DISCOVERY/board.c new file mode 100644 index 000000000..d530c295c --- /dev/null +++ b/os/hal/boards/ST_STM8L_DISCOVERY/board.c @@ -0,0 +1,62 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+ROMCONST PALConfig pal_default_config =
+{
+ {
+ {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
+ {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
+ {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
+ {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
+ {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
+ {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+ }
+};
+#endif
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK (SYSCLK / 16)
+#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * TIM2 initialization as system tick.
+ */
+ CLK->PCKENR1 |= CLK_PCKENR1_TIM2;
+ TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/
+ TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8);
+ TIM2->ARRL = (uint8_t)(TIM2_ARR);
+ TIM2->CNTRH = 0;
+ TIM2->CNTRL = 0;
+ TIM2->SR1 = 0;
+ TIM2->IER = TIM_IER_UIE;
+ TIM2->CR1 = TIM_CR1_CEN;
+}
diff --git a/os/hal/boards/ST_STM8L_DISCOVERY/board.h b/os/hal/boards/ST_STM8L_DISCOVERY/board.h new file mode 100644 index 000000000..907279ee7 --- /dev/null +++ b/os/hal/boards/ST_STM8L_DISCOVERY/board.h @@ -0,0 +1,167 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM8L-Discovery board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_ST_STM8L_DISCOVERY
+#define BOARD_NAME "ST STM8L-Discovery"
+
+/*
+ * Board frequencies and bypass modes.
+ *
+ * The bypass must be set to TRUE if the chip is driven by an external
+ * oscillator rather than a crystal. Frequency must be set to zero if
+ * the clock source is not used at all.
+ * The following constants are used by the HAL low level driver for
+ * correct clock initialization.
+ */
+#define HSECLK 0
+#define HSEBYPASS FALSE
+#define LSECLK 32768
+#define LSEBYPASS FALSE
+
+/*
+ * MCU model used on the board.
+ */
+#define STM8L152C6
+#define STM8L15X_MD
+
+/*
+ * Pin definitions.
+ */
+#define PA_OSC_IN 2
+#define PA_OSC_OUT 3
+#define PA_LCD_COM0 4
+#define PA_LCD_COM1 5
+#define PA_LCD_COM2 6
+#define PA_LCD_SEG0 7
+
+#define PB_LCD_SEG10 0
+#define PB_LCD_SEG11 1
+#define PB_LCD_SEG12 2
+#define PB_LCD_SEG13 3
+#define PB_LCD_SEG14 4
+#define PB_LCD_SEG15 5
+#define PB_LCD_SEG16 6
+#define PB_LCD_SEG17 7
+
+#define PC_UNUSED 0
+#define PC_BUTTON 1
+#define PC_LCD_SEG22 2
+#define PC_LCD_SEG23 3
+#define PC_IDD_CNT_EN 4
+#define PC_LED4 7
+
+#define PD_LCD_SEG7 0
+#define PD_LCD_COM3 1
+#define PD_LCD_SEG8 2
+#define PD_LCD_SEG9 3
+#define PD_LCD_SEG18 4
+#define PD_LCD_SEG19 5
+#define PD_LCD_SEG20 6
+#define PD_LCD_SEG21 7
+
+#define PE_LCD_SEG1 0
+#define PE_LCD_SEG2 1
+#define PE_LCD_SEG3 2
+#define PE_LCD_SEG4 3
+#define PE_LCD_SEG5 4
+#define PE_LCD_SEG6 5
+#define PE_IDD_WAKEUP 6
+#define PE_LED3 7
+
+#define PF0_IDD_MEASUREMENT 0
+
+/*
+ * Port A initial setup.
+ */
+#define VAL_GPIOAODR 0
+#define VAL_GPIOADDR 0 /* All inputs. */
+#define VAL_GPIOACR1 0xFF /* All pull-up/push-pull. */
+#define VAL_GPIOACR2 0
+
+/*
+ * Port B initial setup.
+ */
+#define VAL_GPIOBODR 0
+#define VAL_GPIOBDDR 0 /* All inputs. */
+#define VAL_GPIOBCR1 0xFF /* All pull-up/push-pull. */
+#define VAL_GPIOBCR2 0
+
+/*
+ * Port C initial setup.
+ */
+#define VAL_GPIOCODR 0
+#define VAL_GPIOCDDR (1 << PC_LED4)
+#define VAL_GPIOCCR1 0xFF /* All pull-up/push-pull. */
+#define VAL_GPIOCCR2 0
+
+/*
+ * Port D initial setup.
+ */
+#define VAL_GPIODODR 0
+#define VAL_GPIODDDR 0 /* All inputs. */
+#define VAL_GPIODCR1 0xFF /* All pull-up/push-pull. */
+#define VAL_GPIODCR2 0
+
+/*
+ * Port E initial setup.
+ */
+#define VAL_GPIOEODR 0
+#define VAL_GPIOEDDR (1 << PE_LED3)
+#define VAL_GPIOECR1 0xFF /* All pull-up/push-pull. */
+#define VAL_GPIOECR2 0
+
+/*
+ * Port F initial setup.
+ */
+#define VAL_GPIOFODR 0
+#define VAL_GPIOFDDR 0 /* All inputs. */
+#define VAL_GPIOFCR1 0xFF /* All pull-up/push-pull. */
+#define VAL_GPIOFCR2 0
+
+/*
+ * TIM2-update ISR segment code. This code is injected into the appropriate
+ * ISR by the HAL.
+ */
+#define _TIM2_UPDATE_ISR() { \
+ if (TIM2->SR1 & TIM_SR1_UIF) { \
+ chSysLockFromIsr(); \
+ chSysTimerHandlerI(); \
+ chSysUnlockFromIsr(); \
+ TIM2->SR1 = 0; \
+ } \
+}
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_STM8S_DISCOVERY/board.c b/os/hal/boards/ST_STM8S_DISCOVERY/board.c new file mode 100644 index 000000000..33e1fa1e9 --- /dev/null +++ b/os/hal/boards/ST_STM8S_DISCOVERY/board.c @@ -0,0 +1,78 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+ROMCONST PALConfig pal_default_config =
+{
+ {
+ {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
+ {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
+ {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
+ {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
+ {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
+ {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+ {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
+ }
+};
+#endif
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK (SYSCLK / 16)
+#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * TIM2 interrupt handler.
+ */
+CH_IRQ_HANDLER(13) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ TIM2->SR1 = 0;
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * TIM2 initialization as system tick.
+ */
+ CLK->PCKENR1 |= CLK_PCKENR1_TIM2;
+ TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/
+ TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8);
+ TIM2->ARRL = (uint8_t)(TIM2_ARR);
+ TIM2->CNTRH = 0;
+ TIM2->CNTRL = 0;
+ TIM2->SR1 = 0;
+ TIM2->IER = TIM2_IER_UIE;
+ TIM2->CR1 = TIM2_CR1_CEN;
+}
diff --git a/os/hal/boards/ST_STM8S_DISCOVERY/board.h b/os/hal/boards/ST_STM8S_DISCOVERY/board.h new file mode 100644 index 000000000..70e8682da --- /dev/null +++ b/os/hal/boards/ST_STM8S_DISCOVERY/board.h @@ -0,0 +1,121 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM8S-Discovery board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_ST_STM8S_DISCOVERY
+#define BOARD_NAME "ST STM8S-Discovery"
+
+/*
+ * Board frequencies.
+ */
+#define HSECLK 16000000
+
+/*
+ * MCU model used on the board.
+ */
+#define STM8S105
+
+/*
+ * Pin definitions.
+ */
+#define PA_OSCIN 1
+#define PA_OSCOUT 2
+
+#define PC_TS_KEY 1
+#define PC_TS_LOADREF 2
+#define PC_TS_SHIELD 3
+
+#define PD_LD10 0
+#define PD_SWIM 1
+#define PD_TX 5
+#define PD_RX 6
+
+/*
+ * Port A initial setup.
+ */
+#define VAL_GPIOAODR 0
+#define VAL_GPIOADDR 0 /* All inputs. */
+#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */
+#define VAL_GPIOACR2 0
+
+/*
+ * Port B initial setup.
+ */
+#define VAL_GPIOBODR 0
+#define VAL_GPIOBDDR 0 /* All inputs. */
+#define VAL_GPIOBCR1 0xFF /* All push-pull. */
+#define VAL_GPIOBCR2 0
+
+/*
+ * Port C initial setup.
+ */
+#define VAL_GPIOCODR 0
+#define VAL_GPIOCDDR 0 /* All inputs. */
+#define VAL_GPIOCCR1 0xFF /* All pull-up. */
+#define VAL_GPIOCCR2 0
+
+/*
+ * Port D initial setup.
+ */
+#define VAL_GPIODODR (1 << PD_LD10) | (1 << PD_TX)
+#define VAL_GPIODDDR (1 << PD_LD10) | (1 << PD_TX)
+#define VAL_GPIODCR1 0xFF /* All pull-up. */
+#define VAL_GPIODCR2 0
+
+/*
+ * Port E initial setup.
+ */
+#define VAL_GPIOEODR 0
+#define VAL_GPIOEDDR 0 /* All inputs. */
+#define VAL_GPIOECR1 0xFF /* All pull-up. */
+#define VAL_GPIOECR2 0
+
+/*
+ * Port F initial setup.
+ */
+#define VAL_GPIOFODR 0
+#define VAL_GPIOFDDR 0 /* All inputs. */
+#define VAL_GPIOFCR1 0xFF /* All pull-up. */
+#define VAL_GPIOFCR2 0
+
+/*
+ * Port G initial setup.
+ */
+#define VAL_GPIOGODR 0
+#define VAL_GPIOGDDR 0 /* All inputs. */
+#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */
+#define VAL_GPIOGCR2 0
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/readme.txt b/os/hal/boards/readme.txt new file mode 100644 index 000000000..b08a21bfb --- /dev/null +++ b/os/hal/boards/readme.txt @@ -0,0 +1,6 @@ +This directory contains the support files for various board models. If you
+want to support a new board:
+- Create a new directory under ./boards, give it the name of your board.
+- Copy inside the new directory the files from a similar board.
+- Customize board.c, board.h and board.mk in order to correctly initialize
+ your board.
diff --git a/os/hal/boards/simulator/board.c b/os/hal/boards/simulator/board.c new file mode 100644 index 000000000..6912c20ad --- /dev/null +++ b/os/hal/boards/simulator/board.c @@ -0,0 +1,35 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {0, 0, 0},
+ {0, 0, 0}
+};
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/simulator/board.h b/os/hal/boards/simulator/board.h new file mode 100644 index 000000000..ee9b14e73 --- /dev/null +++ b/os/hal/boards/simulator/board.h @@ -0,0 +1,30 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/simulator/board.mk b/os/hal/boards/simulator/board.mk new file mode 100644 index 000000000..a48747c66 --- /dev/null +++ b/os/hal/boards/simulator/board.mk @@ -0,0 +1,5 @@ +# List of all the simulator board related files.
+BOARDSRC = ${CHIBIOS}/boards/simulator/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/simulator
|