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-rw-r--r--os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c12
-rw-r--r--os/hal/boards/OLIMEX_STM32_E407_REV_D/board.h294
-rw-r--r--os/hal/boards/OLIMEX_STM32_E407_REV_D/board.mk4
3 files changed, 155 insertions, 155 deletions
diff --git a/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c b/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
index cbf380740..c516df7a1 100644
--- a/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
+++ b/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
@@ -77,10 +77,10 @@ void __early_init(void) {
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
- static bool last_status = false;
-
- if (blkIsTransferring(sdcp))
- return last_status;
+ static bool last_status = false;
+
+ if (blkIsTransferring(sdcp))
+ return last_status;
return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);
}
@@ -88,8 +88,8 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
-
- (void)sdcp;
+
+ (void)sdcp;
return false;
}
#endif /* HAL_USE_SDC */
diff --git a/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.h b/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.h
index 40d3f8832..497ee1e4d 100644
--- a/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.h
+++ b/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.h
@@ -14,8 +14,8 @@
limitations under the License.
*/
-#ifndef _BOARD_H_
-#define _BOARD_H_
+#ifndef BOARD_H
+#define BOARD_H
/*
* Setup for Olimex STM32-E407 (rev.D) board.
@@ -393,22 +393,22 @@
PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \
PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \
PIN_ODR_HIGH(GPIOA_JTAG_TDI))
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0) | \
- PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) |\
- PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
- PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0) | \
- PIN_AFIO_AF(GPIOA_PIN4, 0) | \
- PIN_AFIO_AF(GPIOA_PIN5, 0) | \
- PIN_AFIO_AF(GPIOA_PIN6, 0) | \
- PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
- PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \
- PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \
- PIN_AFIO_AF(GPIOA_JTAG_TDI, 0))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_WKUP, 0U) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11U) |\
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11U) |\
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDINT, 0U) |\
+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_HS_BUSON, 0U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_VBUS, 0U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TMS, 0U) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TCK, 0U) | \
+ PIN_AFIO_AF(GPIOA_JTAG_TDI, 0U))
/*
* GPIOB setup:
@@ -510,22 +510,22 @@
PIN_ODR_HIGH(GPIOB_OTG_HS_VBUS) | \
PIN_ODR_HIGH(GPIOB_OTG_HS_DM) | \
PIN_ODR_HIGH(GPIOB_OTG_HS_DP))
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0) | \
- PIN_AFIO_AF(GPIOB_USB_FS_FAULT, 0) | \
- PIN_AFIO_AF(GPIOB_BOOT1, 0) | \
- PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \
- PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \
- PIN_AFIO_AF(GPIOB_PIN5, 0) | \
- PIN_AFIO_AF(GPIOB_PIN6, 0) | \
- PIN_AFIO_AF(GPIOB_PIN7, 0))
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
- PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
- PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) | \
- PIN_AFIO_AF(GPIOB_PIN11, 0) | \
- PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \
- PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0) | \
- PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \
- PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_USB_FS_BUSON, 0U) | \
+ PIN_AFIO_AF(GPIOB_USB_FS_FAULT, 0U) | \
+ PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TDO, 0U) | \
+ PIN_AFIO_AF(GPIOB_JTAG_TRST, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \
+ PIN_AFIO_AF(GPIOB_SPI2_SCK, 5U) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_VBUS, 0U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12U) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12U))
/*
* GPIOC setup:
@@ -627,22 +627,22 @@
PIN_ODR_HIGH(GPIOC_LED) | \
PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
PIN_ODR_HIGH(GPIOC_OSC32_OUT))
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
- PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \
- PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) | \
- PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) | \
- PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \
- PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \
- PIN_AFIO_AF(GPIOC_USART6_TX, 8) | \
- PIN_AFIO_AF(GPIOC_USART6_RX, 8))
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \
- PIN_AFIO_AF(GPIOC_SD_D1, 12) | \
- PIN_AFIO_AF(GPIOC_SD_D2, 12) | \
- PIN_AFIO_AF(GPIOC_SD_D3, 12) | \
- PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \
- PIN_AFIO_AF(GPIOC_LED, 0) | \
- PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
- PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11U) | \
+ PIN_AFIO_AF(GPIOC_SPI2_MISO, 5U) | \
+ PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5U) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11U) |\
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11U) |\
+ PIN_AFIO_AF(GPIOC_USART6_TX, 8U) | \
+ PIN_AFIO_AF(GPIOC_USART6_RX, 8U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_D1, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_D2, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_D3, 12U) | \
+ PIN_AFIO_AF(GPIOC_SD_CLK, 12U) | \
+ PIN_AFIO_AF(GPIOC_LED, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
/*
* GPIOD setup:
@@ -744,22 +744,22 @@
PIN_ODR_HIGH(GPIOD_PIN13) | \
PIN_ODR_HIGH(GPIOD_PIN14) | \
PIN_ODR_HIGH(GPIOD_PIN15))
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
- PIN_AFIO_AF(GPIOD_PIN1, 0) | \
- PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \
- PIN_AFIO_AF(GPIOD_PIN3, 0) | \
- PIN_AFIO_AF(GPIOD_PIN4, 0) | \
- PIN_AFIO_AF(GPIOD_PIN5, 0) | \
- PIN_AFIO_AF(GPIOD_PIN6, 0) | \
- PIN_AFIO_AF(GPIOD_PIN7, 0))
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
- PIN_AFIO_AF(GPIOD_PIN9, 0) | \
- PIN_AFIO_AF(GPIOD_PIN10, 0) | \
- PIN_AFIO_AF(GPIOD_PIN11, 0) | \
- PIN_AFIO_AF(GPIOD_PIN12, 0) | \
- PIN_AFIO_AF(GPIOD_PIN13, 0) | \
- PIN_AFIO_AF(GPIOD_PIN14, 0) | \
- PIN_AFIO_AF(GPIOD_PIN15, 0))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOD_SD_CMD, 12U) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
/*
* GPIOE setup:
@@ -861,22 +861,22 @@
PIN_ODR_HIGH(GPIOE_PIN13) | \
PIN_ODR_HIGH(GPIOE_PIN14) | \
PIN_ODR_HIGH(GPIOE_PIN15))
-#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
- PIN_AFIO_AF(GPIOE_PIN1, 0) | \
- PIN_AFIO_AF(GPIOE_PIN2, 0) | \
- PIN_AFIO_AF(GPIOE_PIN3, 0) | \
- PIN_AFIO_AF(GPIOE_PIN4, 0) | \
- PIN_AFIO_AF(GPIOE_PIN5, 0) | \
- PIN_AFIO_AF(GPIOE_PIN6, 0) | \
- PIN_AFIO_AF(GPIOE_PIN7, 0))
-#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
- PIN_AFIO_AF(GPIOE_PIN9, 0) | \
- PIN_AFIO_AF(GPIOE_PIN10, 0) | \
- PIN_AFIO_AF(GPIOE_PIN11, 0) | \
- PIN_AFIO_AF(GPIOE_PIN12, 0) | \
- PIN_AFIO_AF(GPIOE_PIN13, 0) | \
- PIN_AFIO_AF(GPIOE_PIN14, 0) | \
- PIN_AFIO_AF(GPIOE_PIN15, 0))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
/*
* GPIOF setup:
@@ -978,22 +978,22 @@
PIN_ODR_HIGH(GPIOF_PIN13) | \
PIN_ODR_HIGH(GPIOF_PIN14) | \
PIN_ODR_HIGH(GPIOF_PIN15))
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
- PIN_AFIO_AF(GPIOF_PIN1, 0) | \
- PIN_AFIO_AF(GPIOF_PIN2, 0) | \
- PIN_AFIO_AF(GPIOF_PIN3, 0) | \
- PIN_AFIO_AF(GPIOF_PIN4, 0) | \
- PIN_AFIO_AF(GPIOF_PIN5, 0) | \
- PIN_AFIO_AF(GPIOF_PIN6, 0) | \
- PIN_AFIO_AF(GPIOF_PIN7, 0))
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
- PIN_AFIO_AF(GPIOF_PIN9, 0) | \
- PIN_AFIO_AF(GPIOF_PIN10, 0) | \
- PIN_AFIO_AF(GPIOF_USB_HS_FAULT, 0) | \
- PIN_AFIO_AF(GPIOF_PIN12, 0) | \
- PIN_AFIO_AF(GPIOF_PIN13, 0) | \
- PIN_AFIO_AF(GPIOF_PIN14, 0) | \
- PIN_AFIO_AF(GPIOF_PIN15, 0))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_USB_HS_FAULT, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
/*
* GPIOG setup:
@@ -1095,22 +1095,22 @@
PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD0) | \
PIN_ODR_HIGH(GPIOG_ETH_RMII_TXD1) | \
PIN_ODR_HIGH(GPIOG_PIN15))
-#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
- PIN_AFIO_AF(GPIOG_PIN1, 0) | \
- PIN_AFIO_AF(GPIOG_PIN2, 0) | \
- PIN_AFIO_AF(GPIOG_PIN3, 0) | \
- PIN_AFIO_AF(GPIOG_PIN4, 0) | \
- PIN_AFIO_AF(GPIOG_PIN5, 0) | \
- PIN_AFIO_AF(GPIOG_PIN6, 0) | \
- PIN_AFIO_AF(GPIOG_PIN7, 0))
-#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
- PIN_AFIO_AF(GPIOG_PIN9, 0) | \
- PIN_AFIO_AF(GPIOG_SPI2_CS, 0) | \
- PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11) | \
- PIN_AFIO_AF(GPIOG_PIN12, 0) | \
- PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \
- PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11) | \
- PIN_AFIO_AF(GPIOG_PIN15, 0))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOG_SPI2_CS, 0U) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXEN, 11U) |\
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11U) |\
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11U) |\
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
/*
* GPIOH setup:
@@ -1212,22 +1212,22 @@
PIN_ODR_HIGH(GPIOH_PIN13) | \
PIN_ODR_HIGH(GPIOH_PIN14) | \
PIN_ODR_HIGH(GPIOH_PIN15))
-#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
- PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
- PIN_AFIO_AF(GPIOH_PIN2, 0) | \
- PIN_AFIO_AF(GPIOH_PIN3, 0) | \
- PIN_AFIO_AF(GPIOH_PIN4, 0) | \
- PIN_AFIO_AF(GPIOH_PIN5, 0) | \
- PIN_AFIO_AF(GPIOH_PIN6, 0) | \
- PIN_AFIO_AF(GPIOH_PIN7, 0))
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
- PIN_AFIO_AF(GPIOH_PIN9, 0) | \
- PIN_AFIO_AF(GPIOH_PIN10, 0) | \
- PIN_AFIO_AF(GPIOH_PIN11, 0) | \
- PIN_AFIO_AF(GPIOH_PIN12, 0) | \
- PIN_AFIO_AF(GPIOH_PIN13, 0) | \
- PIN_AFIO_AF(GPIOH_PIN14, 0) | \
- PIN_AFIO_AF(GPIOH_PIN15, 0))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
/*
* GPIOI setup:
@@ -1329,22 +1329,22 @@
PIN_ODR_HIGH(GPIOI_PIN13) | \
PIN_ODR_HIGH(GPIOI_PIN14) | \
PIN_ODR_HIGH(GPIOI_PIN15))
-#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
- PIN_AFIO_AF(GPIOI_PIN1, 0) | \
- PIN_AFIO_AF(GPIOI_PIN2, 0) | \
- PIN_AFIO_AF(GPIOI_PIN3, 0) | \
- PIN_AFIO_AF(GPIOI_PIN4, 0) | \
- PIN_AFIO_AF(GPIOI_PIN5, 0) | \
- PIN_AFIO_AF(GPIOI_PIN6, 0) | \
- PIN_AFIO_AF(GPIOI_PIN7, 0))
-#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
- PIN_AFIO_AF(GPIOI_PIN9, 0) | \
- PIN_AFIO_AF(GPIOI_PIN10, 0) | \
- PIN_AFIO_AF(GPIOI_PIN11, 0) | \
- PIN_AFIO_AF(GPIOI_PIN12, 0) | \
- PIN_AFIO_AF(GPIOI_PIN13, 0) | \
- PIN_AFIO_AF(GPIOI_PIN14, 0) | \
- PIN_AFIO_AF(GPIOI_PIN15, 0))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0U))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0U))
#if !defined(_FROM_ASM_)
@@ -1357,4 +1357,4 @@ extern "C" {
#endif
#endif /* _FROM_ASM_ */
-#endif /* _BOARD_H_ */
+#endif /* BOARD_H */
diff --git a/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.mk b/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.mk
index b4d0fbf98..01a22c3bf 100644
--- a/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.mk
+++ b/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.mk
@@ -1,5 +1,5 @@
# List of all the board related files.
-BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
+BOARDSRC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
# Required include directories
-BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_E407_REV_D
+BOARDINC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_E407_REV_D
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 21:24:59 +0000