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-rwxr-xr-xos/common/startup/ARM/compilers/GCC/ld/SAMA5D2bvddr.ld46
-rwxr-xr-xos/common/startup/ARM/compilers/GCC/ld/SAMA5D2ddr.ld39
-rw-r--r--os/common/startup/ARM/devices/SAMA5D2/mmu.c27
-rw-r--r--os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S42
-rw-r--r--os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld37
-rw-r--r--os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c25
-rw-r--r--os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h2
-rw-r--r--os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h2
8 files changed, 157 insertions, 63 deletions
diff --git a/os/common/startup/ARM/compilers/GCC/ld/SAMA5D2bvddr.ld b/os/common/startup/ARM/compilers/GCC/ld/SAMA5D2bvddr.ld
deleted file mode 100755
index efa2f63d9..000000000
--- a/os/common/startup/ARM/compilers/GCC/ld/SAMA5D2bvddr.ld
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/*
- * SAMA5D2 memory setup in non trusted mode.
- */
-MEMORY
-{
- flash : org = 0x21000000, len = 16M
- ram0 : org = 0x22000000, len = 96M
- ram1 : org = 0x00000000, len = 0
- ram2 : org = 0x00000000, len = 0
- ram3 : org = 0x00000000, len = 0
- ram4 : org = 0x00000000, len = 0
- ram5 : org = 0x00000000, len = 0
- ram6 : org = 0x00000000, len = 0
- ram7 : org = 0x00000000, len = 0
-}
-
-/* RAM region to be used for stacks. This stack accommodates the processing
- of all exceptions and interrupts*/
-REGION_ALIAS("STACKS_RAM", ram0);
-
-/* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
-
-/* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
-
-INCLUDE rules.ld
-
-ENTRY(Boot_Handler);
-
diff --git a/os/common/startup/ARM/compilers/GCC/ld/SAMA5D2ddr.ld b/os/common/startup/ARM/compilers/GCC/ld/SAMA5D2ddr.ld
index e2bcb004a..087234cbf 100755
--- a/os/common/startup/ARM/compilers/GCC/ld/SAMA5D2ddr.ld
+++ b/os/common/startup/ARM/compilers/GCC/ld/SAMA5D2ddr.ld
@@ -19,10 +19,10 @@
*/
MEMORY
{
- flash : org = 0x20000000, len = 16M
- ram0 : org = 0x21000000, len = 96M
- ram1 : org = 0x00000000, len = 0
- ram2 : org = 0x00000000, len = 0
+ flash : org = 0x21000000, len = 16M
+ ram0 : org = 0x22000000, len = 78M
+ ram1 : org = 0x26E00000, len = 1M
+ ram2 : org = 0x26F00000, len = 1M
ram3 : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0
@@ -40,6 +40,37 @@ REGION_ALIAS("DATA_RAM", ram0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
+/* RAM region to be used for lcd frame buffer. */
+REGION_ALIAS("FB_RAM", ram1);
+
+/* RAM region to be used for no cache area. */
+REGION_ALIAS("NO_CACHE", ram2);
+
+SECTIONS
+{
+ /* Special section for frame buffer area.*/
+ .fbram (NOLOAD) : ALIGN(4)
+ {
+ __fbram_base__ = .;
+ *(.fbram)
+ *(.fbram.*)
+ *(.bss.__fbram_*)
+ . = ALIGN(4);
+ __fbram_end__ = .;
+ } > FB_RAM
+
+ /* Special section for no cache area.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NO_CACHE
+}
+
INCLUDE rules.ld
ENTRY(Boot_Handler);
diff --git a/os/common/startup/ARM/devices/SAMA5D2/mmu.c b/os/common/startup/ARM/devices/SAMA5D2/mmu.c
index a4f3b0ea0..449019526 100644
--- a/os/common/startup/ARM/devices/SAMA5D2/mmu.c
+++ b/os/common/startup/ARM/devices/SAMA5D2/mmu.c
@@ -48,9 +48,17 @@
#define SAMA_L2CC_ENABLE 0
#endif
+#if (SAMA_L2CC_ASSUME_ENABLED && SAMA_L2CC_ENABLE)
+#error "These macros are mutually exclusive"
+#endif
+
/*===========================================================================*/
/* Module local definitions. */
/*===========================================================================*/
+/*
+ * @brief No cacheable memory start address.
+ */
+#define NO_CACHE_MEMORY_START_ADDR ((uint8_t *) 0x26F00000)
/*===========================================================================*/
/* Module exported variables. */
@@ -77,7 +85,7 @@
* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
* | section |NS|0|nG|S|AP[2]|TEX[2:0]|AP[1:0]| |domain|XN|C|B|1|PXN|
* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
- * | |0 |0|0 |1|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable
+ * | |X |0|0 |0|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable, write back, no write allocate
* | |0 |0|0 |1|0 |100 |11 |0|0000 |0 |0|0|1|0 | == normal, no-cacheable
* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|1|1|0 | == device
* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|0|1|0 | == strongly-ordered
@@ -121,8 +129,8 @@ void __core_init(void) {
Invalidate a disabled L1 D Cache.*/
pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk)) {
- L1C_CleanInvalidateCache(DCISW_CLEAN);
L1C_DisableCaches();
+ L1C_CleanInvalidateCache(DCISW_CLEAN);
}
/* Disable the MMU and invalidate TLB.*/
@@ -164,7 +172,7 @@ void __core_init(void) {
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* UDPHS RAM region
*
@@ -264,7 +272,7 @@ void __core_init(void) {
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* DDR AESB regions
*
@@ -275,7 +283,7 @@ void __core_init(void) {
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* EBI 1, 2 and 3 regions
*
@@ -360,6 +368,9 @@ void __core_init(void) {
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
+ /* Make a NO CACHE AREA */
+ MMU_MemorySection((mmuTable + ((uint32_t)NO_CACHE_MEMORY_START_ADDR >> 20)), NORMAL, NON_CACHEABLE, NON_CACHEABLE);
+
/* Invalidate TLB and L1 I cache
Enable caches and MMU.*/
MMU_InvalidateTLB();
@@ -395,11 +406,17 @@ void __core_init(void) {
/* Invalidate and enable L2 cache.*/
L2C_InvAllByWay();
+ L2C_310->AUX_CNT = L2CC_ACR_DPEN | L2CC_ACR_IPEN;
+
+ /* Prefetch control register. Double linefeed, instr and data enabled.*/
+ *((uint32_t *)((char *)L2C_310+0x0F60)) = 0x75800001;
L2C_Enable();
__DSB();
__ISB();
}
#endif
+
+
#endif
}
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S
index 4810ea0f6..016e23c58 100644
--- a/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S
@@ -22,6 +22,20 @@
* @{
*/
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
#if !defined(__DOXYGEN__)
.set MODE_USR, 0x10
@@ -117,10 +131,38 @@ bssloop:
*/
bl __core_init
bl __late_init
+#if 0 /* Constructors initialized after halInit() */
+#if CRT0_CALL_CONSTRUCTORS == TRUE
+ /* Constructors invocation.*/
+ ldr r4, =__init_array_start
+ ldr r5, =__init_array_end
+initloop:
+ cmp r4, r5
+ bge endinitloop
+ ldr r1, [r4], #4
+ blx r1
+ b initloop
+endinitloop:
+#endif /* CRT0_CALL_CONSTRUCTORS */
+#endif /* if 0 */
/*
* Main program invocation.
*/
bl main
+
+#if CRT0_CALL_DESTRUCTORS == TRUE
+ /* Destructors invocation.*/
+ ldr r4, =__fini_array_start
+ ldr r5, =__fini_array_end
+finiloop:
+ cmp r4, r5
+ bge endfiniloop
+ ldr r1, [r4], #4
+ blx r1
+ b finiloop
+endfiniloop:
+#endif
+
b __default_exit
#endif /* !defined(__DOXYGEN__) */
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld
index 225f64d74..cb016edc0 100644
--- a/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld
@@ -20,9 +20,9 @@
MEMORY
{
flash : org = 0x27000000, len = 1M
- ram0 : org = 0x27100000, len = 15M
- ram1 : org = 0x00000000, len = 0
- ram2 : org = 0x00000000, len = 0
+ ram0 : org = 0x27100000, len = 13M
+ ram1 : org = 0x27E00000, len = 1M
+ ram2 : org = 0x27F00000, len = 1M
ram3 : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0
@@ -40,6 +40,37 @@ REGION_ALIAS("DATA_RAM", ram0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
+/* RAM region to be used for lcd frame buffer. */
+REGION_ALIAS("FB_RAM", ram1);
+
+/* RAM region to be used for no cache area. */
+REGION_ALIAS("NO_CACHE", ram2);
+
+SECTIONS
+{
+ /* Special section for frame buffer area.*/
+ .fbram (NOLOAD) : ALIGN(4)
+ {
+ __fbram_base__ = .;
+ *(.fbram)
+ *(.fbram.*)
+ *(.bss.__fbram_*)
+ . = ALIGN(4);
+ __fbram_end__ = .;
+ } > FB_RAM
+
+ /* Special section for no cache area.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NO_CACHE
+}
+
INCLUDE rules.ld
ENTRY(Boot_Handler);
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c
index ab063dcfc..b4af836c0 100644
--- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c
@@ -48,9 +48,17 @@
#define SAMA_L2CC_ENABLE 0
#endif
+#if (SAMA_L2CC_ASSUME_ENABLED && SAMA_L2CC_ENABLE)
+#error "These macros are mutually exclusive"
+#endif
+
/*===========================================================================*/
/* Module local definitions. */
/*===========================================================================*/
+/*
+ * @brief No cacheable memory start address.
+ */
+#define NO_CACHE_MEMORY_START_ADDR ((uint8_t *) 0x27F00000)
/*===========================================================================*/
/* Module exported variables. */
@@ -77,7 +85,7 @@
* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
* | section |NS|0|nG|S|AP[2]|TEX[2:0]|AP[1:0]| |domain|XN|C|B|1|PXN|
* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
- * | |0 |0|0 |1|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable
+ * | |0 |0|0 |0|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable, write back, no write allocate
* | |0 |0|0 |1|0 |100 |11 |0|0000 |0 |0|0|1|0 | == normal, no-cacheable
* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|1|1|0 | == device
* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|0|1|0 | == strongly-ordered
@@ -164,7 +172,7 @@ void __core_init(void) {
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* UDPHS RAM region
*
@@ -264,7 +272,7 @@ void __core_init(void) {
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* DDR AESB regions
*
@@ -275,7 +283,7 @@ void __core_init(void) {
TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* EBI 1, 2 and 3 regions
*
@@ -360,6 +368,9 @@ void __core_init(void) {
TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
+ /* Make a NO CACHE AREA */
+ MMU_MemorySection((mmuTable + ((uint32_t)NO_CACHE_MEMORY_START_ADDR >> 20)), NORMAL, NON_CACHEABLE, NON_CACHEABLE);
+
/* Invalidate TLB and L1 I cache
Enable caches and MMU.*/
MMU_InvalidateTLB();
@@ -395,11 +406,17 @@ void __core_init(void) {
/* Invalidate and enable L2 cache.*/
L2C_InvAllByWay();
+ L2C_310->AUX_CNT = L2CC_ACR_DPEN | L2CC_ACR_IPEN;
+
+ /* Prefetch control register. Double linefeed, instr and data enabled.*/
+ *((uint32_t *)((char *)L2C_310+0x0F60)) = 0x75800001;
L2C_Enable();
__DSB();
__ISB();
}
#endif
+
+
#endif
}
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h
index 95ef15854..4392fe222 100644
--- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h
@@ -31,7 +31,6 @@
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
-
#define DCISW_INVALIDATE 0
#define DCISW_CLEAN 1
#define DCISW_CLEAN_AND_INV 2
@@ -44,6 +43,7 @@
/* Derived constants and error checks. */
/*===========================================================================*/
+
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h
index 6aad3e035..1d711bf0b 100644
--- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h
@@ -64,8 +64,10 @@
/**@} */
+#ifndef GBC_DISABLE_AES_REFERENCE
/* TODO: to delete */
#define Aes wc_Aes
+#endif
/**
* @brief SAMA5D2 Family
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-22 06:31:30 +0000