194 files changed, 36832 insertions, 32970 deletions

diff --git a/os/common/ext/CMSIS/include/cmsis_armcc.h b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_armcc.h
index f2bb66a09..1d6a5fbd5 100644
--- a/os/common/ext/CMSIS/include/cmsis_armcc.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_armcc.h
@@ -1,734 +1,814 @@
-/**************************************************************************//**

- * @file     cmsis_armcc.h

- * @brief    CMSIS Cortex-M Core Function/Instruction Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#ifndef __CMSIS_ARMCC_H

-#define __CMSIS_ARMCC_H

-

-

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)

-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

-#endif

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

- */

-

-/* intrinsic void __enable_irq();     */

-/* intrinsic void __disable_irq();    */

-

-/**

-  \brief   Get Control Register

-  \details Returns the content of the Control Register.

-  \return               Control Register value

- */

-__STATIC_INLINE uint32_t __get_CONTROL(void)

-{

-  register uint32_t __regControl         __ASM("control");

-  return(__regControl);

-}

-

-

-/**

-  \brief   Set Control Register

-  \details Writes the given value to the Control Register.

-  \param [in]    control  Control Register value to set

- */

-__STATIC_INLINE void __set_CONTROL(uint32_t control)

-{

-  register uint32_t __regControl         __ASM("control");

-  __regControl = control;

-}

-

-

-/**

-  \brief   Get IPSR Register

-  \details Returns the content of the IPSR Register.

-  \return               IPSR Register value

- */

-__STATIC_INLINE uint32_t __get_IPSR(void)

-{

-  register uint32_t __regIPSR          __ASM("ipsr");

-  return(__regIPSR);

-}

-

-

-/**

-  \brief   Get APSR Register

-  \details Returns the content of the APSR Register.

-  \return               APSR Register value

- */

-__STATIC_INLINE uint32_t __get_APSR(void)

-{

-  register uint32_t __regAPSR          __ASM("apsr");

-  return(__regAPSR);

-}

-

-

-/**

-  \brief   Get xPSR Register

-  \details Returns the content of the xPSR Register.

-  \return               xPSR Register value

- */

-__STATIC_INLINE uint32_t __get_xPSR(void)

-{

-  register uint32_t __regXPSR          __ASM("xpsr");

-  return(__regXPSR);

-}

-

-

-/**

-  \brief   Get Process Stack Pointer

-  \details Returns the current value of the Process Stack Pointer (PSP).

-  \return               PSP Register value

- */

-__STATIC_INLINE uint32_t __get_PSP(void)

-{

-  register uint32_t __regProcessStackPointer  __ASM("psp");

-  return(__regProcessStackPointer);

-}

-

-

-/**

-  \brief   Set Process Stack Pointer

-  \details Assigns the given value to the Process Stack Pointer (PSP).

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  register uint32_t __regProcessStackPointer  __ASM("psp");

-  __regProcessStackPointer = topOfProcStack;

-}

-

-

-/**

-  \brief   Get Main Stack Pointer

-  \details Returns the current value of the Main Stack Pointer (MSP).

-  \return               MSP Register value

- */

-__STATIC_INLINE uint32_t __get_MSP(void)

-{

-  register uint32_t __regMainStackPointer     __ASM("msp");

-  return(__regMainStackPointer);

-}

-

-

-/**

-  \brief   Set Main Stack Pointer

-  \details Assigns the given value to the Main Stack Pointer (MSP).

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  register uint32_t __regMainStackPointer     __ASM("msp");

-  __regMainStackPointer = topOfMainStack;

-}

-

-

-/**

-  \brief   Get Priority Mask

-  \details Returns the current state of the priority mask bit from the Priority Mask Register.

-  \return               Priority Mask value

- */

-__STATIC_INLINE uint32_t __get_PRIMASK(void)

-{

-  register uint32_t __regPriMask         __ASM("primask");

-  return(__regPriMask);

-}

-

-

-/**

-  \brief   Set Priority Mask

-  \details Assigns the given value to the Priority Mask Register.

-  \param [in]    priMask  Priority Mask

- */

-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

-{

-  register uint32_t __regPriMask         __ASM("primask");

-  __regPriMask = (priMask);

-}

-

-

-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

-

-/**

-  \brief   Enable FIQ

-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-#define __enable_fault_irq                __enable_fiq

-

-

-/**

-  \brief   Disable FIQ

-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-#define __disable_fault_irq               __disable_fiq

-

-

-/**

-  \brief   Get Base Priority

-  \details Returns the current value of the Base Priority register.

-  \return               Base Priority register value

- */

-__STATIC_INLINE uint32_t  __get_BASEPRI(void)

-{

-  register uint32_t __regBasePri         __ASM("basepri");

-  return(__regBasePri);

-}

-

-

-/**

-  \brief   Set Base Priority

-  \details Assigns the given value to the Base Priority register.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)

-{

-  register uint32_t __regBasePri         __ASM("basepri");

-  __regBasePri = (basePri & 0xFFU);

-}

-

-

-/**

-  \brief   Set Base Priority with condition

-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

-           or the new value increases the BASEPRI priority level.

-  \param [in]    basePri  Base Priority value to set

- */

-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)

-{

-  register uint32_t __regBasePriMax      __ASM("basepri_max");

-  __regBasePriMax = (basePri & 0xFFU);

-}

-

-

-/**

-  \brief   Get Fault Mask

-  \details Returns the current value of the Fault Mask register.

-  \return               Fault Mask register value

- */

-__STATIC_INLINE uint32_t __get_FAULTMASK(void)

-{

-  register uint32_t __regFaultMask       __ASM("faultmask");

-  return(__regFaultMask);

-}

-

-

-/**

-  \brief   Set Fault Mask

-  \details Assigns the given value to the Fault Mask register.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  register uint32_t __regFaultMask       __ASM("faultmask");

-  __regFaultMask = (faultMask & (uint32_t)1);

-}

-

-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */

-

-

-#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)

-

-/**

-  \brief   Get FPSCR

-  \details Returns the current value of the Floating Point Status/Control register.

-  \return               Floating Point Status/Control register value

- */

-__STATIC_INLINE uint32_t __get_FPSCR(void)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  register uint32_t __regfpscr         __ASM("fpscr");

-  return(__regfpscr);

-#else

-   return(0U);

-#endif

-}

-

-

-/**

-  \brief   Set FPSCR

-  \details Assigns the given value to the Floating Point Status/Control register.

-  \param [in]    fpscr  Floating Point Status/Control value to set

- */

-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  register uint32_t __regfpscr         __ASM("fpscr");

-  __regfpscr = (fpscr);

-#endif

-}

-

-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */

-

-

-

-/*@} end of CMSIS_Core_RegAccFunctions */

-

-

-/* ##########################  Core Instruction Access  ######################### */

-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

-  Access to dedicated instructions

-  @{

-*/

-

-/**

-  \brief   No Operation

-  \details No Operation does nothing. This instruction can be used for code alignment purposes.

- */

-#define __NOP                             __nop

-

-

-/**

-  \brief   Wait For Interrupt

-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

- */

-#define __WFI                             __wfi

-

-

-/**

-  \brief   Wait For Event

-  \details Wait For Event is a hint instruction that permits the processor to enter

-           a low-power state until one of a number of events occurs.

- */

-#define __WFE                             __wfe

-

-

-/**

-  \brief   Send Event

-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.

- */

-#define __SEV                             __sev

-

-

-/**

-  \brief   Instruction Synchronization Barrier

-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,

-           so that all instructions following the ISB are fetched from cache or memory,

-           after the instruction has been completed.

- */

-#define __ISB() do {\

-                   __schedule_barrier();\

-                   __isb(0xF);\

-                   __schedule_barrier();\

-                } while (0U)

-

-/**

-  \brief   Data Synchronization Barrier

-  \details Acts as a special kind of Data Memory Barrier.

-           It completes when all explicit memory accesses before this instruction complete.

- */

-#define __DSB() do {\

-                   __schedule_barrier();\

-                   __dsb(0xF);\

-                   __schedule_barrier();\

-                } while (0U)

-

-/**

-  \brief   Data Memory Barrier

-  \details Ensures the apparent order of the explicit memory operations before

-           and after the instruction, without ensuring their completion.

- */

-#define __DMB() do {\

-                   __schedule_barrier();\

-                   __dmb(0xF);\

-                   __schedule_barrier();\

-                } while (0U)

-

-/**

-  \brief   Reverse byte order (32 bit)

-  \details Reverses the byte order in integer value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __REV                             __rev

-

-

-/**

-  \brief   Reverse byte order (16 bit)

-  \details Reverses the byte order in two unsigned short values.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)

-{

-  rev16 r0, r0

-  bx lr

-}

-#endif

-

-/**

-  \brief   Reverse byte order in signed short value

-  \details Reverses the byte order in a signed short value with sign extension to integer.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)

-{

-  revsh r0, r0

-  bx lr

-}

-#endif

-

-

-/**

-  \brief   Rotate Right in unsigned value (32 bit)

-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

-  \param [in]    value  Value to rotate

-  \param [in]    value  Number of Bits to rotate

-  \return               Rotated value

- */

-#define __ROR                             __ror

-

-

-/**

-  \brief   Breakpoint

-  \details Causes the processor to enter Debug state.

-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.

-  \param [in]    value  is ignored by the processor.

-                 If required, a debugger can use it to store additional information about the breakpoint.

- */

-#define __BKPT(value)                       __breakpoint(value)

-

-

-/**

-  \brief   Reverse bit order of value

-  \details Reverses the bit order of the given value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

-  #define __RBIT                          __rbit

-#else

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

-{

-  uint32_t result;

-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */

-

-  result = value;                      /* r will be reversed bits of v; first get LSB of v */

-  for (value >>= 1U; value; value >>= 1U)

-  {

-    result <<= 1U;

-    result |= value & 1U;

-    s--;

-  }

-  result <<= s;                        /* shift when v's highest bits are zero */

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Count leading zeros

-  \details Counts the number of leading zeros of a data value.

-  \param [in]  value  Value to count the leading zeros

-  \return             number of leading zeros in value

- */

-#define __CLZ                             __clz

-

-

-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

-

-/**

-  \brief   LDR Exclusive (8 bit)

-  \details Executes a exclusive LDR instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))

-#else

-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")

-#endif

-

-

-/**

-  \brief   LDR Exclusive (16 bit)

-  \details Executes a exclusive LDR instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))

-#else

-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")

-#endif

-

-

-/**

-  \brief   LDR Exclusive (32 bit)

-  \details Executes a exclusive LDR instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))

-#else

-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")

-#endif

-

-

-/**

-  \brief   STR Exclusive (8 bit)

-  \details Executes a exclusive STR instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)

-#else

-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")

-#endif

-

-

-/**

-  \brief   STR Exclusive (16 bit)

-  \details Executes a exclusive STR instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)

-#else

-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")

-#endif

-

-

-/**

-  \brief   STR Exclusive (32 bit)

-  \details Executes a exclusive STR instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)

-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)

-#else

-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")

-#endif

-

-

-/**

-  \brief   Remove the exclusive lock

-  \details Removes the exclusive lock which is created by LDREX.

- */

-#define __CLREX                           __clrex

-

-

-/**

-  \brief   Signed Saturate

-  \details Saturates a signed value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (1..32)

-  \return             Saturated value

- */

-#define __SSAT                            __ssat

-

-

-/**

-  \brief   Unsigned Saturate

-  \details Saturates an unsigned value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (0..31)

-  \return             Saturated value

- */

-#define __USAT                            __usat

-

-

-/**

-  \brief   Rotate Right with Extend (32 bit)

-  \details Moves each bit of a bitstring right by one bit.

-           The carry input is shifted in at the left end of the bitstring.

-  \param [in]    value  Value to rotate

-  \return               Rotated value

- */

-#ifndef __NO_EMBEDDED_ASM

-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)

-{

-  rrx r0, r0

-  bx lr

-}

-#endif

-

-

-/**

-  \brief   LDRT Unprivileged (8 bit)

-  \details Executes a Unprivileged LDRT instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))

-

-

-/**

-  \brief   LDRT Unprivileged (16 bit)

-  \details Executes a Unprivileged LDRT instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))

-

-

-/**

-  \brief   LDRT Unprivileged (32 bit)

-  \details Executes a Unprivileged LDRT instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))

-

-

-/**

-  \brief   STRT Unprivileged (8 bit)

-  \details Executes a Unprivileged STRT instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-#define __STRBT(value, ptr)               __strt(value, ptr)

-

-

-/**

-  \brief   STRT Unprivileged (16 bit)

-  \details Executes a Unprivileged STRT instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-#define __STRHT(value, ptr)               __strt(value, ptr)

-

-

-/**

-  \brief   STRT Unprivileged (32 bit)

-  \details Executes a Unprivileged STRT instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-#define __STRT(value, ptr)                __strt(value, ptr)

-

-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */

-

-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

-

-

-/* ###################  Compiler specific Intrinsics  ########################### */

-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

-  Access to dedicated SIMD instructions

-  @{

-*/

-

-#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */

-

-#define __SADD8                           __sadd8

-#define __QADD8                           __qadd8

-#define __SHADD8                          __shadd8

-#define __UADD8                           __uadd8

-#define __UQADD8                          __uqadd8

-#define __UHADD8                          __uhadd8

-#define __SSUB8                           __ssub8

-#define __QSUB8                           __qsub8

-#define __SHSUB8                          __shsub8

-#define __USUB8                           __usub8

-#define __UQSUB8                          __uqsub8

-#define __UHSUB8                          __uhsub8

-#define __SADD16                          __sadd16

-#define __QADD16                          __qadd16

-#define __SHADD16                         __shadd16

-#define __UADD16                          __uadd16

-#define __UQADD16                         __uqadd16

-#define __UHADD16                         __uhadd16

-#define __SSUB16                          __ssub16

-#define __QSUB16                          __qsub16

-#define __SHSUB16                         __shsub16

-#define __USUB16                          __usub16

-#define __UQSUB16                         __uqsub16

-#define __UHSUB16                         __uhsub16

-#define __SASX                            __sasx

-#define __QASX                            __qasx

-#define __SHASX                           __shasx

-#define __UASX                            __uasx

-#define __UQASX                           __uqasx

-#define __UHASX                           __uhasx

-#define __SSAX                            __ssax

-#define __QSAX                            __qsax

-#define __SHSAX                           __shsax

-#define __USAX                            __usax

-#define __UQSAX                           __uqsax

-#define __UHSAX                           __uhsax

-#define __USAD8                           __usad8

-#define __USADA8                          __usada8

-#define __SSAT16                          __ssat16

-#define __USAT16                          __usat16

-#define __UXTB16                          __uxtb16

-#define __UXTAB16                         __uxtab16

-#define __SXTB16                          __sxtb16

-#define __SXTAB16                         __sxtab16

-#define __SMUAD                           __smuad

-#define __SMUADX                          __smuadx

-#define __SMLAD                           __smlad

-#define __SMLADX                          __smladx

-#define __SMLALD                          __smlald

-#define __SMLALDX                         __smlaldx

-#define __SMUSD                           __smusd

-#define __SMUSDX                          __smusdx

-#define __SMLSD                           __smlsd

-#define __SMLSDX                          __smlsdx

-#define __SMLSLD                          __smlsld

-#define __SMLSLDX                         __smlsldx

-#define __SEL                             __sel

-#define __QADD                            __qadd

-#define __QSUB                            __qsub

-

-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

-

-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

-

-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \

-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))

-

-#endif /* (__CORTEX_M >= 0x04) */

-/*@} end of group CMSIS_SIMD_intrinsics */

-

-

-#endif /* __CMSIS_ARMCC_H */

+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/os/common/ext/CMSIS/include/cmsis_armcc_V6.h b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_armclang.h
index d714e9b05..214829708 100644
--- a/os/common/ext/CMSIS/include/cmsis_armcc_V6.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_armclang.h
@@ -1,1800 +1,1802 @@
-/**************************************************************************//**

- * @file     cmsis_armcc_V6.h

- * @brief    CMSIS Cortex-M Core Function/Instruction Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#ifndef __CMSIS_ARMCC_V6_H

-#define __CMSIS_ARMCC_V6_H

-

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

- */

-

-/**

-  \brief   Enable IRQ Interrupts

-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)

-{

-  __ASM volatile ("cpsie i" : : : "memory");

-}

-

-

-/**

-  \brief   Disable IRQ Interrupts

-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)

-{

-  __ASM volatile ("cpsid i" : : : "memory");

-}

-

-

-/**

-  \brief   Get Control Register

-  \details Returns the content of the Control Register.

-  \return               Control Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get Control Register (non-secure)

-  \details Returns the content of the non-secure Control Register when in secure mode.

-  \return               non-secure Control Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Control Register

-  \details Writes the given value to the Control Register.

-  \param [in]    control  Control Register value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)

-{

-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set Control Register (non-secure)

-  \details Writes the given value to the non-secure Control Register when in secure state.

-  \param [in]    control  Control Register value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)

-{

-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");

-}

-#endif

-

-

-/**

-  \brief   Get IPSR Register

-  \details Returns the content of the IPSR Register.

-  \return               IPSR Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get IPSR Register (non-secure)

-  \details Returns the content of the non-secure IPSR Register when in secure state.

-  \return               IPSR Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Get APSR Register

-  \details Returns the content of the APSR Register.

-  \return               APSR Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get APSR Register (non-secure)

-  \details Returns the content of the non-secure APSR Register when in secure state.

-  \return               APSR Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Get xPSR Register

-  \details Returns the content of the xPSR Register.

-  \return               xPSR Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get xPSR Register (non-secure)

-  \details Returns the content of the non-secure xPSR Register when in secure state.

-  \return               xPSR Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Get Process Stack Pointer

-  \details Returns the current value of the Process Stack Pointer (PSP).

-  \return               PSP Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get Process Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.

-  \return               PSP Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Process Stack Pointer

-  \details Assigns the given value to the Process Stack Pointer (PSP).

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set Process Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");

-}

-#endif

-

-

-/**

-  \brief   Get Main Stack Pointer

-  \details Returns the current value of the Main Stack Pointer (MSP).

-  \return               MSP Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, msp" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get Main Stack Pointer (non-secure)

-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.

-  \return               MSP Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Main Stack Pointer

-  \details Assigns the given value to the Main Stack Pointer (MSP).

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set Main Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.

-  \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");

-}

-#endif

-

-

-/**

-  \brief   Get Priority Mask

-  \details Returns the current state of the priority mask bit from the Priority Mask Register.

-  \return               Priority Mask value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get Priority Mask (non-secure)

-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.

-  \return               Priority Mask value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Priority Mask

-  \details Assigns the given value to the Priority Mask Register.

-  \param [in]    priMask  Priority Mask

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set Priority Mask (non-secure)

-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.

-  \param [in]    priMask  Priority Mask

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");

-}

-#endif

-

-

-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */

-

-/**

-  \brief   Enable FIQ

-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)

-{

-  __ASM volatile ("cpsie f" : : : "memory");

-}

-

-

-/**

-  \brief   Disable FIQ

-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)

-{

-  __ASM volatile ("cpsid f" : : : "memory");

-}

-

-

-/**

-  \brief   Get Base Priority

-  \details Returns the current value of the Base Priority register.

-  \return               Base Priority register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get Base Priority (non-secure)

-  \details Returns the current value of the non-secure Base Priority register when in secure state.

-  \return               Base Priority register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Base Priority

-  \details Assigns the given value to the Base Priority register.

-  \param [in]    basePri  Base Priority value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)

-{

-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set Base Priority (non-secure)

-  \details Assigns the given value to the non-secure Base Priority register when in secure state.

-  \param [in]    basePri  Base Priority value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)

-{

-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");

-}

-#endif

-

-

-/**

-  \brief   Set Base Priority with condition

-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

-           or the new value increases the BASEPRI priority level.

-  \param [in]    basePri  Base Priority value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)

-{

-  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set Base Priority with condition (non_secure)

-  \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,

-	       or the new value increases the BASEPRI priority level.

-  \param [in]    basePri  Base Priority value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)

-{

-  __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");

-}

-#endif

-

-

-/**

-  \brief   Get Fault Mask

-  \details Returns the current value of the Fault Mask register.

-  \return               Fault Mask register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get Fault Mask (non-secure)

-  \details Returns the current value of the non-secure Fault Mask register when in secure state.

-  \return               Fault Mask register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Fault Mask

-  \details Assigns the given value to the Fault Mask register.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set Fault Mask (non-secure)

-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");

-}

-#endif

-

-

-#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */

-

-

-#if (__ARM_ARCH_8M__ == 1U)

-

-/**

-  \brief   Get Process Stack Pointer Limit

-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).

-  \return               PSPLIM Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */

-/**

-  \brief   Get Process Stack Pointer Limit (non-secure)

-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

-  \return               PSPLIM Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Process Stack Pointer Limit

-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)

-{

-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */

-/**

-  \brief   Set Process Stack Pointer (non-secure)

-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)

-{

-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));

-}

-#endif

-

-

-/**

-  \brief   Get Main Stack Pointer Limit

-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).

-  \return               MSPLIM Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );

-

-  return(result);

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */

-/**

-  \brief   Get Main Stack Pointer Limit (non-secure)

-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.

-  \return               MSPLIM Register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Set Main Stack Pointer Limit

-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)

-{

-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));

-}

-

-

-#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */

-/**

-  \brief   Set Main Stack Pointer Limit (non-secure)

-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.

-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)

-{

-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

-}

-#endif

-

-#endif /* (__ARM_ARCH_8M__ == 1U) */

-

-

-#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=4 */

-

-/**

-  \brief   Get FPSCR

-  \details eturns the current value of the Floating Point Status/Control register.

-  \return               Floating Point Status/Control register value

- */

-#define __get_FPSCR      __builtin_arm_get_fpscr

-#if 0

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  uint32_t result;

-

-  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

-  __ASM volatile ("");

-  return(result);

-#else

-   return(0);

-#endif

-}

-#endif

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Get FPSCR (non-secure)

-  \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.

-  \return               Floating Point Status/Control register value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  uint32_t result;

-

-  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );

-  __ASM volatile ("");

-  return(result);

-#else

-   return(0);

-#endif

-}

-#endif

-

-

-/**

-  \brief   Set FPSCR

-  \details Assigns the given value to the Floating Point Status/Control register.

-  \param [in]    fpscr  Floating Point Status/Control value to set

- */

-#define __set_FPSCR      __builtin_arm_set_fpscr

-#if 0

-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");

-  __ASM volatile ("");

-#endif

-}

-#endif

-

-#if  (__ARM_FEATURE_CMSE == 3U)

-/**

-  \brief   Set FPSCR (non-secure)

-  \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.

-  \param [in]    fpscr  Floating Point Status/Control value to set

- */

-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");

-  __ASM volatile ("");

-#endif

-}

-#endif

-

-#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */

-

-

-

-/*@} end of CMSIS_Core_RegAccFunctions */

-

-

-/* ##########################  Core Instruction Access  ######################### */

-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

-  Access to dedicated instructions

-  @{

-*/

-

-/* Define macros for porting to both thumb1 and thumb2.

- * For thumb1, use low register (r0-r7), specified by constraint "l"

- * Otherwise, use general registers, specified by constraint "r" */

-#if defined (__thumb__) && !defined (__thumb2__)

-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)

-#define __CMSIS_GCC_USE_REG(r) "l" (r)

-#else

-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)

-#define __CMSIS_GCC_USE_REG(r) "r" (r)

-#endif

-

-/**

-  \brief   No Operation

-  \details No Operation does nothing. This instruction can be used for code alignment purposes.

- */

-#define __NOP          __builtin_arm_nop

-

-/**

-  \brief   Wait For Interrupt

-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

- */

-#define __WFI          __builtin_arm_wfi

-

-

-/**

-  \brief   Wait For Event

-  \details Wait For Event is a hint instruction that permits the processor to enter

-           a low-power state until one of a number of events occurs.

- */

-#define __WFE          __builtin_arm_wfe

-

-

-/**

-  \brief   Send Event

-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.

- */

-#define __SEV          __builtin_arm_sev

-

-

-/**

-  \brief   Instruction Synchronization Barrier

-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,

-           so that all instructions following the ISB are fetched from cache or memory,

-           after the instruction has been completed.

- */

-#define __ISB()        __builtin_arm_isb(0xF);

-

-/**

-  \brief   Data Synchronization Barrier

-  \details Acts as a special kind of Data Memory Barrier.

-           It completes when all explicit memory accesses before this instruction complete.

- */

-#define __DSB()        __builtin_arm_dsb(0xF);

-

-

-/**

-  \brief   Data Memory Barrier

-  \details Ensures the apparent order of the explicit memory operations before

-           and after the instruction, without ensuring their completion.

- */

-#define __DMB()        __builtin_arm_dmb(0xF);

-

-

-/**

-  \brief   Reverse byte order (32 bit)

-  \details Reverses the byte order in integer value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __REV          __builtin_bswap32

-

-

-/**

-  \brief   Reverse byte order (16 bit)

-  \details Reverses the byte order in two unsigned short values.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-#define __REV16          __builtin_bswap16                           /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */

-#if 0

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-#endif

-

-

-/**

-  \brief   Reverse byte order in signed short value

-  \details Reverses the byte order in a signed short value with sign extension to integer.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-                                                          /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */

-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)

-{

-  int32_t result;

-

-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-

-

-/**

-  \brief   Rotate Right in unsigned value (32 bit)

-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

-  \param [in]    op1  Value to rotate

-  \param [in]    op2  Number of Bits to rotate

-  \return               Rotated value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

-{

-  return (op1 >> op2) | (op1 << (32U - op2));

-}

-

-

-/**

-  \brief   Breakpoint

-  \details Causes the processor to enter Debug state.

-            Debug tools can use this to investigate system state when the instruction at a particular address is reached.

-    \param [in]    value  is ignored by the processor.

-                   If required, a debugger can use it to store additional information about the breakpoint.

- */

-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)

-

-

-/**

-  \brief   Reverse bit order of value

-  \details Reverses the bit order of the given value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-                                                          /* ToDo:  ARMCC_V6: check if __builtin_arm_rbit is supported */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

-{

-  uint32_t result;

-

-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */

-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

-#else

-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */

-

-  result = value;                      /* r will be reversed bits of v; first get LSB of v */

-  for (value >>= 1U; value; value >>= 1U)

-  {

-    result <<= 1U;

-    result |= value & 1U;

-    s--;

-  }

-  result <<= s;                        /* shift when v's highest bits are zero */

-#endif

-  return(result);

-}

-

-

-/**

-  \brief   Count leading zeros

-  \details Counts the number of leading zeros of a data value.

-  \param [in]  value  Value to count the leading zeros

-  \return             number of leading zeros in value

- */

-#define __CLZ             __builtin_clz

-

-

-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */

-

-/**

-  \brief   LDR Exclusive (8 bit)

-  \details Executes a exclusive LDR instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#define __LDREXB        (uint8_t)__builtin_arm_ldrex

-

-

-/**

-  \brief   LDR Exclusive (16 bit)

-  \details Executes a exclusive LDR instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#define __LDREXH        (uint16_t)__builtin_arm_ldrex

-

-

-/**

-  \brief   LDR Exclusive (32 bit)

-  \details Executes a exclusive LDR instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#define __LDREXW        (uint32_t)__builtin_arm_ldrex

-

-

-/**

-  \brief   STR Exclusive (8 bit)

-  \details Executes a exclusive STR instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define __STREXB        (uint32_t)__builtin_arm_strex

-

-

-/**

-  \brief   STR Exclusive (16 bit)

-  \details Executes a exclusive STR instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define __STREXH        (uint32_t)__builtin_arm_strex

-

-

-/**

-  \brief   STR Exclusive (32 bit)

-  \details Executes a exclusive STR instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define __STREXW        (uint32_t)__builtin_arm_strex

-

-

-/**

-  \brief   Remove the exclusive lock

-  \details Removes the exclusive lock which is created by LDREX.

- */

-#define __CLREX             __builtin_arm_clrex

-

-

-/**

-  \brief   Signed Saturate

-  \details Saturates a signed value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (1..32)

-  \return             Saturated value

- */

-/*#define __SSAT             __builtin_arm_ssat*/

-#define __SSAT(ARG1,ARG2) \

-({                          \

-  int32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-

-/**

-  \brief   Unsigned Saturate

-  \details Saturates an unsigned value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (0..31)

-  \return             Saturated value

- */

-#define __USAT             __builtin_arm_usat

-#if 0

-#define __USAT(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-#endif

-

-

-/**

-  \brief   Rotate Right with Extend (32 bit)

-  \details Moves each bit of a bitstring right by one bit.

-           The carry input is shifted in at the left end of the bitstring.

-  \param [in]    value  Value to rotate

-  \return               Rotated value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-

-

-/**

-  \brief   LDRT Unprivileged (8 bit)

-  \details Executes a Unprivileged LDRT instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );

-   return ((uint8_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDRT Unprivileged (16 bit)

-  \details Executes a Unprivileged LDRT instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );

-   return ((uint16_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDRT Unprivileged (32 bit)

-  \details Executes a Unprivileged LDRT instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );

-   return(result);

-}

-

-

-/**

-  \brief   STRT Unprivileged (8 bit)

-  \details Executes a Unprivileged STRT instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)

-{

-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   STRT Unprivileged (16 bit)

-  \details Executes a Unprivileged STRT instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)

-{

-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   STRT Unprivileged (32 bit)

-  \details Executes a Unprivileged STRT instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)

-{

-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );

-}

-

-#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */

-

-

-#if (__ARM_ARCH_8M__ == 1U)

-

-/**

-  \brief   Load-Acquire (8 bit)

-  \details Executes a LDAB instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );

-   return ((uint8_t) result);

-}

-

-

-/**

-  \brief   Load-Acquire (16 bit)

-  \details Executes a LDAH instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );

-   return ((uint16_t) result);

-}

-

-

-/**

-  \brief   Load-Acquire (32 bit)

-  \details Executes a LDA instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)

-{

-    uint32_t result;

-

-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );

-   return(result);

-}

-

-

-/**

-  \brief   Store-Release (8 bit)

-  \details Executes a STLB instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)

-{

-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   Store-Release (16 bit)

-  \details Executes a STLH instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)

-{

-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   Store-Release (32 bit)

-  \details Executes a STL instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)

-{

-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   Load-Acquire Exclusive (8 bit)

-  \details Executes a LDAB exclusive instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex

-

-

-/**

-  \brief   Load-Acquire Exclusive (16 bit)

-  \details Executes a LDAH exclusive instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex

-

-

-/**

-  \brief   Load-Acquire Exclusive (32 bit)

-  \details Executes a LDA exclusive instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex

-

-

-/**

-  \brief   Store-Release Exclusive (8 bit)

-  \details Executes a STLB exclusive instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex

-

-

-/**

-  \brief   Store-Release Exclusive (16 bit)

-  \details Executes a STLH exclusive instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex

-

-

-/**

-  \brief   Store-Release Exclusive (32 bit)

-  \details Executes a STL exclusive instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-#define     __STLEX                  (uint32_t)__builtin_arm_stlex

-

-#endif /* (__ARM_ARCH_8M__ == 1U) */

-

-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

-

-

-/* ###################  Compiler specific Intrinsics  ########################### */

-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

-  Access to dedicated SIMD instructions

-  @{

-*/

-

-#if (__ARM_FEATURE_DSP == 1U)        /* ToDo:  ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-#define __SSAT16(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-#define __USAT16(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)

-{

-  uint32_t result;

-

-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)

-{

-  uint32_t result;

-

-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)

-{

-  int32_t result;

-

-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)

-{

-  int32_t result;

-

-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-#define __PKHBT(ARG1,ARG2,ARG3) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

-  __RES; \

- })

-

-#define __PKHTB(ARG1,ARG2,ARG3) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

-  if (ARG3 == 0) \

-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

-  else \

-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

-  __RES; \

- })

-

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

-{

- int32_t result;

-

- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

- return(result);

-}

-

-#endif /* (__ARM_FEATURE_DSP == 1U) */

-/*@} end of group CMSIS_SIMD_intrinsics */

-

-

-#endif /* __CMSIS_ARMCC_V6_H */

+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.3
+ * @date     27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR      __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR      __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          __builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/cmsis_compiler.h b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_compiler.h
new file mode 100644
index 000000000..0f703ff9f
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_compiler.h
@@ -0,0 +1,353 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+
+  #include <cmsis_iar.h>
+
+  /* CMSIS compiler control architecture macros */
+  #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+    #ifndef __ARM_ARCH_6M__
+      #define __ARM_ARCH_6M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7M__)
+    #ifndef __ARM_ARCH_7M__
+      #define __ARM_ARCH_7M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7EM__)
+    #ifndef __ARM_ARCH_7EM__
+      #define __ARM_ARCH_7EM__                     1
+    #endif
+  #endif
+
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __noreturn
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __root
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        __packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         __packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    __packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+  // Workaround for missing __CLZ intrinsic in
+  // various versions of the IAR compilers.
+  // __IAR_FEATURE_CLZ__ should be defined by
+  // the compiler that supports __CLZ internally.
+  #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
+    __STATIC_INLINE uint32_t __CLZ(uint32_t data)
+    {
+      if (data == 0u) { return 32u; }
+      
+      uint32_t count = 0;
+      uint32_t mask = 0x80000000;
+      
+      while ((data & mask) == 0)
+      {
+        count += 1u;
+        mask = mask >> 1u;
+      }
+      
+      return (count);
+    }
+  #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/cmsis_gcc.h b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_gcc.h
new file mode 100644
index 000000000..1a086c559
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_gcc.h
@@ -0,0 +1,1981 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+//  __ASM volatile ("nop");
+//}
+#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+//  __ASM volatile ("wfi");
+//}
+#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+//  __ASM volatile ("wfe");
+//}
+#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+//  __ASM volatile ("sev");
+//}
+#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/* CHIBIOS FIX */
+//#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/cmsis_version.h b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_version.h
new file mode 100644
index 000000000..d458a6c85
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/core_armv8mbl.h b/os/common/ext/ARM/CMSIS/Core/Include/core_armv8mbl.h
new file mode 100644
index 000000000..13003e1cd
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_armv8mbl.h
@@ -0,0 +1,1878 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+ 
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/core_armv8mml.h b/os/common/ext/ARM/CMSIS/Core/Include/core_armv8mml.h
new file mode 100644
index 000000000..5c4d6f6ee
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_armv8mml.h
@@ -0,0 +1,2902 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/CMSIS/include/core_cm0.h b/os/common/ext/ARM/CMSIS/Core/Include/core_cm0.h
index fdee521a8..2f63b6861 100644
--- a/os/common/ext/CMSIS/include/core_cm0.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_cm0.h
@@ -1,798 +1,888 @@
-/**************************************************************************//**

- * @file     core_cm0.h

- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CM0_H_GENERIC

-#define __CORE_CM0_H_GENERIC

-

-#include <stdint.h>

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/**

-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/**

-  \ingroup Cortex_M0

-  @{

- */

-

-/*  CMSIS CM0 definitions */

-#define __CM0_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */

-#define __CM0_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */

-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \

-                                    __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */

-

-#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */

-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */

-  #define __STATIC_INLINE  static inline

-

-#else

-  #error Unknown compiler

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0U

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #if defined __ARM_PCS_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )

-  #if ( __CSMC__ & 0x400U)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#endif

-

-#include "core_cmInstr.h"                /* Core Instruction Access */

-#include "core_cmFunc.h"                 /* Core Function Access */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM0_H_DEPENDANT

-#define __CORE_CM0_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM0_REV

-    #define __CM0_REV               0x0000U

-    #warning "__CM0_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          2U

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0U

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions */

-

-/* following defines should be used for structure members */

-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */

-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */

-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

-

-/*@} end of group Cortex_M0 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

- ******************************************************************************/

-/**

-  \defgroup CMSIS_core_register Defines and Type Definitions

-  \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_CORE  Status and Control Registers

-  \brief      Core Register type definitions.

-  @{

- */

-

-/**

-  \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} APSR_Type;

-

-/* APSR Register Definitions */

-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */

-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

-

-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */

-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

-

-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */

-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

-

-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */

-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

-

-

-/**

-  \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} IPSR_Type;

-

-/* IPSR Register Definitions */

-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */

-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */

-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} xPSR_Type;

-

-/* xPSR Register Definitions */

-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */

-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

-

-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */

-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

-

-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */

-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

-

-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */

-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

-

-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */

-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

-

-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */

-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */

-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} CONTROL_Type;

-

-/* CONTROL Register Definitions */

-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */

-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

-

-/*@} end of group CMSIS_CORE */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-  \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

-        uint32_t RESERVED0[31U];

-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

-        uint32_t RSERVED1[31U];

-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

-        uint32_t RESERVED2[31U];

-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

-        uint32_t RESERVED3[31U];

-        uint32_t RESERVED4[64U];

-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */

-}  NVIC_Type;

-

-/*@} end of group CMSIS_NVIC */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCB     System Control Block (SCB)

-  \brief    Type definitions for the System Control Block Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */

-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */

-        uint32_t RESERVED0;

-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */

-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */

-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */

-        uint32_t RESERVED1;

-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */

-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-  \brief    Type definitions for the System Timer Registers.

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */

-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */

-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.

-            Therefore they are not covered by the Cortex-M0 header file.

-  @{

- */

-/*@} end of group CMSIS_CoreDebug */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_bitfield     Core register bit field macros

-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

-  @{

- */

-

-/**

-  \brief   Mask and shift a bit field value for use in a register bit range.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of the bit field.

-  \return           Masked and shifted value.

-*/

-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)

-

-/**

-  \brief     Mask and shift a register value to extract a bit filed value.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of register.

-  \return           Masked and shifted bit field value.

-*/

-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)

-

-/*@} end of group CMSIS_core_bitfield */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_base     Core Definitions

-  \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M0 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */

-

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/**

-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-  \brief    Functions that manage interrupts and exceptions via the NVIC.

-  @{

- */

-

-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

-/* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

-

-

-/**

-  \brief   Enable External Interrupt

-  \details Enables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Disable External Interrupt

-  \details Disables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Pending Interrupt

-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not pending.

-  \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Pending Interrupt

-  \details Sets the pending bit of an external interrupt.

-  \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Clear Pending Interrupt

-  \details Clears the pending bit of an external interrupt.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Set Interrupt Priority

-  \details Sets the priority of an interrupt.

-  \note    The priority cannot be set for every core interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if ((int32_t)(IRQn) < 0)

-  {

-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

-  }

-  else

-  {

-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

-  }

-}

-

-

-/**

-  \brief   Get Interrupt Priority

-  \details Reads the priority of an interrupt.

-           The interrupt number can be positive to specify an external (device specific) interrupt,

-           or negative to specify an internal (core) interrupt.

-  \param [in]   IRQn  Interrupt number.

-  \return             Interrupt Priority.

-                      Value is aligned automatically to the implemented priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if ((int32_t)(IRQn) < 0)

-  {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));

-  }

-  else

-  {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));

-  }

-}

-

-

-/**

-  \brief   System Reset

-  \details Initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                          /* Ensure all outstanding memory accesses included

-                                                                       buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);

-  __DSB();                                                          /* Ensure completion of memory access */

-

-  for(;;)                                                           /* wait until reset */

-  {

-    __NOP();

-  }

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-  \brief    Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0U)

-

-/**

-  \brief   System Tick Configuration

-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.

-           Counter is in free running mode to generate periodic interrupts.

-  \param [in]  ticks  Number of ticks between two interrupts.

-  \return          0  Function succeeded.

-  \return          1  Function failed.

-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-           must contain a vendor-specific implementation of this function.

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

-  {

-    return (1UL);                                                   /* Reload value impossible */

-  }

-

-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

-  return (0UL);                                                     /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/CMSIS/include/core_cm0plus.h b/os/common/ext/ARM/CMSIS/Core/Include/core_cm0plus.h
index 7614450d3..5c6135802 100644
--- a/os/common/ext/CMSIS/include/core_cm0plus.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_cm0plus.h
@@ -1,914 +1,1021 @@
-/**************************************************************************//**

- * @file     core_cm0plus.h

- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CM0PLUS_H_GENERIC

-#define __CORE_CM0PLUS_H_GENERIC

-

-#include <stdint.h>

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/**

-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/**

-  \ingroup Cortex-M0+

-  @{

- */

-

-/*  CMSIS CM0+ definitions */

-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                   /*!< [31:16] CMSIS HAL main version */

-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                   /*!< [15:0]  CMSIS HAL sub version */

-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \

-                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */

-

-#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */

-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */

-  #define __STATIC_INLINE  static inline

-

-#else

-  #error Unknown compiler

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0U

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #if defined __ARM_PCS_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )

-  #if ( __CSMC__ & 0x400U)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#endif

-

-#include "core_cmInstr.h"                /* Core Instruction Access */

-#include "core_cmFunc.h"                 /* Core Function Access */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0PLUS_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM0PLUS_H_DEPENDANT

-#define __CORE_CM0PLUS_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM0PLUS_REV

-    #define __CM0PLUS_REV             0x0000U

-    #warning "__CM0PLUS_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0U

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __VTOR_PRESENT

-    #define __VTOR_PRESENT            0U

-    #warning "__VTOR_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          2U

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0U

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions */

-

-/* following defines should be used for structure members */

-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */

-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */

-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

-

-/*@} end of group Cortex-M0+ */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core MPU Register

- ******************************************************************************/

-/**

-  \defgroup CMSIS_core_register Defines and Type Definitions

-  \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_CORE  Status and Control Registers

-  \brief      Core Register type definitions.

-  @{

- */

-

-/**

-  \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} APSR_Type;

-

-/* APSR Register Definitions */

-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */

-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

-

-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */

-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

-

-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */

-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

-

-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */

-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

-

-

-/**

-  \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} IPSR_Type;

-

-/* IPSR Register Definitions */

-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */

-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */

-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} xPSR_Type;

-

-/* xPSR Register Definitions */

-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */

-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

-

-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */

-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

-

-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */

-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

-

-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */

-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

-

-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */

-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

-

-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */

-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */

-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} CONTROL_Type;

-

-/* CONTROL Register Definitions */

-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */

-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

-

-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */

-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

-

-/*@} end of group CMSIS_CORE */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-  \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

-        uint32_t RESERVED0[31U];

-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

-        uint32_t RSERVED1[31U];

-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

-        uint32_t RESERVED2[31U];

-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

-        uint32_t RESERVED3[31U];

-        uint32_t RESERVED4[64U];

-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */

-}  NVIC_Type;

-

-/*@} end of group CMSIS_NVIC */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCB     System Control Block (SCB)

-  \brief    Type definitions for the System Control Block Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */

-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */

-#if (__VTOR_PRESENT == 1U)

-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */

-#else

-        uint32_t RESERVED0;

-#endif

-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */

-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */

-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */

-        uint32_t RESERVED1;

-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */

-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

-

-#if (__VTOR_PRESENT == 1U)

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

-#endif

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-  \brief    Type definitions for the System Timer Registers.

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */

-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */

-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-#if (__MPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-  \brief    Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */

-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */

-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */

-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register Definitions */

-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register Definitions */

-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register Definitions */

-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register Definitions */

-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register Definitions */

-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.

-            Therefore they are not covered by the Cortex-M0+ header file.

-  @{

- */

-/*@} end of group CMSIS_CoreDebug */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_bitfield     Core register bit field macros

-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

-  @{

- */

-

-/**

-  \brief   Mask and shift a bit field value for use in a register bit range.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of the bit field.

-  \return           Masked and shifted value.

-*/

-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)

-

-/**

-  \brief     Mask and shift a register value to extract a bit filed value.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of register.

-  \return           Masked and shifted bit field value.

-*/

-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)

-

-/*@} end of group CMSIS_core_bitfield */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_base     Core Definitions

-  \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M0+ Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */

-

-#if (__MPU_PRESENT == 1U)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/**

-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-  \brief    Functions that manage interrupts and exceptions via the NVIC.

-  @{

- */

-

-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

-/* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

-

-

-/**

-  \brief   Enable External Interrupt

-  \details Enables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Disable External Interrupt

-  \details Disables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Pending Interrupt

-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not pending.

-  \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Pending Interrupt

-  \details Sets the pending bit of an external interrupt.

-  \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Clear Pending Interrupt

-  \details Clears the pending bit of an external interrupt.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Set Interrupt Priority

-  \details Sets the priority of an interrupt.

-  \note    The priority cannot be set for every core interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if ((int32_t)(IRQn) < 0)

-  {

-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

-  }

-  else

-  {

-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

-  }

-}

-

-

-/**

-  \brief   Get Interrupt Priority

-  \details Reads the priority of an interrupt.

-           The interrupt number can be positive to specify an external (device specific) interrupt,

-           or negative to specify an internal (core) interrupt.

-  \param [in]   IRQn  Interrupt number.

-  \return             Interrupt Priority.

-                      Value is aligned automatically to the implemented priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if ((int32_t)(IRQn) < 0)

-  {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));

-  }

-  else

-  {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));

-  }

-}

-

-

-/**

-  \brief   System Reset

-  \details Initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                          /* Ensure all outstanding memory accesses included

-                                                                       buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);

-  __DSB();                                                          /* Ensure completion of memory access */

-

-  for(;;)                                                           /* wait until reset */

-  {

-    __NOP();

-  }

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-  \brief    Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0U)

-

-/**

-  \brief   System Tick Configuration

-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.

-           Counter is in free running mode to generate periodic interrupts.

-  \param [in]  ticks  Number of ticks between two interrupts.

-  \return          0  Function succeeded.

-  \return          1  Function failed.

-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-           must contain a vendor-specific implementation of this function.

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

-  {

-    return (1UL);                                                   /* Reload value impossible */

-  }

-

-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

-  return (0UL);                                                     /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM0PLUS_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/core_cm23.h b/os/common/ext/ARM/CMSIS/Core/Include/core_cm23.h
new file mode 100644
index 000000000..b97fa9dd3
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_cm23.h
@@ -0,0 +1,1878 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/CMSIS/include/core_cm3.h b/os/common/ext/ARM/CMSIS/Core/Include/core_cm3.h
index 34ed84c1e..3c1f01f49 100644
--- a/os/common/ext/CMSIS/include/core_cm3.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_cm3.h
@@ -1,1763 +1,1928 @@
-/**************************************************************************//**

- * @file     core_cm3.h

- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CM3_H_GENERIC

-#define __CORE_CM3_H_GENERIC

-

-#include <stdint.h>

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/**

-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/**

-  \ingroup Cortex_M3

-  @{

- */

-

-/*  CMSIS CM3 definitions */

-#define __CM3_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */

-#define __CM3_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */

-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \

-                                    __CM3_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */

-

-#define __CORTEX_M                (0x03U)                                      /*!< Cortex-M Core */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */

-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */

-  #define __STATIC_INLINE  static inline

-

-#else

-  #error Unknown compiler

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0U

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #if defined __ARM_PCS_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )

-  #if ( __CSMC__ & 0x400U)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#endif

-

-#include "core_cmInstr.h"                /* Core Instruction Access */

-#include "core_cmFunc.h"                 /* Core Function Access */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM3_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM3_H_DEPENDANT

-#define __CORE_CM3_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM3_REV

-    #define __CM3_REV               0x0200U

-    #warning "__CM3_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0U

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          4U

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0U

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions */

-

-/* following defines should be used for structure members */

-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */

-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */

-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

-

-/*@} end of group Cortex_M3 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

- ******************************************************************************/

-/**

-  \defgroup CMSIS_core_register Defines and Type Definitions

-  \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_CORE  Status and Control Registers

-  \brief      Core Register type definitions.

-  @{

- */

-

-/**

-  \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} APSR_Type;

-

-/* APSR Register Definitions */

-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */

-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

-

-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */

-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

-

-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */

-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

-

-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */

-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

-

-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */

-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

-

-

-/**

-  \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} IPSR_Type;

-

-/* IPSR Register Definitions */

-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */

-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} xPSR_Type;

-

-/* xPSR Register Definitions */

-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */

-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

-

-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */

-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

-

-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */

-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

-

-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */

-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

-

-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */

-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

-

-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */

-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

-

-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */

-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

-

-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */

-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */

-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} CONTROL_Type;

-

-/* CONTROL Register Definitions */

-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */

-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

-

-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */

-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

-

-/*@} end of group CMSIS_CORE */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-  \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

-        uint32_t RESERVED0[24U];

-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

-        uint32_t RSERVED1[24U];

-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

-        uint32_t RESERVED2[24U];

-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

-        uint32_t RESERVED3[24U];

-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */

-        uint32_t RESERVED4[56U];

-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-        uint32_t RESERVED5[644U];

-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCB     System Control Block (SCB)

-  \brief    Type definitions for the System Control Block Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */

-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */

-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */

-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */

-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */

-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */

-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */

-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */

-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */

-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */

-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */

-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */

-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */

-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */

-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */

-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */

-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */

-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */

-        uint32_t RESERVED0[5U];

-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#if (__CM3_REV < 0x0201U)                   /* core r2p1 */

-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */

-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */

-

-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

-#else

-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-#endif

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Register Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Register Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-  \brief    Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-        uint32_t RESERVED0[1U];

-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */

-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))

-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */

-#else

-        uint32_t RESERVED1[1U];

-#endif

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

-

-/* Auxiliary Control Register Definitions */

-

-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */

-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

-

-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */

-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

-

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-  \brief    Type definitions for the System Timer Registers.

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */

-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */

-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __OM  union

-  {

-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */

-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */

-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */

-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */

-        uint32_t RESERVED0[864U];

-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */

-        uint32_t RESERVED1[15U];

-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */

-        uint32_t RESERVED2[15U];

-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */

-        uint32_t RESERVED3[29U];

-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */

-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */

-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */

-        uint32_t RESERVED4[43U];

-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */

-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */

-        uint32_t RESERVED5[6U];

-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */

-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */

-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */

-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */

-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */

-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */

-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */

-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */

-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */

-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */

-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */

-        uint32_t RESERVED0[1U];

-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */

-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */

-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */

-        uint32_t RESERVED1[1U];

-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */

-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */

-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */

-        uint32_t RESERVED2[1U];

-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */

-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */

-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-  \brief    Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */

-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-        uint32_t RESERVED0[2U];

-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-        uint32_t RESERVED1[55U];

-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-        uint32_t RESERVED2[131U];

-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-        uint32_t RESERVED3[759U];

-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-        uint32_t RESERVED4[1U];

-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-        uint32_t RESERVED5[39U];

-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-        uint32_t RESERVED7[8U];

-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-  \brief    Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */

-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */

-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */

-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */

-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */

-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */

-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register Definitions */

-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register Definitions */

-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register Definitions */

-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register Definitions */

-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register Definitions */

-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-  \brief    Type definitions for the Core Debug Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */

-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */

-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */

-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register Definitions */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register Definitions */

-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register Definitions */

-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_bitfield     Core register bit field macros

-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

-  @{

- */

-

-/**

-  \brief   Mask and shift a bit field value for use in a register bit range.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of the bit field.

-  \return           Masked and shifted value.

-*/

-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)

-

-/**

-  \brief     Mask and shift a register value to extract a bit filed value.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of register.

-  \return           Masked and shifted bit field value.

-*/

-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)

-

-/*@} end of group CMSIS_core_bitfield */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_base     Core Definitions

-  \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M3 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */

-

-#if (__MPU_PRESENT == 1U)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/**

-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-  \brief    Functions that manage interrupts and exceptions via the NVIC.

-  @{

- */

-

-/**

-  \brief   Set Priority Grouping

-  \details Sets the priority grouping field using the required unlock sequence.

-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-           Only values from 0..7 are used.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */

-  reg_value  =  (reg_value                                   |

-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/**

-  \brief   Get Priority Grouping

-  \details Reads the priority grouping field from the NVIC Interrupt Controller.

-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

-}

-

-

-/**

-  \brief   Enable External Interrupt

-  \details Enables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Disable External Interrupt

-  \details Disables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Pending Interrupt

-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not pending.

-  \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Pending Interrupt

-  \details Sets the pending bit of an external interrupt.

-  \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Clear Pending Interrupt

-  \details Clears the pending bit of an external interrupt.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Active Interrupt

-  \details Reads the active register in NVIC and returns the active bit.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not active.

-  \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Interrupt Priority

-  \details Sets the priority of an interrupt.

-  \note    The priority cannot be set for every core interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if ((int32_t)(IRQn) < 0)

-  {

-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-  else

-  {

-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-}

-

-

-/**

-  \brief   Get Interrupt Priority

-  \details Reads the priority of an interrupt.

-           The interrupt number can be positive to specify an external (device specific) interrupt,

-           or negative to specify an internal (core) interrupt.

-  \param [in]   IRQn  Interrupt number.

-  \return             Interrupt Priority.

-                      Value is aligned automatically to the implemented priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if ((int32_t)(IRQn) < 0)

-  {

-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));

-  }

-  else

-  {

-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));

-  }

-}

-

-

-/**

-  \brief   Encode Priority

-  \details Encodes the priority for an interrupt with the given priority group,

-           preemptive priority value, and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]     PriorityGroup  Used priority group.

-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-  \param [in]       SubPriority  Subpriority value (starting from 0).

-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  return (

-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

-         );

-}

-

-

-/**

-  \brief   Decode Priority

-  \details Decodes an interrupt priority value with a given priority group to

-           preemptive priority value and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-  \param [in]     PriorityGroup  Used priority group.

-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-  \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

-}

-

-

-/**

-  \brief   System Reset

-  \details Initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                          /* Ensure all outstanding memory accesses included

-                                                                       buffered write are completed before reset */

-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

-  __DSB();                                                          /* Ensure completion of memory access */

-

-  for(;;)                                                           /* wait until reset */

-  {

-    __NOP();

-  }

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-  \brief    Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0U)

-

-/**

-  \brief   System Tick Configuration

-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.

-           Counter is in free running mode to generate periodic interrupts.

-  \param [in]  ticks  Number of ticks between two interrupts.

-  \return          0  Function succeeded.

-  \return          1  Function failed.

-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-           must contain a vendor-specific implementation of this function.

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

-  {

-    return (1UL);                                                   /* Reload value impossible */

-  }

-

-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

-  return (0UL);                                                     /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_core_DebugFunctions ITM Functions

-  \brief    Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */

-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/**

-  \brief   ITM Send Character

-  \details Transmits a character via the ITM channel 0, and

-           \li Just returns when no debugger is connected that has booked the output.

-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-  \param [in]     ch  Character to transmit.

-  \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0U].u32 == 0UL)

-    {

-      __NOP();

-    }

-    ITM->PORT[0U].u8 = (uint8_t)ch;

-  }

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Receive Character

-  \details Inputs a character via the external variable \ref ITM_RxBuffer.

-  \return             Received character.

-  \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void)

-{

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)

-  {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Check Character

-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-  \return          0  No character available.

-  \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void)

-{

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)

-  {

-    return (0);                              /* no character available */

-  }

-  else

-  {

-    return (1);                              /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM3_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/core_cm33.h b/os/common/ext/ARM/CMSIS/Core/Include/core_cm33.h
new file mode 100644
index 000000000..fab2f9a11
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_cm33.h
@@ -0,0 +1,2898 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )     /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/CMSIS/include/core_cm4.h b/os/common/ext/ARM/CMSIS/Core/Include/core_cm4.h
index 01cb73bf3..ad3bc27d5 100644
--- a/os/common/ext/CMSIS/include/core_cm4.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_cm4.h
@@ -1,1937 +1,2113 @@
-/**************************************************************************//**

- * @file     core_cm4.h

- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CM4_H_GENERIC

-#define __CORE_CM4_H_GENERIC

-

-#include <stdint.h>

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/**

-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/**

-  \ingroup Cortex_M4

-  @{

- */

-

-/*  CMSIS CM4 definitions */

-#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */

-#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */

-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \

-                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */

-

-#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */

-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */

-  #define __STATIC_INLINE  static inline

-

-#else

-  #error Unknown compiler

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

-*/

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #if defined __ARM_PCS_VFP

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1U

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __CSMC__ )

-  #if ( __CSMC__ & 0x400U)

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#endif

-

-#include "core_cmInstr.h"                /* Core Instruction Access */

-#include "core_cmFunc.h"                 /* Core Function Access */

-#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM4_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM4_H_DEPENDANT

-#define __CORE_CM4_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM4_REV

-    #define __CM4_REV               0x0000U

-    #warning "__CM4_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __FPU_PRESENT

-    #define __FPU_PRESENT             0U

-    #warning "__FPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0U

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          4U

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0U

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions */

-

-/* following defines should be used for structure members */

-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */

-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */

-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

-

-/*@} end of group Cortex_M4 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

-  - Core FPU Register

- ******************************************************************************/

-/**

-  \defgroup CMSIS_core_register Defines and Type Definitions

-  \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_CORE  Status and Control Registers

-  \brief      Core Register type definitions.

-  @{

- */

-

-/**

-  \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} APSR_Type;

-

-/* APSR Register Definitions */

-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */

-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

-

-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */

-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

-

-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */

-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

-

-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */

-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

-

-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */

-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

-

-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */

-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */

-

-

-/**

-  \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} IPSR_Type;

-

-/* IPSR Register Definitions */

-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */

-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} xPSR_Type;

-

-/* xPSR Register Definitions */

-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */

-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

-

-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */

-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

-

-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */

-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

-

-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */

-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

-

-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */

-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

-

-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */

-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

-

-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */

-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

-

-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */

-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */

-

-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */

-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} CONTROL_Type;

-

-/* CONTROL Register Definitions */

-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */

-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */

-

-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */

-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

-

-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */

-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

-

-/*@} end of group CMSIS_CORE */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-  \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

-        uint32_t RESERVED0[24U];

-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

-        uint32_t RSERVED1[24U];

-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

-        uint32_t RESERVED2[24U];

-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

-        uint32_t RESERVED3[24U];

-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */

-        uint32_t RESERVED4[56U];

-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-        uint32_t RESERVED5[644U];

-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCB     System Control Block (SCB)

-  \brief    Type definitions for the System Control Block Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */

-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */

-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */

-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */

-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */

-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */

-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */

-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */

-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */

-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */

-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */

-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */

-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */

-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */

-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */

-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */

-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */

-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */

-        uint32_t RESERVED0[5U];

-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Register Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Register Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-  \brief    Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-        uint32_t RESERVED0[1U];

-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */

-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

-

-/* Auxiliary Control Register Definitions */

-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */

-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */

-

-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */

-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */

-

-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */

-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

-

-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */

-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

-

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-  \brief    Type definitions for the System Timer Registers.

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */

-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */

-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __OM  union

-  {

-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */

-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */

-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */

-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */

-        uint32_t RESERVED0[864U];

-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */

-        uint32_t RESERVED1[15U];

-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */

-        uint32_t RESERVED2[15U];

-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */

-        uint32_t RESERVED3[29U];

-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */

-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */

-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */

-        uint32_t RESERVED4[43U];

-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */

-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */

-        uint32_t RESERVED5[6U];

-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */

-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */

-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */

-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */

-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */

-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */

-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */

-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */

-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */

-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */

-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */

-        uint32_t RESERVED0[1U];

-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */

-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */

-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */

-        uint32_t RESERVED1[1U];

-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */

-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */

-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */

-        uint32_t RESERVED2[1U];

-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */

-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */

-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-  \brief    Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */

-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-        uint32_t RESERVED0[2U];

-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-        uint32_t RESERVED1[55U];

-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-        uint32_t RESERVED2[131U];

-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-        uint32_t RESERVED3[759U];

-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-        uint32_t RESERVED4[1U];

-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-        uint32_t RESERVED5[39U];

-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-        uint32_t RESERVED7[8U];

-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-  \brief    Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */

-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */

-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */

-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */

-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */

-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */

-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register Definitions */

-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register Definitions */

-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register Definitions */

-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register Definitions */

-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register Definitions */

-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-#if (__FPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)

-  \brief    Type definitions for the Floating Point Unit (FPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Floating Point Unit (FPU).

- */

-typedef struct

-{

-        uint32_t RESERVED0[1U];

-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */

-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */

-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */

-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */

-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */

-} FPU_Type;

-

-/* Floating-Point Context Control Register Definitions */

-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */

-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */

-

-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */

-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */

-

-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */

-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */

-

-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */

-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */

-

-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */

-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */

-

-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */

-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */

-

-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */

-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */

-

-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */

-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

-

-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */

-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */

-

-/* Floating-Point Context Address Register Definitions */

-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */

-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */

-

-/* Floating-Point Default Status Control Register Definitions */

-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */

-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */

-

-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */

-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */

-

-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */

-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */

-

-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */

-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

-

-/* Media and FP Feature Register 0 Definitions */

-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */

-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

-

-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */

-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */

-

-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */

-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */

-

-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */

-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */

-

-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */

-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */

-

-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */

-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */

-

-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */

-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

-

-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */

-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */

-

-/* Media and FP Feature Register 1 Definitions */

-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */

-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

-

-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */

-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */

-

-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */

-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

-

-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */

-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */

-

-/*@} end of group CMSIS_FPU */

-#endif

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-  \brief    Type definitions for the Core Debug Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */

-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */

-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */

-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register Definitions */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register Definitions */

-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register Definitions */

-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_bitfield     Core register bit field macros

-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

-  @{

- */

-

-/**

-  \brief   Mask and shift a bit field value for use in a register bit range.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of the bit field.

-  \return           Masked and shifted value.

-*/

-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)

-

-/**

-  \brief     Mask and shift a register value to extract a bit filed value.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of register.

-  \return           Masked and shifted bit field value.

-*/

-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)

-

-/*@} end of group CMSIS_core_bitfield */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_base     Core Definitions

-  \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M4 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */

-

-#if (__MPU_PRESENT == 1U)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */

-#endif

-

-#if (__FPU_PRESENT == 1U)

-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */

-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/**

-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-  \brief    Functions that manage interrupts and exceptions via the NVIC.

-  @{

- */

-

-/**

-  \brief   Set Priority Grouping

-  \details Sets the priority grouping field using the required unlock sequence.

-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-           Only values from 0..7 are used.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */

-  reg_value  =  (reg_value                                   |

-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/**

-  \brief   Get Priority Grouping

-  \details Reads the priority grouping field from the NVIC Interrupt Controller.

-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

-}

-

-

-/**

-  \brief   Enable External Interrupt

-  \details Enables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Disable External Interrupt

-  \details Disables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Pending Interrupt

-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not pending.

-  \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Pending Interrupt

-  \details Sets the pending bit of an external interrupt.

-  \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Clear Pending Interrupt

-  \details Clears the pending bit of an external interrupt.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Active Interrupt

-  \details Reads the active register in NVIC and returns the active bit.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not active.

-  \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Interrupt Priority

-  \details Sets the priority of an interrupt.

-  \note    The priority cannot be set for every core interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if ((int32_t)(IRQn) < 0)

-  {

-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-  else

-  {

-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-}

-

-

-/**

-  \brief   Get Interrupt Priority

-  \details Reads the priority of an interrupt.

-           The interrupt number can be positive to specify an external (device specific) interrupt,

-           or negative to specify an internal (core) interrupt.

-  \param [in]   IRQn  Interrupt number.

-  \return             Interrupt Priority.

-                      Value is aligned automatically to the implemented priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if ((int32_t)(IRQn) < 0)

-  {

-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));

-  }

-  else

-  {

-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));

-  }

-}

-

-

-/**

-  \brief   Encode Priority

-  \details Encodes the priority for an interrupt with the given priority group,

-           preemptive priority value, and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]     PriorityGroup  Used priority group.

-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-  \param [in]       SubPriority  Subpriority value (starting from 0).

-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  return (

-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

-         );

-}

-

-

-/**

-  \brief   Decode Priority

-  \details Decodes an interrupt priority value with a given priority group to

-           preemptive priority value and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-  \param [in]     PriorityGroup  Used priority group.

-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-  \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

-}

-

-

-/**

-  \brief   System Reset

-  \details Initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                          /* Ensure all outstanding memory accesses included

-                                                                       buffered write are completed before reset */

-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

-  __DSB();                                                          /* Ensure completion of memory access */

-

-  for(;;)                                                           /* wait until reset */

-  {

-    __NOP();

-  }

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-  \brief    Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0U)

-

-/**

-  \brief   System Tick Configuration

-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.

-           Counter is in free running mode to generate periodic interrupts.

-  \param [in]  ticks  Number of ticks between two interrupts.

-  \return          0  Function succeeded.

-  \return          1  Function failed.

-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-           must contain a vendor-specific implementation of this function.

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

-  {

-    return (1UL);                                                   /* Reload value impossible */

-  }

-

-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

-  return (0UL);                                                     /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_core_DebugFunctions ITM Functions

-  \brief    Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */

-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/**

-  \brief   ITM Send Character

-  \details Transmits a character via the ITM channel 0, and

-           \li Just returns when no debugger is connected that has booked the output.

-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-  \param [in]     ch  Character to transmit.

-  \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0U].u32 == 0UL)

-    {

-      __NOP();

-    }

-    ITM->PORT[0U].u8 = (uint8_t)ch;

-  }

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Receive Character

-  \details Inputs a character via the external variable \ref ITM_RxBuffer.

-  \return             Received character.

-  \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void)

-{

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)

-  {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Check Character

-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-  \return          0  No character available.

-  \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void)

-{

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)

-  {

-    return (0);                              /* no character available */

-  }

-  else

-  {

-    return (1);                              /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM4_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/CMSIS/include/core_cm7.h b/os/common/ext/ARM/CMSIS/Core/Include/core_cm7.h
index 20963c148..bf701fe8e 100644
--- a/os/common/ext/CMSIS/include/core_cm7.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_cm7.h
@@ -1,2512 +1,2655 @@
-/**************************************************************************//**

- * @file     core_cm7.h

- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CM7_H_GENERIC

-#define __CORE_CM7_H_GENERIC

-

-#include <stdint.h>

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/**

-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/**

-  \ingroup Cortex_M7

-  @{

- */

-

-/*  CMSIS CM7 definitions */

-#define __CM7_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */

-#define __CM7_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */

-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \

-                                    __CM7_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */

-

-#define __CORTEX_M                (0x07U)                                      /*!< Cortex-M Core */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */

-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */

-  #define __STATIC_INLINE  static inline

-

-#else

-  #error Unknown compiler

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

-*/

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #if defined __ARM_PCS_VFP

-    #if (__FPU_PRESENT == 1)

-      #define __FPU_USED       1U

-    #else

-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#elif defined ( __CSMC__ )

-  #if ( __CSMC__ & 0x400U)

-    #if (__FPU_PRESENT == 1U)

-      #define __FPU_USED       1U

-    #else

-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-      #define __FPU_USED       0U

-    #endif

-  #else

-    #define __FPU_USED         0U

-  #endif

-

-#endif

-

-#include "core_cmInstr.h"                /* Core Instruction Access */

-#include "core_cmFunc.h"                 /* Core Function Access */

-#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM7_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_CM7_H_DEPENDANT

-#define __CORE_CM7_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __CM7_REV

-    #define __CM7_REV               0x0000U

-    #warning "__CM7_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __FPU_PRESENT

-    #define __FPU_PRESENT             0U

-    #warning "__FPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0U

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __ICACHE_PRESENT

-    #define __ICACHE_PRESENT          0U

-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __DCACHE_PRESENT

-    #define __DCACHE_PRESENT          0U

-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __DTCM_PRESENT

-    #define __DTCM_PRESENT            0U

-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          3U

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0U

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions */

-

-/* following defines should be used for structure members */

-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */

-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */

-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

-

-/*@} end of group Cortex_M7 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

-  - Core FPU Register

- ******************************************************************************/

-/**

-  \defgroup CMSIS_core_register Defines and Type Definitions

-  \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_CORE  Status and Control Registers

-  \brief      Core Register type definitions.

-  @{

- */

-

-/**

-  \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */

-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} APSR_Type;

-

-/* APSR Register Definitions */

-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */

-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

-

-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */

-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

-

-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */

-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

-

-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */

-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

-

-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */

-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

-

-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */

-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */

-

-

-/**

-  \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} IPSR_Type;

-

-/* IPSR Register Definitions */

-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */

-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */

-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */

-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} xPSR_Type;

-

-/* xPSR Register Definitions */

-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */

-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

-

-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */

-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

-

-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */

-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

-

-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */

-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

-

-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */

-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

-

-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */

-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

-

-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */

-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

-

-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */

-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */

-

-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */

-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */

-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */

-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} CONTROL_Type;

-

-/* CONTROL Register Definitions */

-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */

-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */

-

-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */

-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

-

-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */

-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

-

-/*@} end of group CMSIS_CORE */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-  \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

-        uint32_t RESERVED0[24U];

-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

-        uint32_t RSERVED1[24U];

-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

-        uint32_t RESERVED2[24U];

-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

-        uint32_t RESERVED3[24U];

-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */

-        uint32_t RESERVED4[56U];

-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-        uint32_t RESERVED5[644U];

-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCB     System Control Block (SCB)

-  \brief    Type definitions for the System Control Block Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */

-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */

-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */

-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */

-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */

-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */

-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */

-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */

-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */

-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */

-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */

-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */

-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */

-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */

-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */

-  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */

-  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */

-  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */

-        uint32_t RESERVED0[1U];

-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */

-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */

-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */

-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */

-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */

-        uint32_t RESERVED3[93U];

-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */

-        uint32_t RESERVED4[15U];

-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */

-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */

-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */

-        uint32_t RESERVED5[1U];

-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */

-        uint32_t RESERVED6[1U];

-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */

-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */

-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */

-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */

-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */

-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */

-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */

-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */

-        uint32_t RESERVED7[6U];

-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */

-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */

-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */

-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */

-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */

-        uint32_t RESERVED8[1U];

-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */

-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */

-

-#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */

-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */

-

-#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */

-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */

-

-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Register Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Register Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

-

-/* SCB Cache Level ID Register Definitions */

-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */

-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */

-

-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */

-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */

-

-/* SCB Cache Type Register Definitions */

-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */

-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */

-

-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */

-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */

-

-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */

-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */

-

-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */

-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */

-

-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */

-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */

-

-/* SCB Cache Size ID Register Definitions */

-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */

-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */

-

-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */

-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */

-

-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */

-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */

-

-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */

-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */

-

-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */

-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */

-

-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */

-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */

-

-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */

-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */

-

-/* SCB Cache Size Selection Register Definitions */

-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */

-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */

-

-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */

-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */

-

-/* SCB Software Triggered Interrupt Register Definitions */

-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */

-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */

-

-/* SCB D-Cache Invalidate by Set-way Register Definitions */

-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */

-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */

-

-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */

-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */

-

-/* SCB D-Cache Clean by Set-way Register Definitions */

-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */

-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */

-

-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */

-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */

-

-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */

-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */

-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */

-

-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */

-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */

-

-/* Instruction Tightly-Coupled Memory Control Register Definitions */

-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */

-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */

-

-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */

-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */

-

-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */

-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */

-

-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */

-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */

-

-/* Data Tightly-Coupled Memory Control Register Definitions */

-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */

-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */

-

-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */

-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */

-

-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */

-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */

-

-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */

-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */

-

-/* AHBP Control Register Definitions */

-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */

-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */

-

-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */

-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */

-

-/* L1 Cache Control Register Definitions */

-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */

-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */

-

-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */

-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */

-

-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */

-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */

-

-/* AHBS Control Register Definitions */

-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */

-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */

-

-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */

-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */

-

-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/

-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */

-

-/* Auxiliary Bus Fault Status Register Definitions */

-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/

-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */

-

-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/

-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */

-

-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/

-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */

-

-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/

-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */

-

-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/

-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */

-

-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/

-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-  \brief    Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-        uint32_t RESERVED0[1U];

-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */

-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

-

-/* Auxiliary Control Register Definitions */

-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */

-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */

-

-#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */

-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */

-

-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */

-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */

-

-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */

-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

-

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-  \brief    Type definitions for the System Timer Registers.

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */

-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */

-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __OM  union

-  {

-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */

-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */

-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */

-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */

-        uint32_t RESERVED0[864U];

-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */

-        uint32_t RESERVED1[15U];

-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */

-        uint32_t RESERVED2[15U];

-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */

-        uint32_t RESERVED3[29U];

-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */

-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */

-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */

-        uint32_t RESERVED4[43U];

-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */

-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */

-        uint32_t RESERVED5[6U];

-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */

-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */

-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */

-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */

-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */

-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */

-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */

-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */

-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */

-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */

-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */

-        uint32_t RESERVED0[1U];

-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */

-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */

-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */

-        uint32_t RESERVED1[1U];

-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */

-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */

-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */

-        uint32_t RESERVED2[1U];

-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */

-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */

-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */

-        uint32_t RESERVED3[981U];

-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */

-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-  \brief    Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */

-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-        uint32_t RESERVED0[2U];

-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-        uint32_t RESERVED1[55U];

-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-        uint32_t RESERVED2[131U];

-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-        uint32_t RESERVED3[759U];

-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-        uint32_t RESERVED4[1U];

-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-        uint32_t RESERVED5[39U];

-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-        uint32_t RESERVED7[8U];

-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-  \brief    Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */

-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */

-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */

-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */

-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */

-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */

-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register Definitions */

-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register Definitions */

-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register Definitions */

-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register Definitions */

-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register Definitions */

-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-#if (__FPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)

-  \brief    Type definitions for the Floating Point Unit (FPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Floating Point Unit (FPU).

- */

-typedef struct

-{

-        uint32_t RESERVED0[1U];

-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */

-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */

-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */

-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */

-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */

-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */

-} FPU_Type;

-

-/* Floating-Point Context Control Register Definitions */

-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */

-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */

-

-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */

-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */

-

-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */

-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */

-

-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */

-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */

-

-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */

-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */

-

-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */

-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */

-

-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */

-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */

-

-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */

-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

-

-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */

-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */

-

-/* Floating-Point Context Address Register Definitions */

-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */

-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */

-

-/* Floating-Point Default Status Control Register Definitions */

-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */

-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */

-

-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */

-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */

-

-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */

-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */

-

-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */

-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

-

-/* Media and FP Feature Register 0 Definitions */

-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */

-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

-

-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */

-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */

-

-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */

-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */

-

-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */

-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */

-

-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */

-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */

-

-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */

-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */

-

-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */

-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

-

-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */

-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */

-

-/* Media and FP Feature Register 1 Definitions */

-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */

-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

-

-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */

-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */

-

-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */

-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

-

-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */

-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */

-

-/* Media and FP Feature Register 2 Definitions */

-

-/*@} end of group CMSIS_FPU */

-#endif

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-  \brief    Type definitions for the Core Debug Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */

-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */

-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */

-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register Definitions */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register Definitions */

-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register Definitions */

-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_bitfield     Core register bit field macros

-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

-  @{

- */

-

-/**

-  \brief   Mask and shift a bit field value for use in a register bit range.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of the bit field.

-  \return           Masked and shifted value.

-*/

-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)

-

-/**

-  \brief     Mask and shift a register value to extract a bit filed value.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of register.

-  \return           Masked and shifted bit field value.

-*/

-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)

-

-/*@} end of group CMSIS_core_bitfield */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_base     Core Definitions

-  \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M4 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */

-

-#if (__MPU_PRESENT == 1U)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */

-#endif

-

-#if (__FPU_PRESENT == 1U)

-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */

-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/**

-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-  \brief    Functions that manage interrupts and exceptions via the NVIC.

-  @{

- */

-

-/**

-  \brief   Set Priority Grouping

-  \details Sets the priority grouping field using the required unlock sequence.

-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-           Only values from 0..7 are used.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */

-  reg_value  =  (reg_value                                   |

-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/**

-  \brief   Get Priority Grouping

-  \details Reads the priority grouping field from the NVIC Interrupt Controller.

-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

-}

-

-

-/**

-  \brief   Enable External Interrupt

-  \details Enables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Disable External Interrupt

-  \details Disables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Pending Interrupt

-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not pending.

-  \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Pending Interrupt

-  \details Sets the pending bit of an external interrupt.

-  \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Clear Pending Interrupt

-  \details Clears the pending bit of an external interrupt.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Active Interrupt

-  \details Reads the active register in NVIC and returns the active bit.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not active.

-  \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Interrupt Priority

-  \details Sets the priority of an interrupt.

-  \note    The priority cannot be set for every core interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if ((int32_t)(IRQn) < 0)

-  {

-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-  else

-  {

-    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-}

-

-

-/**

-  \brief   Get Interrupt Priority

-  \details Reads the priority of an interrupt.

-           The interrupt number can be positive to specify an external (device specific) interrupt,

-           or negative to specify an internal (core) interrupt.

-  \param [in]   IRQn  Interrupt number.

-  \return             Interrupt Priority.

-                      Value is aligned automatically to the implemented priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if ((int32_t)(IRQn) < 0)

-  {

-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));

-  }

-  else

-  {

-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));

-  }

-}

-

-

-/**

-  \brief   Encode Priority

-  \details Encodes the priority for an interrupt with the given priority group,

-           preemptive priority value, and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]     PriorityGroup  Used priority group.

-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-  \param [in]       SubPriority  Subpriority value (starting from 0).

-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  return (

-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

-         );

-}

-

-

-/**

-  \brief   Decode Priority

-  \details Decodes an interrupt priority value with a given priority group to

-           preemptive priority value and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-  \param [in]     PriorityGroup  Used priority group.

-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-  \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

-}

-

-

-/**

-  \brief   System Reset

-  \details Initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                          /* Ensure all outstanding memory accesses included

-                                                                       buffered write are completed before reset */

-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

-  __DSB();                                                          /* Ensure completion of memory access */

-

-  for(;;)                                                           /* wait until reset */

-  {

-    __NOP();

-  }

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-/* ##########################  FPU functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_FpuFunctions FPU Functions

-  \brief    Function that provides FPU type.

-  @{

- */

-

-/**

-  \brief   get FPU type

-  \details returns the FPU type

-  \returns

-   - \b  0: No FPU

-   - \b  1: Single precision FPU

-   - \b  2: Double + Single precision FPU

- */

-__STATIC_INLINE uint32_t SCB_GetFPUType(void)

-{

-  uint32_t mvfr0;

-

-  mvfr0 = SCB->MVFR0;

-  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL)

-  {

-    return 2UL;           /* Double + Single precision FPU */

-  }

-  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)

-  {

-    return 1UL;           /* Single precision FPU */

-  }

-  else

-  {

-    return 0UL;           /* No FPU */

-  }

-}

-

-

-/*@} end of CMSIS_Core_FpuFunctions */

-

-

-

-/* ##########################  Cache functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_CacheFunctions Cache Functions

-  \brief    Functions that configure Instruction and Data cache.

-  @{

- */

-

-/* Cache Size ID Register Macros */

-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )

-

-

-/**

-  \brief   Enable I-Cache

-  \details Turns on I-Cache

-  */

-__STATIC_INLINE void SCB_EnableICache (void)

-{

-  #if (__ICACHE_PRESENT == 1U)

-    __DSB();

-    __ISB();

-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */

-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   Disable I-Cache

-  \details Turns off I-Cache

-  */

-__STATIC_INLINE void SCB_DisableICache (void)

-{

-  #if (__ICACHE_PRESENT == 1U)

-    __DSB();

-    __ISB();

-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */

-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   Invalidate I-Cache

-  \details Invalidates I-Cache

-  */

-__STATIC_INLINE void SCB_InvalidateICache (void)

-{

-  #if (__ICACHE_PRESENT == 1U)

-    __DSB();

-    __ISB();

-    SCB->ICIALLU = 0UL;

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   Enable D-Cache

-  \details Turns on D-Cache

-  */

-__STATIC_INLINE void SCB_EnableDCache (void)

-{

-  #if (__DCACHE_PRESENT == 1U)

-    uint32_t ccsidr;

-    uint32_t sets;

-    uint32_t ways;

-

-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */

-    __DSB();

-

-    ccsidr = SCB->CCSIDR;

-

-                                            /* invalidate D-Cache */

-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

-    do {

-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

-      do {

-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |

-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );

-        #if defined ( __CC_ARM )

-          __schedule_barrier();

-        #endif

-      } while (ways--);

-    } while(sets--);

-    __DSB();

-

-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   Disable D-Cache

-  \details Turns off D-Cache

-  */

-__STATIC_INLINE void SCB_DisableDCache (void)

-{

-  #if (__DCACHE_PRESENT == 1U)

-    uint32_t ccsidr;

-    uint32_t sets;

-    uint32_t ways;

-

-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */

-    __DSB();

-

-    ccsidr = SCB->CCSIDR;

-

-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */

-

-                                            /* clean & invalidate D-Cache */

-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

-    do {

-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

-      do {

-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |

-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );

-        #if defined ( __CC_ARM )

-          __schedule_barrier();

-        #endif

-      } while (ways--);

-    } while(sets--);

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   Invalidate D-Cache

-  \details Invalidates D-Cache

-  */

-__STATIC_INLINE void SCB_InvalidateDCache (void)

-{

-  #if (__DCACHE_PRESENT == 1U)

-    uint32_t ccsidr;

-    uint32_t sets;

-    uint32_t ways;

-

-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */

-    __DSB();

-

-    ccsidr = SCB->CCSIDR;

-

-                                            /* invalidate D-Cache */

-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

-    do {

-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

-      do {

-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |

-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );

-        #if defined ( __CC_ARM )

-          __schedule_barrier();

-        #endif

-      } while (ways--);

-    } while(sets--);

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   Clean D-Cache

-  \details Cleans D-Cache

-  */

-__STATIC_INLINE void SCB_CleanDCache (void)

-{

-  #if (__DCACHE_PRESENT == 1U)

-    uint32_t ccsidr;

-    uint32_t sets;

-    uint32_t ways;

-

-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */

-    __DSB();

-

-    ccsidr = SCB->CCSIDR;

-

-                                            /* clean D-Cache */

-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

-    do {

-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

-      do {

-        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |

-                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );

-        #if defined ( __CC_ARM )

-          __schedule_barrier();

-        #endif

-      } while (ways--);

-    } while(sets--);

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   Clean & Invalidate D-Cache

-  \details Cleans and Invalidates D-Cache

-  */

-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)

-{

-  #if (__DCACHE_PRESENT == 1U)

-    uint32_t ccsidr;

-    uint32_t sets;

-    uint32_t ways;

-

-    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */

-    __DSB();

-

-    ccsidr = SCB->CCSIDR;

-

-                                            /* clean & invalidate D-Cache */

-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));

-    do {

-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));

-      do {

-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |

-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );

-        #if defined ( __CC_ARM )

-          __schedule_barrier();

-        #endif

-      } while (ways--);

-    } while(sets--);

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   D-Cache Invalidate by address

-  \details Invalidates D-Cache for the given address

-  \param[in]   addr    address (aligned to 32-byte boundary)

-  \param[in]   dsize   size of memory block (in number of bytes)

-*/

-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)

-{

-  #if (__DCACHE_PRESENT == 1U)

-     int32_t op_size = dsize;

-    uint32_t op_addr = (uint32_t)addr;

-     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */

-

-    __DSB();

-

-    while (op_size > 0) {

-      SCB->DCIMVAC = op_addr;

-      op_addr += linesize;

-      op_size -= linesize;

-    }

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   D-Cache Clean by address

-  \details Cleans D-Cache for the given address

-  \param[in]   addr    address (aligned to 32-byte boundary)

-  \param[in]   dsize   size of memory block (in number of bytes)

-*/

-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)

-{

-  #if (__DCACHE_PRESENT == 1)

-     int32_t op_size = dsize;

-    uint32_t op_addr = (uint32_t) addr;

-     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */

-

-    __DSB();

-

-    while (op_size > 0) {

-      SCB->DCCMVAC = op_addr;

-      op_addr += linesize;

-      op_size -= linesize;

-    }

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/**

-  \brief   D-Cache Clean and Invalidate by address

-  \details Cleans and invalidates D_Cache for the given address

-  \param[in]   addr    address (aligned to 32-byte boundary)

-  \param[in]   dsize   size of memory block (in number of bytes)

-*/

-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)

-{

-  #if (__DCACHE_PRESENT == 1U)

-     int32_t op_size = dsize;

-    uint32_t op_addr = (uint32_t) addr;

-     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */

-

-    __DSB();

-

-    while (op_size > 0) {

-      SCB->DCCIMVAC = op_addr;

-      op_addr += linesize;

-      op_size -= linesize;

-    }

-

-    __DSB();

-    __ISB();

-  #endif

-}

-

-

-/*@} end of CMSIS_Core_CacheFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-  \brief    Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0U)

-

-/**

-  \brief   System Tick Configuration

-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.

-           Counter is in free running mode to generate periodic interrupts.

-  \param [in]  ticks  Number of ticks between two interrupts.

-  \return          0  Function succeeded.

-  \return          1  Function failed.

-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-           must contain a vendor-specific implementation of this function.

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

-  {

-    return (1UL);                                                   /* Reload value impossible */

-  }

-

-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

-  return (0UL);                                                     /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_core_DebugFunctions ITM Functions

-  \brief    Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */

-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/**

-  \brief   ITM Send Character

-  \details Transmits a character via the ITM channel 0, and

-           \li Just returns when no debugger is connected that has booked the output.

-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-  \param [in]     ch  Character to transmit.

-  \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0U].u32 == 0UL)

-    {

-      __NOP();

-    }

-    ITM->PORT[0U].u8 = (uint8_t)ch;

-  }

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Receive Character

-  \details Inputs a character via the external variable \ref ITM_RxBuffer.

-  \return             Received character.

-  \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void)

-{

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)

-  {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Check Character

-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-  \return          0  No character available.

-  \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void)

-{

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)

-  {

-    return (0);                              /* no character available */

-  }

-  else

-  {

-    return (1);                              /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CM7_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    register uint32_t ccsidr;
+    register uint32_t sets;
+    register uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/CMSIS/include/core_sc000.h b/os/common/ext/ARM/CMSIS/Core/Include/core_sc000.h
index ea16bf3ef..bd26eaa0d 100644
--- a/os/common/ext/CMSIS/include/core_sc000.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_sc000.h
@@ -1,926 +1,1016 @@
-/**************************************************************************//**

- * @file     core_sc000.h

- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_SC000_H_GENERIC

-#define __CORE_SC000_H_GENERIC

-

-#include <stdint.h>

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/**

-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/**

-  \ingroup SC000

-  @{

- */

-

-/*  CMSIS SC000 definitions */

-#define __SC000_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */

-#define __SC000_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */

-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \

-                                      __SC000_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */

-

-#define __CORTEX_SC                 (000U)                                     /*!< Cortex secure core */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */

-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */

-  #define __STATIC_INLINE  static inline

-

-#else

-  #error Unknown compiler

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0U

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #if defined __ARM_PCS_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )

-  #if ( __CSMC__ & 0x400U)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#endif

-

-#include "core_cmInstr.h"                /* Core Instruction Access */

-#include "core_cmFunc.h"                 /* Core Function Access */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC000_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_SC000_H_DEPENDANT

-#define __CORE_SC000_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __SC000_REV

-    #define __SC000_REV             0x0000U

-    #warning "__SC000_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0U

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          2U

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0U

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions */

-

-/* following defines should be used for structure members */

-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */

-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */

-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

-

-/*@} end of group SC000 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core MPU Register

- ******************************************************************************/

-/**

-  \defgroup CMSIS_core_register Defines and Type Definitions

-  \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_CORE  Status and Control Registers

-  \brief      Core Register type definitions.

-  @{

- */

-

-/**

-  \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} APSR_Type;

-

-/* APSR Register Definitions */

-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */

-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

-

-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */

-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

-

-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */

-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

-

-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */

-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

-

-

-/**

-  \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} IPSR_Type;

-

-/* IPSR Register Definitions */

-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */

-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */

-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} xPSR_Type;

-

-/* xPSR Register Definitions */

-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */

-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

-

-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */

-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

-

-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */

-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

-

-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */

-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

-

-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */

-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

-

-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */

-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */

-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} CONTROL_Type;

-

-/* CONTROL Register Definitions */

-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */

-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

-

-/*@} end of group CMSIS_CORE */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-  \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

-        uint32_t RESERVED0[31U];

-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

-        uint32_t RSERVED1[31U];

-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

-        uint32_t RESERVED2[31U];

-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

-        uint32_t RESERVED3[31U];

-        uint32_t RESERVED4[64U];

-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */

-}  NVIC_Type;

-

-/*@} end of group CMSIS_NVIC */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCB     System Control Block (SCB)

-  \brief    Type definitions for the System Control Block Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */

-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */

-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */

-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */

-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */

-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */

-        uint32_t RESERVED0[1U];

-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */

-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */

-        uint32_t RESERVED1[154U];

-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-  \brief    Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-        uint32_t RESERVED0[2U];

-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */

-} SCnSCB_Type;

-

-/* Auxiliary Control Register Definitions */

-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */

-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-  \brief    Type definitions for the System Timer Registers.

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */

-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */

-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-#if (__MPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-  \brief    Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */

-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */

-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */

-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register Definitions */

-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register Definitions */

-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register Definitions */

-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register Definitions */

-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register Definitions */

-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.

-            Therefore they are not covered by the SC000 header file.

-  @{

- */

-/*@} end of group CMSIS_CoreDebug */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_bitfield     Core register bit field macros

-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

-  @{

- */

-

-/**

-  \brief   Mask and shift a bit field value for use in a register bit range.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of the bit field.

-  \return           Masked and shifted value.

-*/

-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)

-

-/**

-  \brief     Mask and shift a register value to extract a bit filed value.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of register.

-  \return           Masked and shifted bit field value.

-*/

-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)

-

-/*@} end of group CMSIS_core_bitfield */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_base     Core Definitions

-  \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of SC000 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */

-

-#if (__MPU_PRESENT == 1U)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/**

-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-  \brief    Functions that manage interrupts and exceptions via the NVIC.

-  @{

- */

-

-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */

-/* The following MACROS handle generation of the register offset and byte masks */

-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )

-

-

-/**

-  \brief   Enable External Interrupt

-  \details Enables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Disable External Interrupt

-  \details Disables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Pending Interrupt

-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not pending.

-  \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Pending Interrupt

-  \details Sets the pending bit of an external interrupt.

-  \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Clear Pending Interrupt

-  \details Clears the pending bit of an external interrupt.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Set Interrupt Priority

-  \details Sets the priority of an interrupt.

-  \note    The priority cannot be set for every core interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if ((int32_t)(IRQn) < 0)

-  {

-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

-  }

-  else

-  {

-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |

-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));

-  }

-}

-

-

-/**

-  \brief   Get Interrupt Priority

-  \details Reads the priority of an interrupt.

-           The interrupt number can be positive to specify an external (device specific) interrupt,

-           or negative to specify an internal (core) interrupt.

-  \param [in]   IRQn  Interrupt number.

-  \return             Interrupt Priority.

-                      Value is aligned automatically to the implemented priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if ((int32_t)(IRQn) < 0)

-  {

-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));

-  }

-  else

-  {

-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));

-  }

-}

-

-

-/**

-  \brief   System Reset

-  \details Initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                          /* Ensure all outstanding memory accesses included

-                                                                       buffered write are completed before reset */

-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

-                 SCB_AIRCR_SYSRESETREQ_Msk);

-  __DSB();                                                          /* Ensure completion of memory access */

-

-  for(;;)                                                           /* wait until reset */

-  {

-    __NOP();

-  }

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-  \brief    Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0U)

-

-/**

-  \brief   System Tick Configuration

-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.

-           Counter is in free running mode to generate periodic interrupts.

-  \param [in]  ticks  Number of ticks between two interrupts.

-  \return          0  Function succeeded.

-  \return          1  Function failed.

-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-           must contain a vendor-specific implementation of this function.

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

-  {

-    return (1UL);                                                   /* Reload value impossible */

-  }

-

-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

-  return (0UL);                                                     /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC000_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/CMSIS/include/core_sc300.h b/os/common/ext/ARM/CMSIS/Core/Include/core_sc300.h
index 820cef4f8..780372a35 100644
--- a/os/common/ext/CMSIS/include/core_sc300.h
+++ b/os/common/ext/ARM/CMSIS/Core/Include/core_sc300.h
@@ -1,1745 +1,1903 @@
-/**************************************************************************//**

- * @file     core_sc300.h

- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_SC300_H_GENERIC

-#define __CORE_SC300_H_GENERIC

-

-#include <stdint.h>

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/**

-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

-  CMSIS violates the following MISRA-C:2004 rules:

-

-   \li Required Rule 8.5, object/function definition in header file.<br>

-     Function definitions in header files are used to allow 'inlining'.

-

-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

-     Unions are used for effective representation of core registers.

-

-   \li Advisory Rule 19.7, Function-like macro defined.<br>

-     Function-like macros are used to allow more efficient code.

- */

-

-

-/*******************************************************************************

- *                 CMSIS definitions

- ******************************************************************************/

-/**

-  \ingroup SC3000

-  @{

- */

-

-/*  CMSIS SC300 definitions */

-#define __SC300_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */

-#define __SC300_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */

-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \

-                                      __SC300_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */

-

-#define __CORTEX_SC                 (300U)                                     /*!< Cortex secure core */

-

-

-#if   defined ( __CC_ARM )

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */

-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */

-  #define __STATIC_INLINE  static __inline

-

-#elif defined ( __GNUC__ )

-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __ICCARM__ )

-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TMS470__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __TASKING__ )

-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */

-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */

-  #define __STATIC_INLINE  static inline

-

-#elif defined ( __CSMC__ )

-  #define __packed

-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */

-  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */

-  #define __STATIC_INLINE  static inline

-

-#else

-  #error Unknown compiler

-#endif

-

-/** __FPU_USED indicates whether an FPU is used or not.

-    This core does not support an FPU at all

-*/

-#define __FPU_USED       0U

-

-#if defined ( __CC_ARM )

-  #if defined __TARGET_FPU_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #if defined __ARM_PCS_VFP

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __GNUC__ )

-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __ICCARM__ )

-  #if defined __ARMVFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TMS470__ )

-  #if defined __TI_VFP_SUPPORT__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __TASKING__ )

-  #if defined __FPU_VFP__

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#elif defined ( __CSMC__ )

-  #if ( __CSMC__ & 0x400U)

-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

-  #endif

-

-#endif

-

-#include "core_cmInstr.h"                /* Core Instruction Access */

-#include "core_cmFunc.h"                 /* Core Function Access */

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC300_H_GENERIC */

-

-#ifndef __CMSIS_GENERIC

-

-#ifndef __CORE_SC300_H_DEPENDANT

-#define __CORE_SC300_H_DEPENDANT

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-/* check device defines and use defaults */

-#if defined __CHECK_DEVICE_DEFINES

-  #ifndef __SC300_REV

-    #define __SC300_REV               0x0000U

-    #warning "__SC300_REV not defined in device header file; using default!"

-  #endif

-

-  #ifndef __MPU_PRESENT

-    #define __MPU_PRESENT             0U

-    #warning "__MPU_PRESENT not defined in device header file; using default!"

-  #endif

-

-  #ifndef __NVIC_PRIO_BITS

-    #define __NVIC_PRIO_BITS          4U

-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

-  #endif

-

-  #ifndef __Vendor_SysTickConfig

-    #define __Vendor_SysTickConfig    0U

-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

-  #endif

-#endif

-

-/* IO definitions (access restrictions to peripheral registers) */

-/**

-    \defgroup CMSIS_glob_defs CMSIS Global Defines

-

-    <strong>IO Type Qualifiers</strong> are used

-    \li to specify the access to peripheral variables.

-    \li for automatic generation of peripheral register debug information.

-*/

-#ifdef __cplusplus

-  #define   __I     volatile             /*!< Defines 'read only' permissions */

-#else

-  #define   __I     volatile const       /*!< Defines 'read only' permissions */

-#endif

-#define     __O     volatile             /*!< Defines 'write only' permissions */

-#define     __IO    volatile             /*!< Defines 'read / write' permissions */

-

-/* following defines should be used for structure members */

-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */

-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */

-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */

-

-/*@} end of group SC300 */

-

-

-

-/*******************************************************************************

- *                 Register Abstraction

-  Core Register contain:

-  - Core Register

-  - Core NVIC Register

-  - Core SCB Register

-  - Core SysTick Register

-  - Core Debug Register

-  - Core MPU Register

- ******************************************************************************/

-/**

-  \defgroup CMSIS_core_register Defines and Type Definitions

-  \brief Type definitions and defines for Cortex-M processor based devices.

-*/

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_CORE  Status and Control Registers

-  \brief      Core Register type definitions.

-  @{

- */

-

-/**

-  \brief  Union type to access the Application Program Status Register (APSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} APSR_Type;

-

-/* APSR Register Definitions */

-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */

-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */

-

-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */

-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */

-

-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */

-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */

-

-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */

-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */

-

-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */

-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */

-

-

-/**

-  \brief  Union type to access the Interrupt Program Status Register (IPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} IPSR_Type;

-

-/* IPSR Register Definitions */

-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */

-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */

-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */

-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */

-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */

-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */

-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */

-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */

-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */

-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} xPSR_Type;

-

-/* xPSR Register Definitions */

-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */

-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */

-

-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */

-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */

-

-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */

-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */

-

-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */

-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */

-

-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */

-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */

-

-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */

-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */

-

-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */

-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */

-

-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */

-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */

-

-

-/**

-  \brief  Union type to access the Control Registers (CONTROL).

- */

-typedef union

-{

-  struct

-  {

-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */

-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */

-  } b;                                   /*!< Structure used for bit  access */

-  uint32_t w;                            /*!< Type      used for word access */

-} CONTROL_Type;

-

-/* CONTROL Register Definitions */

-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */

-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */

-

-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */

-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */

-

-/*@} end of group CMSIS_CORE */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

-  \brief      Type definitions for the NVIC Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

- */

-typedef struct

-{

-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

-        uint32_t RESERVED0[24U];

-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

-        uint32_t RSERVED1[24U];

-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

-        uint32_t RESERVED2[24U];

-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

-        uint32_t RESERVED3[24U];

-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */

-        uint32_t RESERVED4[56U];

-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

-        uint32_t RESERVED5[644U];

-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */

-}  NVIC_Type;

-

-/* Software Triggered Interrupt Register Definitions */

-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */

-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_NVIC */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCB     System Control Block (SCB)

-  \brief    Type definitions for the System Control Block Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control Block (SCB).

- */

-typedef struct

-{

-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */

-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */

-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */

-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */

-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */

-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */

-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */

-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */

-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */

-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */

-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */

-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */

-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */

-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */

-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */

-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */

-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */

-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */

-        uint32_t RESERVED0[5U];

-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */

-        uint32_t RESERVED1[129U];

-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */

-} SCB_Type;

-

-/* SCB CPUID Register Definitions */

-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */

-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

-

-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */

-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

-

-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */

-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

-

-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */

-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

-

-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */

-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */

-

-/* SCB Interrupt Control State Register Definitions */

-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */

-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

-

-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */

-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

-

-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */

-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

-

-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */

-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

-

-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */

-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

-

-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */

-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

-

-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */

-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

-

-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */

-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

-

-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */

-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

-

-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */

-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */

-

-/* SCB Vector Table Offset Register Definitions */

-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */

-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */

-

-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */

-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */

-

-/* SCB Application Interrupt and Reset Control Register Definitions */

-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */

-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

-

-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */

-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

-

-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */

-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

-

-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */

-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

-

-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */

-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

-

-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */

-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

-

-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */

-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */

-

-/* SCB System Control Register Definitions */

-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */

-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

-

-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */

-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

-

-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */

-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

-

-/* SCB Configuration Control Register Definitions */

-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */

-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

-

-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */

-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

-

-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */

-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

-

-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */

-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

-

-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */

-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

-

-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */

-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */

-

-/* SCB System Handler Control and State Register Definitions */

-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */

-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

-

-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */

-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

-

-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */

-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

-

-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */

-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

-

-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */

-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

-

-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */

-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

-

-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */

-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

-

-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */

-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

-

-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */

-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

-

-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */

-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

-

-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */

-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

-

-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */

-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

-

-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */

-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

-

-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */

-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */

-

-/* SCB Configurable Fault Status Register Definitions */

-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */

-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

-

-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */

-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

-

-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */

-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

-

-/* SCB Hard Fault Status Register Definitions */

-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */

-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

-

-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */

-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

-

-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */

-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

-

-/* SCB Debug Fault Status Register Definitions */

-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */

-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

-

-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */

-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

-

-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */

-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

-

-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */

-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

-

-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */

-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */

-

-/*@} end of group CMSIS_SCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

-  \brief    Type definitions for the System Control and ID Register not in the SCB

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Control and ID Register not in the SCB.

- */

-typedef struct

-{

-        uint32_t RESERVED0[1U];

-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */

-        uint32_t RESERVED1[1U];

-} SCnSCB_Type;

-

-/* Interrupt Controller Type Register Definitions */

-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */

-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */

-

-/*@} end of group CMSIS_SCnotSCB */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

-  \brief    Type definitions for the System Timer Registers.

-  @{

- */

-

-/**

-  \brief  Structure type to access the System Timer (SysTick).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */

-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */

-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */

-} SysTick_Type;

-

-/* SysTick Control / Status Register Definitions */

-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */

-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

-

-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */

-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

-

-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */

-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

-

-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */

-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */

-

-/* SysTick Reload Register Definitions */

-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */

-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */

-

-/* SysTick Current Register Definitions */

-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */

-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */

-

-/* SysTick Calibration Register Definitions */

-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */

-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

-

-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */

-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

-

-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */

-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */

-

-/*@} end of group CMSIS_SysTick */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

- */

-typedef struct

-{

-  __OM  union

-  {

-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */

-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */

-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */

-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */

-        uint32_t RESERVED0[864U];

-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */

-        uint32_t RESERVED1[15U];

-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */

-        uint32_t RESERVED2[15U];

-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */

-        uint32_t RESERVED3[29U];

-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */

-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */

-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */

-        uint32_t RESERVED4[43U];

-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */

-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */

-        uint32_t RESERVED5[6U];

-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

-} ITM_Type;

-

-/* ITM Trace Privilege Register Definitions */

-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */

-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */

-

-/* ITM Trace Control Register Definitions */

-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */

-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

-

-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */

-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

-

-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */

-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

-

-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */

-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

-

-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */

-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

-

-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */

-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

-

-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */

-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

-

-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */

-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

-

-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */

-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */

-

-/* ITM Integration Write Register Definitions */

-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */

-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */

-

-/* ITM Integration Read Register Definitions */

-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */

-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */

-

-/* ITM Integration Mode Control Register Definitions */

-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */

-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */

-

-/* ITM Lock Status Register Definitions */

-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */

-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

-

-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */

-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

-

-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */

-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */

-

-/*@}*/ /* end of group CMSIS_ITM */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

- */

-typedef struct

-{

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */

-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */

-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */

-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */

-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */

-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */

-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */

-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */

-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */

-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */

-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */

-        uint32_t RESERVED0[1U];

-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */

-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */

-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */

-        uint32_t RESERVED1[1U];

-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */

-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */

-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */

-        uint32_t RESERVED2[1U];

-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */

-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */

-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */

-} DWT_Type;

-

-/* DWT Control Register Definitions */

-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */

-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

-

-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */

-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

-

-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */

-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

-

-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */

-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

-

-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */

-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

-

-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */

-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

-

-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */

-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

-

-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */

-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

-

-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */

-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

-

-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */

-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

-

-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */

-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

-

-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */

-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

-

-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */

-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

-

-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */

-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

-

-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */

-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

-

-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */

-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

-

-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */

-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

-

-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */

-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */

-

-/* DWT CPI Count Register Definitions */

-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */

-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */

-

-/* DWT Exception Overhead Count Register Definitions */

-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */

-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */

-

-/* DWT Sleep Count Register Definitions */

-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */

-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */

-

-/* DWT LSU Count Register Definitions */

-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */

-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */

-

-/* DWT Folded-instruction Count Register Definitions */

-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */

-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */

-

-/* DWT Comparator Mask Register Definitions */

-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */

-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */

-

-/* DWT Comparator Function Register Definitions */

-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */

-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

-

-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */

-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

-

-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */

-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

-

-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */

-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

-

-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */

-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

-

-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */

-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

-

-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */

-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

-

-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */

-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

-

-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */

-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */

-

-/*@}*/ /* end of group CMSIS_DWT */

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)

-  \brief    Type definitions for the Trace Port Interface (TPI)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Trace Port Interface Register (TPI).

- */

-typedef struct

-{

-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */

-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

-        uint32_t RESERVED0[2U];

-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

-        uint32_t RESERVED1[55U];

-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

-        uint32_t RESERVED2[131U];

-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

-        uint32_t RESERVED3[759U];

-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */

-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

-        uint32_t RESERVED4[1U];

-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

-        uint32_t RESERVED5[39U];

-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */

-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

-        uint32_t RESERVED7[8U];

-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

-} TPI_Type;

-

-/* TPI Asynchronous Clock Prescaler Register Definitions */

-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */

-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */

-

-/* TPI Selected Pin Protocol Register Definitions */

-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */

-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */

-

-/* TPI Formatter and Flush Status Register Definitions */

-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */

-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

-

-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */

-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

-

-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */

-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

-

-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */

-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */

-

-/* TPI Formatter and Flush Control Register Definitions */

-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */

-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

-

-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */

-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

-

-/* TPI TRIGGER Register Definitions */

-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */

-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */

-

-/* TPI Integration ETM Data Register Definitions (FIFO0) */

-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */

-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

-

-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */

-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

-

-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */

-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

-

-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */

-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

-

-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */

-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

-

-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */

-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

-

-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */

-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */

-

-/* TPI ITATBCTR2 Register Definitions */

-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */

-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */

-

-/* TPI Integration ITM Data Register Definitions (FIFO1) */

-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */

-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

-

-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */

-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

-

-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */

-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

-

-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */

-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

-

-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */

-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

-

-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */

-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

-

-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */

-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */

-

-/* TPI ITATBCTR0 Register Definitions */

-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */

-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */

-

-/* TPI Integration Mode Control Register Definitions */

-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */

-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */

-

-/* TPI DEVID Register Definitions */

-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */

-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

-

-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */

-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

-

-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */

-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

-

-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */

-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

-

-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */

-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

-

-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */

-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */

-

-/* TPI DEVTYPE Register Definitions */

-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */

-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

-

-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */

-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */

-

-/*@}*/ /* end of group CMSIS_TPI */

-

-

-#if (__MPU_PRESENT == 1U)

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

-  \brief    Type definitions for the Memory Protection Unit (MPU)

-  @{

- */

-

-/**

-  \brief  Structure type to access the Memory Protection Unit (MPU).

- */

-typedef struct

-{

-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */

-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */

-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */

-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */

-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */

-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */

-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */

-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

-} MPU_Type;

-

-/* MPU Type Register Definitions */

-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */

-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

-

-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */

-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

-

-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */

-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */

-

-/* MPU Control Register Definitions */

-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */

-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

-

-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */

-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

-

-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */

-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */

-

-/* MPU Region Number Register Definitions */

-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */

-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */

-

-/* MPU Region Base Address Register Definitions */

-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */

-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

-

-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */

-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

-

-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */

-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */

-

-/* MPU Region Attribute and Size Register Definitions */

-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */

-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

-

-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */

-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

-

-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */

-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

-

-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */

-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

-

-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */

-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

-

-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */

-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

-

-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */

-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

-

-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */

-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

-

-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */

-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

-

-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */

-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */

-

-/*@} end of group CMSIS_MPU */

-#endif

-

-

-/**

-  \ingroup  CMSIS_core_register

-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

-  \brief    Type definitions for the Core Debug Registers

-  @{

- */

-

-/**

-  \brief  Structure type to access the Core Debug Register (CoreDebug).

- */

-typedef struct

-{

-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */

-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */

-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */

-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

-} CoreDebug_Type;

-

-/* Debug Halting Control and Status Register Definitions */

-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */

-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

-

-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */

-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

-

-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

-

-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */

-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

-

-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */

-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

-

-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */

-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

-

-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */

-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

-

-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

-

-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */

-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

-

-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */

-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

-

-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */

-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

-

-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */

-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

-

-/* Debug Core Register Selector Register Definitions */

-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */

-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

-

-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */

-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */

-

-/* Debug Exception and Monitor Control Register Definitions */

-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */

-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

-

-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */

-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

-

-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */

-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

-

-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */

-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

-

-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */

-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

-

-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */

-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

-

-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */

-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

-

-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */

-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

-

-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */

-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

-

-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */

-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

-

-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */

-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

-

-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */

-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

-

-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */

-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */

-

-/*@} end of group CMSIS_CoreDebug */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_bitfield     Core register bit field macros

-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

-  @{

- */

-

-/**

-  \brief   Mask and shift a bit field value for use in a register bit range.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of the bit field.

-  \return           Masked and shifted value.

-*/

-#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)

-

-/**

-  \brief     Mask and shift a register value to extract a bit filed value.

-  \param[in] field  Name of the register bit field.

-  \param[in] value  Value of register.

-  \return           Masked and shifted bit field value.

-*/

-#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)

-

-/*@} end of group CMSIS_core_bitfield */

-

-

-/**

-  \ingroup    CMSIS_core_register

-  \defgroup   CMSIS_core_base     Core Definitions

-  \brief      Definitions for base addresses, unions, and structures.

-  @{

- */

-

-/* Memory mapping of Cortex-M3 Hardware */

-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */

-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */

-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */

-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */

-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */

-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */

-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */

-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

-

-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */

-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */

-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */

-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */

-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */

-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */

-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */

-

-#if (__MPU_PRESENT == 1U)

-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */

-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */

-#endif

-

-/*@} */

-

-

-

-/*******************************************************************************

- *                Hardware Abstraction Layer

-  Core Function Interface contains:

-  - Core NVIC Functions

-  - Core SysTick Functions

-  - Core Debug Functions

-  - Core Register Access Functions

- ******************************************************************************/

-/**

-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

-*/

-

-

-

-/* ##########################   NVIC functions  #################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions

-  \brief    Functions that manage interrupts and exceptions via the NVIC.

-  @{

- */

-

-/**

-  \brief   Set Priority Grouping

-  \details Sets the priority grouping field using the required unlock sequence.

-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

-           Only values from 0..7 are used.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]      PriorityGroup  Priority grouping field.

- */

-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

-{

-  uint32_t reg_value;

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

-

-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */

-  reg_value  =  (reg_value                                   |

-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |

-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */

-  SCB->AIRCR =  reg_value;

-}

-

-

-/**

-  \brief   Get Priority Grouping

-  \details Reads the priority grouping field from the NVIC Interrupt Controller.

-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

- */

-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

-{

-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));

-}

-

-

-/**

-  \brief   Enable External Interrupt

-  \details Enables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Disable External Interrupt

-  \details Disables a device-specific interrupt in the NVIC interrupt controller.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Pending Interrupt

-  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not pending.

-  \return             1  Interrupt status is pending.

- */

-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Pending Interrupt

-  \details Sets the pending bit of an external interrupt.

-  \param [in]      IRQn  Interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Clear Pending Interrupt

-  \details Clears the pending bit of an external interrupt.

-  \param [in]      IRQn  External interrupt number. Value cannot be negative.

- */

-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

-{

-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));

-}

-

-

-/**

-  \brief   Get Active Interrupt

-  \details Reads the active register in NVIC and returns the active bit.

-  \param [in]      IRQn  Interrupt number.

-  \return             0  Interrupt status is not active.

-  \return             1  Interrupt status is active.

- */

-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

-{

-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));

-}

-

-

-/**

-  \brief   Set Interrupt Priority

-  \details Sets the priority of an interrupt.

-  \note    The priority cannot be set for every core interrupt.

-  \param [in]      IRQn  Interrupt number.

-  \param [in]  priority  Priority to set.

- */

-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

-{

-  if ((int32_t)(IRQn) < 0)

-  {

-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-  else

-  {

-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);

-  }

-}

-

-

-/**

-  \brief   Get Interrupt Priority

-  \details Reads the priority of an interrupt.

-           The interrupt number can be positive to specify an external (device specific) interrupt,

-           or negative to specify an internal (core) interrupt.

-  \param [in]   IRQn  Interrupt number.

-  \return             Interrupt Priority.

-                      Value is aligned automatically to the implemented priority bits of the microcontroller.

- */

-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

-{

-

-  if ((int32_t)(IRQn) < 0)

-  {

-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));

-  }

-  else

-  {

-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));

-  }

-}

-

-

-/**

-  \brief   Encode Priority

-  \details Encodes the priority for an interrupt with the given priority group,

-           preemptive priority value, and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

-  \param [in]     PriorityGroup  Used priority group.

-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

-  \param [in]       SubPriority  Subpriority value (starting from 0).

-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

- */

-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  return (

-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |

-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))

-         );

-}

-

-

-/**

-  \brief   Decode Priority

-  \details Decodes an interrupt priority value with a given priority group to

-           preemptive priority value and subpriority value.

-           In case of a conflict between priority grouping and available

-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

-  \param [in]     PriorityGroup  Used priority group.

-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

-  \param [out]     pSubPriority  Subpriority value (starting from 0).

- */

-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)

-{

-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */

-  uint32_t PreemptPriorityBits;

-  uint32_t SubPriorityBits;

-

-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);

-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

-

-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);

-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);

-}

-

-

-/**

-  \brief   System Reset

-  \details Initiates a system reset request to reset the MCU.

- */

-__STATIC_INLINE void NVIC_SystemReset(void)

-{

-  __DSB();                                                          /* Ensure all outstanding memory accesses included

-                                                                       buffered write are completed before reset */

-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |

-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */

-  __DSB();                                                          /* Ensure completion of memory access */

-

-  for(;;)                                                           /* wait until reset */

-  {

-    __NOP();

-  }

-}

-

-/*@} end of CMSIS_Core_NVICFunctions */

-

-

-

-/* ##################################    SysTick function  ############################################ */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

-  \brief    Functions that configure the System.

-  @{

- */

-

-#if (__Vendor_SysTickConfig == 0U)

-

-/**

-  \brief   System Tick Configuration

-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.

-           Counter is in free running mode to generate periodic interrupts.

-  \param [in]  ticks  Number of ticks between two interrupts.

-  \return          0  Function succeeded.

-  \return          1  Function failed.

-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

-           must contain a vendor-specific implementation of this function.

- */

-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

-{

-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)

-  {

-    return (1UL);                                                   /* Reload value impossible */

-  }

-

-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */

-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */

-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */

-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

-                   SysTick_CTRL_TICKINT_Msk   |

-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */

-  return (0UL);                                                     /* Function successful */

-}

-

-#endif

-

-/*@} end of CMSIS_Core_SysTickFunctions */

-

-

-

-/* ##################################### Debug In/Output function ########################################### */

-/**

-  \ingroup  CMSIS_Core_FunctionInterface

-  \defgroup CMSIS_core_DebugFunctions ITM Functions

-  \brief    Functions that access the ITM debug interface.

-  @{

- */

-

-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */

-#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

-

-

-/**

-  \brief   ITM Send Character

-  \details Transmits a character via the ITM channel 0, and

-           \li Just returns when no debugger is connected that has booked the output.

-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

-  \param [in]     ch  Character to transmit.

-  \returns            Character to transmit.

- */

-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

-{

-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */

-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */

-  {

-    while (ITM->PORT[0U].u32 == 0UL)

-    {

-      __NOP();

-    }

-    ITM->PORT[0U].u8 = (uint8_t)ch;

-  }

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Receive Character

-  \details Inputs a character via the external variable \ref ITM_RxBuffer.

-  \return             Received character.

-  \return         -1  No character pending.

- */

-__STATIC_INLINE int32_t ITM_ReceiveChar (void)

-{

-  int32_t ch = -1;                           /* no character available */

-

-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)

-  {

-    ch = ITM_RxBuffer;

-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

-  }

-

-  return (ch);

-}

-

-

-/**

-  \brief   ITM Check Character

-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

-  \return          0  No character available.

-  \return          1  Character available.

- */

-__STATIC_INLINE int32_t ITM_CheckChar (void)

-{

-

-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)

-  {

-    return (0);                              /* no character available */

-  }

-  else

-  {

-    return (1);                              /*    character available */

-  }

-}

-

-/*@} end of CMSIS_core_DebugFunctions */

-

-

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_SC300_H_DEPENDANT */

-

-#endif /* __CMSIS_GENERIC */

+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/mpu_armv7.h b/os/common/ext/ARM/CMSIS/Core/Include/mpu_armv7.h
new file mode 100644
index 000000000..0f11cf8ad
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/mpu_armv7.h
@@ -0,0 +1,184 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for ARMv7 MPU
+ * @version  V5.0.2
+ * @date     09. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0u 
+#define ARM_MPU_AP_PRIV 1u
+#define ARM_MPU_AP_URO  2u
+#define ARM_MPU_AP_FULL 3u
+#define ARM_MPU_AP_PRO  5u
+#define ARM_MPU_AP_RO   6u
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
+
+/**
+* MPU Region Attribut and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ((DisableExec      << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
+  ((AccessPermission << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
+  ((TypeExtField     << MPU_RASR_TEX_Pos)    & MPU_RASR_TEX_Msk)    | \
+  ((IsShareable      << MPU_RASR_S_Pos)      & MPU_RASR_S_Msk)      | \
+  ((IsCacheable      << MPU_RASR_C_Pos)      & MPU_RASR_C_Msk)      | \
+  ((IsBufferable     << MPU_RASR_B_Pos)      & MPU_RASR_B_Msk)      | \
+  ((SubRegionDisable << MPU_RASR_SRD_Pos)    & MPU_RASR_SRD_Msk)    | \
+  ((Size             << MPU_RASR_SIZE_Pos)   & MPU_RASR_SIZE_Msk)   | \
+  ((1UL              << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct _ARM_MPU_Region_t {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+/* CHIBIOS FIX */
+//__STATIC_INLINE void ARM_MPU_Disable()
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0u;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0u; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
+}
+
+#endif
diff --git a/os/common/ext/ARM/CMSIS/Core/Include/tz_context.h b/os/common/ext/ARM/CMSIS/Core/Include/tz_context.h
new file mode 100644
index 000000000..0784d26ca
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core/Include/tz_context.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date:        21. September 2016
+ * $Revision:    V1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+  
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armcc.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armcc.h
new file mode 100644
index 000000000..8b3df6bff
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armcc.h
@@ -0,0 +1,791 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.00
+ * @date     22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))
+  #define __ARM_ARCH_7A__           1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif                                          
+#ifndef   __INLINE                              
+  #define __INLINE                               __inline
+#endif                                          
+#ifndef   __STATIC_INLINE                       
+  #define __STATIC_INLINE                        static __inline
+#endif                                                                                   
+#ifndef   __NO_RETURN                           
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif                                          
+#ifndef   __USED                                
+  #define __USED                                 __attribute__((used))
+#endif                                          
+#ifndef   __WEAK                                
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif                                          
+#ifndef   __PACKED                              
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR (Floating Point Status/Control)
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR (Floating Point Status/Control)
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                     __breakpoint(value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+/** \brief  Get CPSR (Current Program Status Register)
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+
+/** \brief  Set CPSR (Current Program Status Register)
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  __regCPSR = cpsr;
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void) {
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
+  MOV  r1, lr
+  MSR  CPSR_C, r0
+  BX   r1
+}
+
+/** \brief  Set Stack Pointer 
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
+{
+  MOV  sp, r0
+  BX   lr
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
+{
+  ARM
+  PRESERVE8
+
+  BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     SP, R0
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Get FPEXC (Floating Point Exception Control Register)
+    \return               Floating Point Exception Control Register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC (Floating Point Exception Control Register)
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+}
+
+/** \brief  Get ACTLR (Auxiliary Control Register)
+    \return               Auxiliary Control Register value
+ */
+__STATIC_INLINE uint32_t __get_ACTLR(void)
+{
+  register uint32_t __regACTLR         __ASM("cp15:0:c1:c0:1");
+  return __regACTLR;
+}
+
+/** \brief  Set ACTLR (Auxiliary Control Register)
+    \param [in]    actlr  Auxiliary Control value to set
+ */
+__STATIC_INLINE void __set_ACTLR(uint32_t actlr)
+{
+  register uint32_t __regACTLR         __ASM("cp15:0:c1:c0:1");
+  __regACTLR = actlr;
+}
+
+/** \brief  Get CPACR (Coprocessor Access Control Register)
+    \return               Coprocessor Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CPACR(void)
+{
+  register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+  return __regCPACR;
+}
+
+/** \brief  Set CPACR (Coprocessor Access Control Register)
+    \param [in]    cpacr  Coprocessor Access Control value to set
+ */
+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+  register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+  __regCPACR = cpacr;
+}
+
+/** \brief  Get DFSR (Data Fault Status Register)
+    \return               Data Fault Status Register value
+ */
+__STATIC_INLINE uint32_t __get_DFSR(void)
+{
+  register uint32_t __regDFSR         __ASM("cp15:0:c5:c0:0");
+  return __regDFSR;
+}
+
+/** \brief  Set DFSR (Data Fault Status Register)
+    \param [in]    dfsr  Data Fault Status value to set
+ */
+__STATIC_INLINE void __set_DFSR(uint32_t dfsr)
+{
+  register uint32_t __regDFSR         __ASM("cp15:0:c5:c0:0");
+  __regDFSR = dfsr;
+}
+
+/** \brief  Get IFSR (Instruction Fault Status Register)
+    \return               Instruction Fault Status Register value
+ */
+__STATIC_INLINE uint32_t __get_IFSR(void)
+{
+  register uint32_t __regIFSR         __ASM("cp15:0:c5:c0:1");
+  return __regIFSR;
+}
+
+/** \brief  Set IFSR (Instruction Fault Status Register)
+    \param [in]    ifsr  Instruction Fault Status value to set
+ */
+__STATIC_INLINE void __set_IFSR(uint32_t ifsr)
+{
+  register uint32_t __regIFSR         __ASM("cp15:0:c5:c0:1");
+  __regIFSR = ifsr;
+}
+
+/** \brief  Get ISR (Interrupt Status Register)
+    \return               Interrupt Status Register value
+ */
+__STATIC_INLINE uint32_t __get_ISR(void)
+{
+  register uint32_t __regISR         __ASM("cp15:0:c5:c0:1");
+  return __regISR;
+}
+
+/** \brief  Get CBAR (Configuration Base Address Register)
+    \return               Configuration Base Address Register value
+ */
+__STATIC_INLINE uint32_t __get_CBAR() {
+  register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
+  return(__regCBAR);
+}
+
+/** \brief  Get TTBR0 (Translation Table Base Register 0)
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_INLINE uint32_t __get_TTBR0() {
+  register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+  return(__regTTBR0);
+}
+
+/** \brief  Set TTBR0 Translation Table Base Register 0
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+  register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+  __regTTBR0 = ttbr0;
+}
+
+/** \brief  Get DACR (Domain Access Control Register)
+    \return               Domain Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_DACR() {
+  register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+  return(__regDACR);
+}
+
+/** \brief  Set DACR (Domain Access Control Register)
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+  register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+  __regDACR = dacr;
+}
+
+/** \brief  Set SCTLR (System Control Register).
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+  register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+  __regSCTLR = sctlr;
+}
+
+/** \brief  Get SCTLR (System Control Register).
+    \return               System Control Register value
+ */
+__STATIC_INLINE uint32_t __get_SCTLR() {
+  register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+  return(__regSCTLR);
+}
+
+/** \brief  Set ACTRL (Auxiliary Control Register)
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_INLINE void __set_ACTRL(uint32_t actrl)
+{
+  register uint32_t __regACTRL         __ASM("cp15:0:c1:c0:1");
+  __regACTRL = actrl;
+}
+
+/** \brief  Get ACTRL (Auxiliary Control Register)
+    \return               Auxiliary Control Register value
+ */
+__STATIC_INLINE uint32_t __get_ACTRL(void)
+{
+  register uint32_t __regACTRL         __ASM("cp15:0:c1:c0:1");
+  return(__regACTRL);
+}
+
+/** \brief  Get MPIDR (Multiprocessor Affinity Register)
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_INLINE uint32_t __get_MPIDR(void)
+{
+  register uint32_t __regMPIDR         __ASM("cp15:0:c0:c0:5");
+  return(__regMPIDR);
+}
+
+ /** \brief  Get VBAR (Vector Base Address Register)
+    \return               Vector Base Address Register
+ */
+__STATIC_INLINE uint32_t __get_VBAR(void)
+{
+  register uint32_t __regVBAR         __ASM("cp15:0:c12:c0:0");
+  return(__regVBAR);
+}
+
+/** \brief  Set VBAR (Vector Base Address Register)
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_INLINE void __set_VBAR(uint32_t vbar)
+{
+  register uint32_t __regVBAR          __ASM("cp15:0:c12:c0:0");
+  __regVBAR = vbar;
+}
+
+/** \brief  Set CNTFRQ (Counter Frequency Register)
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_INLINE void __set_CNTFRQ(uint32_t value) {
+  register uint32_t __regCNTFRQ         __ASM("cp15:0:c14:c0:0");
+  __regCNTFRQ = value;
+}
+
+/** \brief  Set CNTP_TVAL (PL1 Physical TimerValue Register)
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
+  register uint32_t __regCNTP_TVAL         __ASM("cp15:0:c14:c2:0");
+  __regCNTP_TVAL = value;
+}
+
+/** \brief  Get CNTP_TVAL (PL1 Physical TimerValue Register)
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
+  register uint32_t __regCNTP_TVAL         __ASM("cp15:0:c14:c2:0");
+  return(__regCNTP_TVAL);
+}
+
+/** \brief  Set CNTP_CTL (PL1 Physical Timer Control Register)
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
+  register uint32_t __regCNTP_CTL          __ASM("cp15:0:c14:c2:1");
+  __regCNTP_CTL = value;
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_CTL() {
+  register uint32_t __regCNTP_CTL          __ASM("cp15:0:c14:c2:1");
+  return(__regCNTP_CTL);
+}
+
+/** \brief  Set TLBIALL (Invalidate Entire Unified TLB)
+ */
+__STATIC_INLINE void __set_TLBIALL(uint32_t value) {
+  register uint32_t __TLBIALL              __ASM("cp15:0:c8:c7:0");
+  __TLBIALL = value;
+}
+
+/** \brief  Set BPIALL (Branch Predictor Invalidate All)
+* \param [in] value    BPIALL value to set
+*/
+__STATIC_INLINE void __set_BPIALL(uint32_t value) {
+  register uint32_t __BPIALL            __ASM("cp15:0:c7:c5:6");
+  __BPIALL = value;
+}
+
+/** \brief  Set ICIALLU (Instruction Cache Invalidate All)
+ * \param [in] value    ICIALLU value to set
+ */
+__STATIC_INLINE void __set_ICIALLU(uint32_t value) {
+  register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
+  __ICIALLU = value;
+}
+
+/** \brief  Set DCCMVAC (Clean data or unified cache line by MVA to PoC)
+ * \param [in] value    DCCMVAC value to set
+ */
+__STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
+  register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
+  __DCCMVAC = value;
+}
+
+/** \brief  Set DCIMVAC (Invalidate data or unified cache line by MVA to PoC)
+ * \param [in] value    DCIMVAC value to set
+ */
+__STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
+  register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
+  __DCIMVAC = value;
+}
+
+/** \brief  Set DCCIMVAC (Clean and Invalidate data or unified cache line by MVA to PoC)
+ * \param [in] value    DCCIMVAC value to set
+ */
+__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
+  register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
+  __DCCIMVAC = value;
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+ * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+ */
+__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
+        ARM
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
+        ANDS    R3, R6, #0x07000000        // Extract coherency level
+        MOV     R3, R3, LSR #23            // Total cache levels << 1
+        BEQ     Finished                   // If 0, no need to clean
+
+        MOV     R10, #0                    // R10 holds current cache level << 1
+Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
+        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
+        AND     R1, R1, #7                 // Isolate those lower 3 bits
+        CMP     R1, #2
+        BLT     Skip                       // No cache or only instruction cache at this level
+
+        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
+        ISB                                // ISB to sync the change to the CacheSizeID reg
+        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
+        AND     R2, R1, #7                 // Extract the line length field
+        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
+        CLZ     R5, R4                     // R5 is the bit position of the way size increment
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
+
+Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
+
+Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
+        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
+        B       cont
+Dccsw   CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
+        B       cont
+Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
+cont    SUBS    R9, R9, #1                 // Decrement the Way number
+        BGE     Loop3
+        SUBS    R7, R7, #1                 // Decrement the Set number
+        BGE     Loop2
+Skip    ADD     R10, R10, #2               // Increment the cache number
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished
+        DSB
+        POP    {R4-R11}
+        BX     lr
+}
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE __ASM void __FPU_Enable(void) {
+        ARM
+
+        //Permit access to VFP/NEON, registers by modifying CPACR
+        MRC     p15,0,R1,c1,c0,2
+        ORR     R1,R1,#0x00F00000
+        MCR     p15,0,R1,c1,c0,2
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+        ISB
+
+        //Enable VFP/NEON
+        VMRS    R1,FPEXC
+        ORR     R1,R1,#0x40000000
+        VMSR    FPEXC,R1
+
+        //Initialise VFP/NEON registers to 0
+        MOV     R2,#0
+  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
+        //Initialise D16 registers to 0
+        VMOV    D0, R2,R2
+        VMOV    D1, R2,R2
+        VMOV    D2, R2,R2
+        VMOV    D3, R2,R2
+        VMOV    D4, R2,R2
+        VMOV    D5, R2,R2
+        VMOV    D6, R2,R2
+        VMOV    D7, R2,R2
+        VMOV    D8, R2,R2
+        VMOV    D9, R2,R2
+        VMOV    D10,R2,R2
+        VMOV    D11,R2,R2
+        VMOV    D12,R2,R2
+        VMOV    D13,R2,R2
+        VMOV    D14,R2,R2
+        VMOV    D15,R2,R2
+  ENDIF
+  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+        //Initialise D32 registers to 0
+        VMOV    D16,R2,R2
+        VMOV    D17,R2,R2
+        VMOV    D18,R2,R2
+        VMOV    D19,R2,R2
+        VMOV    D20,R2,R2
+        VMOV    D21,R2,R2
+        VMOV    D22,R2,R2
+        VMOV    D23,R2,R2
+        VMOV    D24,R2,R2
+        VMOV    D25,R2,R2
+        VMOV    D26,R2,R2
+        VMOV    D27,R2,R2
+        VMOV    D28,R2,R2
+        VMOV    D29,R2,R2
+        VMOV    D30,R2,R2
+        VMOV    D31,R2,R2
+  ENDIF
+
+        //Initialise FPSCR to a known state
+        VMRS    R2,FPSCR
+        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        AND     R2,R2,R3
+        VMSR    FPSCR,R2
+
+        BX      LR
+}
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armclang.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armclang.h
new file mode 100644
index 000000000..3d6667026
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armclang.h
@@ -0,0 +1,821 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.00
+ * @date     05. Apr 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif                                          
+#ifndef   __INLINE                              
+  #define __INLINE                               __inline
+#endif                                          
+#ifndef   __STATIC_INLINE                       
+  #define __STATIC_INLINE                        static __inline
+#endif                                                                                    
+#ifndef   __NO_RETURN                           
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif                                          
+#ifndef   __USED                                
+  #define __USED                                 __attribute__((used))
+#endif                                          
+#ifndef   __WEAK                                
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif                                        
+#ifndef   __PACKED                            
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  uint32_t result;
+  __ASM volatile("MRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+  (void)fpscr;
+#endif
+}
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __builtin_arm_wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __builtin_arm_wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __builtin_arm_sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __builtin_bswap32
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  int32_t result;
+  __ASM volatile("revsh %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT                            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void) {
+	return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE void __set_mode(uint32_t mode) {
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  __ASM volatile(
+    ".preserve8         \n"
+    "BIC     r0, r0, #7 \n" // ensure stack is 8-byte aligned
+    "MRS     r1, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, r0     \n"
+    "MSR     cpsr_c, r1 \n" // no effect in USR mode
+    "ISB"
+   );
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("MRS %0, fpexc" : "=r" (result) );
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("MSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/** \brief  Get ACTLR
+    \return               Auxiliary Control register value
+ */
+__STATIC_INLINE uint32_t __get_ACTLR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, actlr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set ACTLR
+    \param [in]    actlr  Auxiliary Control value to set
+ */
+__STATIC_INLINE void __set_ACTLR(uint32_t actlr)
+{
+  __ASM volatile ("MSR fpexc, %0" : : "r" (actlr) : "memory");
+}
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_INLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Access Control value to set
+ */
+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory");
+}
+
+/** \brief  Get DFSR
+    \return               Data Fault Status Register value
+ */
+__STATIC_INLINE uint32_t __get_DFSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c5, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set DFSR
+    \param [in]    dfsr  Data Fault Status value to set
+ */
+__STATIC_INLINE void __set_DFSR(uint32_t dfsr)
+{
+  __ASM volatile("MCR p15, 0, %0, c5, c0, 0" : : "r"(dfsr) : "memory");
+}
+
+/** \brief  Get IFSR
+    \return               Instruction Fault Status Register value
+ */
+__STATIC_INLINE uint32_t __get_IFSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c5, c0, 1" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set IFSR
+    \param [in]    ifsr  Instruction Fault Status value to set
+ */
+__STATIC_INLINE void __set_IFSR(uint32_t ifsr)
+{
+  __ASM volatile("MCR p15, 0, %0, c5, c0, 1" : : "r"(ifsr) : "memory");
+}
+
+/** \brief  Get ISR
+    \return               Interrupt Status Register value
+ */
+__STATIC_INLINE uint32_t __get_ISR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c12, c1, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_INLINE uint32_t __get_CBAR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_INLINE uint32_t __get_TTBR0() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+  __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory");
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_DACR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+  __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory");
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory");
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_INLINE uint32_t __get_SCTLR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_INLINE void __set_ACTRL(uint32_t actrl)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory");
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_INLINE uint32_t __get_ACTRL(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_INLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result));
+  return result;
+}
+
+ /** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_INLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_INLINE void __set_VBAR(uint32_t vbar)
+{
+  __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory");
+}
+
+/** \brief  Set CNTFRQ
+
+  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_INLINE void __set_CNTFRQ(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c0, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_CTL() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c14, c2, 1" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_INLINE void __set_TLBIALL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_INLINE void __set_BPIALL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory");
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_INLINE void __set_ICIALLU(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+ */
+__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
+  __ASM volatile(
+    "        PUSH    {R4-R11}                   \n"
+
+    "        MRC     p15, 1, R6, c0, c0, 1      \n" // Read CLIDR
+    "        ANDS    R3, R6, #0x07000000        \n" // Extract coherency level
+    "        MOV     R3, R3, LSR #23            \n" // Total cache levels << 1
+    "        BEQ     Finished                   \n" // If 0, no need to clean
+
+    "        MOV     R10, #0                    \n" // R10 holds current cache level << 1
+    "Loop1:  ADD     R2, R10, R10, LSR #1       \n" // R2 holds cache "Set" position
+    "        MOV     R1, R6, LSR R2             \n" // Bottom 3 bits are the Cache-type for this level
+    "        AND     R1, R1, #7                 \n" // Isolate those lower 3 bits
+    "        CMP     R1, #2                     \n"
+    "        BLT     Skip                       \n" // No cache or only instruction cache at this level
+
+    "        MCR     p15, 2, R10, c0, c0, 0     \n" // Write the Cache Size selection register
+    "        ISB                                \n" // ISB to sync the change to the CacheSizeID reg
+    "        MRC     p15, 1, R1, c0, c0, 0      \n" // Reads current Cache Size ID register
+    "        AND     R2, R1, #7                 \n" // Extract the line length field
+    "        ADD     R2, R2, #4                 \n" // Add 4 for the line length offset (log2 16 bytes)
+    "        LDR     R4, =0x3FF                 \n"
+    "        ANDS    R4, R4, R1, LSR #3         \n" // R4 is the max number on the way size (right aligned)
+    "        CLZ     R5, R4                     \n" // R5 is the bit position of the way size increment
+    "        LDR     R7, =0x7FFF                \n"
+    "        ANDS    R7, R7, R1, LSR #13        \n" // R7 is the max number of the index size (right aligned)
+
+    "Loop2:  MOV     R9, R4                     \n" // R9 working copy of the max way size (right aligned)
+
+    "Loop3:  ORR     R11, R10, R9, LSL R5       \n" // Factor in the Way number and cache number into R11
+    "        ORR     R11, R11, R7, LSL R2       \n" // Factor in the Set number
+    "        CMP     R0, #0                     \n"
+    "        BNE     Dccsw                      \n"
+    "        MCR     p15, 0, R11, c7, c6, 2     \n" // DCISW. Invalidate by Set/Way
+    "        B       cont                       \n"
+    "Dccsw:  CMP     R0, #1                     \n"
+    "        BNE     Dccisw                     \n"
+    "        MCR     p15, 0, R11, c7, c10, 2    \n" // DCCSW. Clean by Set/Way
+    "        B       cont                       \n"
+    "Dccisw: MCR     p15, 0, R11, c7, c14, 2    \n" // DCCISW. Clean and Invalidate by Set/Way
+    "cont:   SUBS    R9, R9, #1                 \n" // Decrement the Way number
+    "        BGE     Loop3                      \n"
+    "        SUBS    R7, R7, #1                 \n" // Decrement the Set number
+    "        BGE     Loop2                      \n"
+    "Skip:   ADD     R10, R10, #2               \n" // Increment the cache number
+    "        CMP     R3, R10                    \n"
+    "        BGT     Loop1                      \n"
+
+    "Finished:                                  \n"
+    "        DSB                                \n"
+    "        POP    {R4-R11}                      "
+  );
+}
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void) {
+  __ASM volatile(
+	    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+	    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+	    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+	    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+#if 0 // TODO: Initialize FPU registers according to available register count
+    ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n"
+	    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+    ".endif                            \n"
+
+    ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n"
+	    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+    ".endif                            \n"
+#endif
+	    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_compiler.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_compiler.h
new file mode 100644
index 000000000..9fa0e0ea4
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_compiler.h
@@ -0,0 +1,211 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.00
+ * @date     22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+
+  #include <cmsis_iar.h>
+
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __noreturn
+  #endif
+  #ifndef   __USED
+    #define __USED                    __root
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __weak
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    __packed struct T_UINT32 { uint32_t v; };
+      #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __packed
+  #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __attribute__((aligned(x)))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __attribute__((packed))
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __packed__
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                     _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __weak
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  @packed
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h
new file mode 100644
index 000000000..4e95b82fb
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h
@@ -0,0 +1,955 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.00
+ * @date     06. Jul 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return Floating Point Status/Control register value
+*/
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    return __builtin_arm_get_fpscr();
+  #else
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+  #endif
+  #else
+    return(0U);
+  #endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in] fpscr  Floating Point Status/Control value to set
+*/
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    __builtin_arm_set_fpscr(fpscr);
+  #else
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+  #endif
+  #else
+    (void)fpscr;
+  #endif
+}
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+/**
+  \brief   Send Event
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void) {
+    return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE void __set_mode(uint32_t mode) {
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  __ASM volatile(
+    ".preserve8         \n"
+    "BIC     r0, r0, #7 \n" // ensure stack is 8-byte aligned
+    "MRS     r1, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, r0     \n"
+    "MSR     cpsr_c, r1 \n" // no effect in USR mode
+    "ISB"
+   );
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("MRS %0, fpexc" : "=r" (result) );
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("MSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/** \brief  Get ACTLR
+    \return               Auxiliary Control register value
+ */
+__STATIC_INLINE uint32_t __get_ACTLR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, actlr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set ACTLR
+    \param [in]    actlr  Auxiliary Control value to set
+ */
+__STATIC_INLINE void __set_ACTLR(uint32_t actlr)
+{
+  __ASM volatile ("MSR fpexc, %0" : : "r" (actlr) : "memory");
+}
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_INLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Access Control value to set
+ */
+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory");
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_INLINE uint32_t __get_CBAR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_INLINE uint32_t __get_TTBR0() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+  __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory");
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_DACR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+  __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory");
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory");
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_INLINE uint32_t __get_SCTLR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_INLINE void __set_ACTRL(uint32_t actrl)
+{
+  __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory");
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_INLINE uint32_t __get_ACTRL(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_INLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result));
+  return result;
+}
+
+ /** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_INLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_INLINE void __set_VBAR(uint32_t vbar)
+{
+  __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory");
+}
+
+/** \brief  Set CNTFRQ
+
+  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_INLINE void __set_CNTFRQ(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c0, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_INLINE uint32_t __get_CNTP_CTL() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 0, %0, c14, c2, 1" : "=r"(result));
+  return result;
+}
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_INLINE void __set_TLBIALL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_INLINE void __set_BPIALL(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory");
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_INLINE void __set_ICIALLU(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory");
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
+  __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory");
+}
+
+
+/** \brief  Set CCSIDR
+ */
+__STATIC_INLINE void __set_CCSIDR(uint32_t value) {
+  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+}
+
+/** \brief  Get CCSIDR
+    \return CCSIDR Register value
+ */
+__STATIC_INLINE uint32_t __get_CCSIDR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result));
+  return result;
+}
+
+/** \brief  Get CLIDR
+    \return CLIDR Register value
+ */
+__STATIC_INLINE uint32_t __get_CLIDR() {
+  uint32_t result;
+  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result));
+  return result;
+}
+
+__STATIC_INLINE int32_t log2_up(uint32_t n)
+{
+  int32_t log = -1;
+  uint32_t t = n;
+  while(t)
+  {
+    log++; t >>=1;
+  }
+  /* if n not power of 2 -> round up*/
+  if ( n & (n - 1) ) log++;
+  return log;
+}
+
+__STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
+{
+  register volatile uint32_t Dummy;
+  register volatile uint32_t ccsidr;
+  uint32_t num_sets;
+  uint32_t num_ways;
+  uint32_t shift_way;
+  uint32_t log2_linesize;
+  uint32_t log2_num_ways;
+
+  Dummy = level << 1;
+  /* set csselr, select ccsidr register */
+  __set_CCSIDR(Dummy);
+  /* get current ccsidr register */
+  ccsidr = __get_CCSIDR();
+  num_sets = ((ccsidr & 0x0FFFE000) >> 13) + 1;
+  num_ways = ((ccsidr & 0x00001FF8) >> 3) + 1;
+  log2_linesize = (ccsidr & 0x00000007) + 2 + 2;
+  log2_num_ways = log2_up(num_ways);
+  shift_way = 32 - log2_num_ways;
+  for(int way = num_ways-1; way >= 0; way--) {
+    for(int set = num_sets-1; set >= 0; set--) {
+      Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way);
+      switch (maint)
+      {
+        case 0:
+          __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(Dummy) : "memory"); // DCISW. Invalidate by Set/Way
+          break;
+
+        case 1:
+          __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(Dummy) : "memory"); // DCCSW. Clean by Set/Way
+          break;
+
+        default:
+          __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(Dummy) : "memory"); // DCCISW. Clean and Invalidate by Set/Way
+          break;
+
+      }
+    }
+  }
+  __DMB();
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+ */
+__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) {
+  register volatile uint32_t clidr;
+  uint32_t cache_type;
+  clidr =  __get_CLIDR();
+  for(uint32_t i = 0; i<7; i++)
+  {
+    cache_type = (clidr >> i*3) & 0x7UL;
+    if ((cache_type >= 2) && (cache_type <= 4))
+    {
+      __L1C_MaintainDCacheSetWay(i, op);
+    }
+  }
+
+}
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void) {
+  __ASM volatile(
+        //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+        //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+        //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
+        //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+#endif
+
+#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
+        //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+  );
+
+  // Initialise FPSCR to a known state
+  // Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+  __set_FPSCR(__get_FPSCR() & 0x00086060u);
+}
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h b/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h
new file mode 100644
index 000000000..a80150298
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h
@@ -0,0 +1,2456 @@
+/**************************************************************************//**
+ * @file     core_ca.h
+ * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
+ * @version  V1.00
+ * @date     22. Feb 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA_H_GENERIC
+#define __CORE_CA_H_GENERIC
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+
+/*  CMSIS CA definitions */
+#define __CA_CMSIS_VERSION_MAIN  (1U)                                      /*!< \brief [31:16] CMSIS-Core(A) main version   */
+#define __CA_CMSIS_VERSION_SUB   (0U)                                      /*!< \brief [15:0]  CMSIS-Core(A) sub version    */
+#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CA_CMSIS_VERSION_SUB          )       /*!< \brief CMSIS-Core(A) version number         */
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA_H_DEPENDANT
+#define __CORE_CA_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ /* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CA_REV
+    #define __CA_REV              0x0000U
+    #warning "__CA_REV not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+    
+  #ifndef __GIC_PRESENT
+    #define __GIC_PRESENT             1U
+    #warning "__GIC_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __TIM_PRESENT
+    #define __TIM_PRESENT             1U
+    #warning "__TIM_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __L2C_PRESENT
+    #define __L2C_PRESENT             0U
+    #warning "__L2C_PRESENT not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< \brief Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< \brief Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< \brief Defines 'write only' permissions */
+#define     __IO    volatile             /*!< \brief Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*!< \brief Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*!< \brief Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
+#define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
+
+ /*******************************************************************************
+  *                 Register Abstraction
+   Core Register contain:
+   - CPSR
+   - CP15 Registers
+   - L2C-310 Cache Controller
+   - Generic Interrupt Controller Distributor
+   - Generic Interrupt Controller Interface
+  ******************************************************************************/
+
+/* Core Register CPSR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:5;                        /*!< \brief bit:  0.. 4  Mode field */
+    uint32_t T:1;                        /*!< \brief bit:      5  Thumb execution state bit */
+    uint32_t F:1;                        /*!< \brief bit:      6  FIQ mask bit */
+    uint32_t I:1;                        /*!< \brief bit:      7  IRQ mask bit */
+    uint32_t A:1;                        /*!< \brief bit:      8  Asynchronous abort mask bit */
+    uint32_t E:1;                        /*!< \brief bit:      9  Endianness execution state bit */
+    uint32_t IT1:6;                      /*!< \brief bit: 10..15  If-Then execution state bits 2-7 */
+    uint32_t GE:4;                       /*!< \brief bit: 16..19  Greater than or Equal flags */
+    RESERVED(0:4, uint32_t)              
+    uint32_t J:1;                        /*!< \brief bit:     24  Jazelle bit */
+    uint32_t IT0:2;                      /*!< \brief bit: 25..26  If-Then execution state bits 0-1 */
+    uint32_t Q:1;                        /*!< \brief bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< \brief bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< \brief bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< \brief bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< \brief bit:     31  Negative condition code flag */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPSR_Type;
+
+
+
+/* CPSR Register Definitions */
+#define CPSR_N_Pos                       31U                                    /*!< \brief CPSR: N Position */
+#define CPSR_N_Msk                       (1UL << CPSR_N_Pos)                    /*!< \brief CPSR: N Mask */
+
+#define CPSR_Z_Pos                       30U                                    /*!< \brief CPSR: Z Position */
+#define CPSR_Z_Msk                       (1UL << CPSR_Z_Pos)                    /*!< \brief CPSR: Z Mask */
+
+#define CPSR_C_Pos                       29U                                    /*!< \brief CPSR: C Position */
+#define CPSR_C_Msk                       (1UL << CPSR_C_Pos)                    /*!< \brief CPSR: C Mask */
+
+#define CPSR_V_Pos                       28U                                    /*!< \brief CPSR: V Position */
+#define CPSR_V_Msk                       (1UL << CPSR_V_Pos)                    /*!< \brief CPSR: V Mask */
+
+#define CPSR_Q_Pos                       27U                                    /*!< \brief CPSR: Q Position */
+#define CPSR_Q_Msk                       (1UL << CPSR_Q_Pos)                    /*!< \brief CPSR: Q Mask */
+
+#define CPSR_IT0_Pos                     25U                                    /*!< \brief CPSR: IT0 Position */
+#define CPSR_IT0_Msk                     (3UL << CPSR_IT0_Pos)                  /*!< \brief CPSR: IT0 Mask */
+
+#define CPSR_J_Pos                       24U                                    /*!< \brief CPSR: J Position */
+#define CPSR_J_Msk                       (1UL << CPSR_J_Pos)                    /*!< \brief CPSR: J Mask */
+
+#define CPSR_GE_Pos                      16U                                    /*!< \brief CPSR: GE Position */
+#define CPSR_GE_Msk                      (0xFUL << CPSR_GE_Pos)                 /*!< \brief CPSR: GE Mask */
+
+#define CPSR_IT1_Pos                     10U                                    /*!< \brief CPSR: IT1 Position */
+#define CPSR_IT1_Msk                     (0x3FUL << CPSR_IT1_Pos)               /*!< \brief CPSR: IT1 Mask */
+
+#define CPSR_E_Pos                       9U                                     /*!< \brief CPSR: E Position */
+#define CPSR_E_Msk                       (1UL << CPSR_E_Pos)                    /*!< \brief CPSR: E Mask */
+
+#define CPSR_A_Pos                       8U                                     /*!< \brief CPSR: A Position */
+#define CPSR_A_Msk                       (1UL << CPSR_A_Pos)                    /*!< \brief CPSR: A Mask */
+
+#define CPSR_I_Pos                       7U                                     /*!< \brief CPSR: I Position */
+#define CPSR_I_Msk                       (1UL << CPSR_I_Pos)                    /*!< \brief CPSR: I Mask */
+
+#define CPSR_F_Pos                       6U                                     /*!< \brief CPSR: F Position */
+#define CPSR_F_Msk                       (1UL << CPSR_F_Pos)                    /*!< \brief CPSR: F Mask */
+
+#define CPSR_T_Pos                       5U                                     /*!< \brief CPSR: T Position */
+#define CPSR_T_Msk                       (1UL << CPSR_T_Pos)                    /*!< \brief CPSR: T Mask */
+
+#define CPSR_M_Pos                       0U                                     /*!< \brief CPSR: M Position */
+#define CPSR_M_Msk                       (0x1FUL << CPSR_M_Pos)                 /*!< \brief CPSR: M Mask */
+
+#define CPSR_M_USR                       0x10U                                  /*!< \brief CPSR: M User mode (PL0) */
+#define CPSR_M_FIQ                       0x11U                                  /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
+#define CPSR_M_IRQ                       0x12U                                  /*!< \brief CPSR: M Interrupt mode (PL1) */
+#define CPSR_M_SVC                       0x13U                                  /*!< \brief CPSR: M Supervisor mode (PL1) */
+#define CPSR_M_MON                       0x16U                                  /*!< \brief CPSR: M Monitor mode (PL1) */
+#define CPSR_M_ABT                       0x17U                                  /*!< \brief CPSR: M Abort mode (PL1) */
+#define CPSR_M_HYP                       0x1AU                                  /*!< \brief CPSR: M Hypervisor mode (PL2) */
+#define CPSR_M_UND                       0x1BU                                  /*!< \brief CPSR: M Undefined mode (PL1) */
+#define CPSR_M_SYS                       0x1FU                                  /*!< \brief CPSR: M System mode (PL1) */
+
+/* CP15 Register SCTLR */
+typedef union
+{
+  struct
+  {
+    uint32_t M:1;                        /*!< \brief bit:     0  MMU enable */
+    uint32_t A:1;                        /*!< \brief bit:     1  Alignment check enable */
+    uint32_t C:1;                        /*!< \brief bit:     2  Cache enable */
+    RESERVED(0:2, uint32_t)              
+    uint32_t CP15BEN:1;                  /*!< \brief bit:     5  CP15 barrier enable */
+    RESERVED(1:1, uint32_t)              
+    uint32_t B:1;                        /*!< \brief bit:     7  Endianness model */
+    RESERVED(2:2, uint32_t)              
+    uint32_t SW:1;                       /*!< \brief bit:    10  SWP and SWPB enable */
+    uint32_t Z:1;                        /*!< \brief bit:    11  Branch prediction enable */
+    uint32_t I:1;                        /*!< \brief bit:    12  Instruction cache enable */
+    uint32_t V:1;                        /*!< \brief bit:    13  Vectors bit */
+    uint32_t RR:1;                       /*!< \brief bit:    14  Round Robin select */
+    RESERVED(3:2, uint32_t)              
+    uint32_t HA:1;                       /*!< \brief bit:    17  Hardware Access flag enable */
+    RESERVED(4:1, uint32_t)              
+    uint32_t WXN:1;                      /*!< \brief bit:    19  Write permission implies XN */
+    uint32_t UWXN:1;                     /*!< \brief bit:    20  Unprivileged write permission implies PL1 XN */
+    uint32_t FI:1;                       /*!< \brief bit:    21  Fast interrupts configuration enable */
+    uint32_t U:1;                        /*!< \brief bit:    22  Alignment model */
+    RESERVED(5:1, uint32_t)              
+    uint32_t VE:1;                       /*!< \brief bit:    24  Interrupt Vectors Enable */
+    uint32_t EE:1;                       /*!< \brief bit:    25  Exception Endianness */
+    RESERVED(6:1, uint32_t)              
+    uint32_t NMFI:1;                     /*!< \brief bit:    27  Non-maskable FIQ (NMFI) support */
+    uint32_t TRE:1;                      /*!< \brief bit:    28  TEX remap enable. */
+    uint32_t AFE:1;                      /*!< \brief bit:    29  Access flag enable */
+    uint32_t TE:1;                       /*!< \brief bit:    30  Thumb Exception enable */
+    RESERVED(7:1, uint32_t)              
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} SCTLR_Type;
+
+#define SCTLR_TE_Pos                     30U                                    /*!< \brief SCTLR: TE Position */
+#define SCTLR_TE_Msk                     (1UL << SCTLR_TE_Pos)                  /*!< \brief SCTLR: TE Mask */
+
+#define SCTLR_AFE_Pos                    29U                                    /*!< \brief SCTLR: AFE Position */
+#define SCTLR_AFE_Msk                    (1UL << SCTLR_AFE_Pos)                 /*!< \brief SCTLR: AFE Mask */
+
+#define SCTLR_TRE_Pos                    28U                                    /*!< \brief SCTLR: TRE Position */
+#define SCTLR_TRE_Msk                    (1UL << SCTLR_TRE_Pos)                 /*!< \brief SCTLR: TRE Mask */
+
+#define SCTLR_NMFI_Pos                   27U                                    /*!< \brief SCTLR: NMFI Position */
+#define SCTLR_NMFI_Msk                   (1UL << SCTLR_NMFI_Pos)                /*!< \brief SCTLR: NMFI Mask */
+
+#define SCTLR_EE_Pos                     25U                                    /*!< \brief SCTLR: EE Position */
+#define SCTLR_EE_Msk                     (1UL << SCTLR_EE_Pos)                  /*!< \brief SCTLR: EE Mask */
+
+#define SCTLR_VE_Pos                     24U                                    /*!< \brief SCTLR: VE Position */
+#define SCTLR_VE_Msk                     (1UL << SCTLR_VE_Pos)                  /*!< \brief SCTLR: VE Mask */
+
+#define SCTLR_U_Pos                      22U                                    /*!< \brief SCTLR: U Position */
+#define SCTLR_U_Msk                      (1UL << SCTLR_U_Pos)                   /*!< \brief SCTLR: U Mask */
+
+#define SCTLR_FI_Pos                     21U                                    /*!< \brief SCTLR: FI Position */
+#define SCTLR_FI_Msk                     (1UL << SCTLR_FI_Pos)                  /*!< \brief SCTLR: FI Mask */
+
+#define SCTLR_UWXN_Pos                   20U                                    /*!< \brief SCTLR: UWXN Position */
+#define SCTLR_UWXN_Msk                   (1UL << SCTLR_UWXN_Pos)                /*!< \brief SCTLR: UWXN Mask */
+
+#define SCTLR_WXN_Pos                    19U                                    /*!< \brief SCTLR: WXN Position */
+#define SCTLR_WXN_Msk                    (1UL << SCTLR_WXN_Pos)                 /*!< \brief SCTLR: WXN Mask */
+
+#define SCTLR_HA_Pos                     17U                                    /*!< \brief SCTLR: HA Position */
+#define SCTLR_HA_Msk                     (1UL << SCTLR_HA_Pos)                  /*!< \brief SCTLR: HA Mask */
+
+#define SCTLR_RR_Pos                     14U                                    /*!< \brief SCTLR: RR Position */
+#define SCTLR_RR_Msk                     (1UL << SCTLR_RR_Pos)                  /*!< \brief SCTLR: RR Mask */
+
+#define SCTLR_V_Pos                      13U                                    /*!< \brief SCTLR: V Position */
+#define SCTLR_V_Msk                      (1UL << SCTLR_V_Pos)                   /*!< \brief SCTLR: V Mask */
+
+#define SCTLR_I_Pos                      12U                                    /*!< \brief SCTLR: I Position */
+#define SCTLR_I_Msk                      (1UL << SCTLR_I_Pos)                   /*!< \brief SCTLR: I Mask */
+
+#define SCTLR_Z_Pos                      11U                                    /*!< \brief SCTLR: Z Position */
+#define SCTLR_Z_Msk                      (1UL << SCTLR_Z_Pos)                   /*!< \brief SCTLR: Z Mask */
+
+#define SCTLR_SW_Pos                     10U                                    /*!< \brief SCTLR: SW Position */
+#define SCTLR_SW_Msk                     (1UL << SCTLR_SW_Pos)                  /*!< \brief SCTLR: SW Mask */
+
+#define SCTLR_B_Pos                      7U                                     /*!< \brief SCTLR: B Position */
+#define SCTLR_B_Msk                      (1UL << SCTLR_B_Pos)                   /*!< \brief SCTLR: B Mask */
+
+#define SCTLR_CP15BEN_Pos                5U                                     /*!< \brief SCTLR: CP15BEN Position */
+#define SCTLR_CP15BEN_Msk                (1UL << SCTLR_CP15BEN_Pos)             /*!< \brief SCTLR: CP15BEN Mask */
+
+#define SCTLR_C_Pos                      2U                                     /*!< \brief SCTLR: C Position */
+#define SCTLR_C_Msk                      (1UL << SCTLR_C_Pos)                   /*!< \brief SCTLR: C Mask */
+
+#define SCTLR_A_Pos                      1U                                     /*!< \brief SCTLR: A Position */
+#define SCTLR_A_Msk                      (1UL << SCTLR_A_Pos)                   /*!< \brief SCTLR: A Mask */
+
+#define SCTLR_M_Pos                      0U                                     /*!< \brief SCTLR: M Position */
+#define SCTLR_M_Msk                      (1UL << SCTLR_M_Pos)                   /*!< \brief SCTLR: M Mask */
+
+/* CP15 Register ACTLR */
+typedef union
+{
+#if __CORTEX_A == 5 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A5 */
+  struct
+  {
+    uint32_t FW:1;                      /*!< \brief bit:      0  Cache and TLB maintenance broadcast */
+    RESERVED(0:5, uint32_t)              
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    uint32_t EXCL:1;                     /*!< \brief bit:     7  Exclusive L1/L2 cache control */
+    RESERVED(1:2, uint32_t)
+    uint32_t DODMBS:1;                   /*!< \brief bit:    10  Disable optimized data memory barrier behavior */
+    uint32_t DWBST:1;                    /*!< \brief bit:    11  AXI data write bursts to Normal memory */
+    uint32_t RADIS:1;                    /*!< \brief bit:    12  L1 Data Cache read-allocate mode disable */
+    uint32_t L1PCTL:2;                   /*!< \brief bit:13..14  L1 Data prefetch control */    
+    uint32_t BP:2;                       /*!< \brief bit:16..15  Branch prediction policy */
+    uint32_t RSDIS:1;                    /*!< \brief bit:    17  Disable return stack operation */
+    uint32_t BTDIS:1;                    /*!< \brief bit:    18  Disable indirect Branch Target Address Cache (BTAC) */
+    RESERVED(3:9, uint32_t)             
+    uint32_t DBDI:1;                     /*!< \brief bit:    28  Disable branch dual issue */
+    RESERVED(7:3, uint32_t)              
+ } b;
+#endif  
+#if __CORTEX_A == 7 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A7 */
+  struct
+  {
+    RESERVED(0:6, uint32_t)              
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    RESERVED(1:3, uint32_t)              
+    uint32_t DODMBS:1;                   /*!< \brief bit:    10  Disable optimized data memory barrier behavior */
+    uint32_t L2RADIS:1;                  /*!< \brief bit:    11  L2 Data Cache read-allocate mode disable */
+    uint32_t L1RADIS:1;                  /*!< \brief bit:    12  L1 Data Cache read-allocate mode disable */
+    uint32_t L1PCTL:2;                   /*!< \brief bit:13..14  L1 Data prefetch control */
+    uint32_t DDVM:1;                     /*!< \brief bit:    15  Disable Distributed Virtual Memory (DVM) transactions */
+    RESERVED(3:12, uint32_t)             
+    uint32_t DDI:1;                      /*!< \brief bit:    28  Disable dual issue */
+    RESERVED(7:3, uint32_t)              
+  } b;
+#endif  
+#if __CORTEX_A == 9 || defined(DOXYGEN)
+  /** \brief Structure used for bit access on Cortex-A9 */
+  struct
+  {
+    uint32_t FW:1;                       /*!< \brief bit:     0  Cache and TLB maintenance broadcast */
+    RESERVED(0:1, uint32_t)
+    uint32_t L1PE:1;                     /*!< \brief bit:     2  Dside prefetch */
+    uint32_t WFLZM:1;                    /*!< \brief bit:     3  Cache and TLB maintenance broadcast */
+    RESERVED(1:2, uint32_t)
+    uint32_t SMP:1;                      /*!< \brief bit:     6  Enables coherent requests to the processor */
+    uint32_t EXCL:1;                     /*!< \brief bit:     7  Exclusive L1/L2 cache control */
+    uint32_t AOW:1;                      /*!< \brief bit:     8  Enable allocation in one cache way only */
+    uint32_t PARITY:1;                   /*!< \brief bit:     9  Support for parity checking, if implemented */
+    RESERVED(7:22, uint32_t)              
+  } b;
+#endif  
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} ACTLR_Type;
+
+#define ACTLR_DDI_Pos                    28U                                     /*!< \brief ACTLR: DDI Position */
+#define ACTLR_DDI_Msk                    (1UL << ACTLR_DDI_Pos)                  /*!< \brief ACTLR: DDI Mask */
+
+#define ACTLR_DBDI_Pos                   28U                                     /*!< \brief ACTLR: DBDI Position */
+#define ACTLR_DBDI_Msk                   (1UL << ACTLR_DBDI_Pos)                 /*!< \brief ACTLR: DBDI Mask */
+
+#define ACTLR_BTDIS_Pos                  18U                                     /*!< \brief ACTLR: BTDIS Position */
+#define ACTLR_BTDIS_Msk                  (1UL << ACTLR_BTDIS_Pos)                /*!< \brief ACTLR: BTDIS Mask */
+
+#define ACTLR_RSDIS_Pos                  17U                                     /*!< \brief ACTLR: RSDIS Position */
+#define ACTLR_RSDIS_Msk                  (1UL << ACTLR_RSDIS_Pos)                /*!< \brief ACTLR: RSDIS Mask */
+
+#define ACTLR_BP_Pos                     15U                                     /*!< \brief ACTLR: BP Position */
+#define ACTLR_BP_Msk                     (3UL << ACTLR_BP_Pos)                   /*!< \brief ACTLR: BP Mask */
+
+#define ACTLR_DDVM_Pos                   15U                                     /*!< \brief ACTLR: DDVM Position */
+#define ACTLR_DDVM_Msk                   (1UL << ACTLR_DDVM_Pos)                 /*!< \brief ACTLR: DDVM Mask */
+
+#define ACTLR_L1PCTL_Pos                 13U                                     /*!< \brief ACTLR: L1PCTL Position */
+#define ACTLR_L1PCTL_Msk                 (3UL << ACTLR_L1PCTL_Pos)               /*!< \brief ACTLR: L1PCTL Mask */
+
+#define ACTLR_RADIS_Pos                  12U                                     /*!< \brief ACTLR: RADIS Position */
+#define ACTLR_RADIS_Msk                  (1UL << ACTLR_RADIS_Pos)                /*!< \brief ACTLR: RADIS Mask */
+
+#define ACTLR_L1RADIS_Pos                12U                                     /*!< \brief ACTLR: L1RADIS Position */
+#define ACTLR_L1RADIS_Msk                (1UL << ACTLR_L1RADIS_Pos)              /*!< \brief ACTLR: L1RADIS Mask */
+
+#define ACTLR_DWBST_Pos                  11U                                     /*!< \brief ACTLR: DWBST Position */
+#define ACTLR_DWBST_Msk                  (1UL << ACTLR_DWBST_Pos)                /*!< \brief ACTLR: DWBST Mask */
+
+#define ACTLR_L2RADIS_Pos                11U                                     /*!< \brief ACTLR: L2RADIS Position */
+#define ACTLR_L2RADIS_Msk                (1UL << ACTLR_L2RADIS_Pos)              /*!< \brief ACTLR: L2RADIS Mask */
+
+#define ACTLR_DODMBS_Pos                 10U                                     /*!< \brief ACTLR: DODMBS Position */
+#define ACTLR_DODMBS_Msk                 (1UL << ACTLR_DODMBS_Pos)               /*!< \brief ACTLR: DODMBS Mask */
+
+#define ACTLR_PARITY_Pos                 9U                                      /*!< \brief ACTLR: PARITY Position */
+#define ACTLR_PARITY_Msk                 (1UL << ACTLR_PARITY_Pos)               /*!< \brief ACTLR: PARITY Mask */
+
+#define ACTLR_AOW_Pos                    8U                                      /*!< \brief ACTLR: AOW Position */
+#define ACTLR_AOW_Msk                    (1UL << ACTLR_AOW_Pos)                  /*!< \brief ACTLR: AOW Mask */
+
+#define ACTLR_EXCL_Pos                   7U                                      /*!< \brief ACTLR: EXCL Position */
+#define ACTLR_EXCL_Msk                   (1UL << ACTLR_EXCL_Pos)                 /*!< \brief ACTLR: EXCL Mask */
+
+#define ACTLR_SMP_Pos                    6U                                      /*!< \brief ACTLR: SMP Position */
+#define ACTLR_SMP_Msk                    (1UL << ACTLR_SMP_Pos)                  /*!< \brief ACTLR: SMP Mask */
+
+#define ACTLR_WFLZM_Pos                  3U                                      /*!< \brief ACTLR: WFLZM Position */
+#define ACTLR_WFLZM_Msk                  (1UL << ACTLR_WFLZM_Pos)                /*!< \brief ACTLR: WFLZM Mask */
+
+#define ACTLR_L1PE_Pos                   2U                                      /*!< \brief ACTLR: L1PE Position */
+#define ACTLR_L1PE_Msk                   (1UL << ACTLR_L1PE_Pos)                 /*!< \brief ACTLR: L1PE Mask */
+
+#define ACTLR_FW_Pos                     0U                                      /*!< \brief ACTLR: FW Position */
+#define ACTLR_FW_Msk                     (1UL << ACTLR_FW_Pos)                   /*!< \brief ACTLR: FW Mask */
+
+/* CP15 Register CPACR */
+typedef union
+{
+  struct
+  {
+    uint32_t CP0:2;                      /*!< \brief bit:  0..1  Access rights for coprocessor 0 */
+    uint32_t CP1:2;                      /*!< \brief bit:  2..3  Access rights for coprocessor 1 */
+    uint32_t CP2:2;                      /*!< \brief bit:  4..5  Access rights for coprocessor 2 */
+    uint32_t CP3:2;                      /*!< \brief bit:  6..7  Access rights for coprocessor 3 */
+    uint32_t CP4:2;                      /*!< \brief bit:  8..9  Access rights for coprocessor 4 */
+    uint32_t CP5:2;                      /*!< \brief bit:10..11  Access rights for coprocessor 5 */
+    uint32_t CP6:2;                      /*!< \brief bit:12..13  Access rights for coprocessor 6 */
+    uint32_t CP7:2;                      /*!< \brief bit:14..15  Access rights for coprocessor 7 */
+    uint32_t CP8:2;                      /*!< \brief bit:16..17  Access rights for coprocessor 8 */
+    uint32_t CP9:2;                      /*!< \brief bit:18..19  Access rights for coprocessor 9 */
+    uint32_t CP10:2;                     /*!< \brief bit:20..21  Access rights for coprocessor 10 */
+    uint32_t CP11:2;                     /*!< \brief bit:22..23  Access rights for coprocessor 11 */
+	uint32_t CP12:2;                     /*!< \brief bit:24..25  Access rights for coprocessor 11 */
+	uint32_t CP13:2;                     /*!< \brief bit:26..27  Access rights for coprocessor 11 */
+	uint32_t TRCDIS:1;                   /*!< \brief bit:    28  Disable CP14 access to trace registers */
+    RESERVED(0:1, uint32_t)              
+    uint32_t D32DIS:1;                   /*!< \brief bit:    30  Disable use of registers D16-D31 of the VFP register file */
+    uint32_t ASEDIS:1;                   /*!< \brief bit:    31  Disable Advanced SIMD Functionality */
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} CPACR_Type;
+
+#define CPACR_ASEDIS_Pos                 31U                                    /*!< \brief CPACR: ASEDIS Position */
+#define CPACR_ASEDIS_Msk                 (1UL << CPACR_ASEDIS_Pos)              /*!< \brief CPACR: ASEDIS Mask */
+
+#define CPACR_D32DIS_Pos                 30U                                    /*!< \brief CPACR: D32DIS Position */
+#define CPACR_D32DIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_TRCDIS_Pos                 28U                                    /*!< \brief CPACR: D32DIS Position */
+#define CPACR_TRCDIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \brief CPACR: D32DIS Mask */
+
+#define CPACR_CP_Pos_(n)                 (n*2U)                                 /*!< \brief CPACR: CPn Position */
+#define CPACR_CP_Msk_(n)                 (3UL << CPACR_CP_Pos_(n))              /*!< \brief CPACR: CPn Mask */
+
+#define CPACR_CP_NA                      0U                                     /*!< \brief CPACR CPn field: Access denied. */
+#define CPACR_CP_PL1                     1U                                     /*!< \brief CPACR CPn field: Accessible from PL1 only. */
+#define CPACR_CP_FA                      3U                                     /*!< \brief CPACR CPn field: Full access. */
+
+/* CP15 Register DFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    uint32_t Domain:4;                   /*!< \brief bit: 4.. 7  Fault on which domain */
+    RESERVED(0:1, uint32_t)              
+	uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
+    RESERVED(1:18, uint32_t)             
+  } s;                                   /*!< \brief Structure used for bit  access in short format */
+  struct
+  {
+    uint32_t STATUS:5;                   /*!< \brief bit: 0.. 5  Fault Status bits */
+    RESERVED(0:3, uint32_t)              
+	uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    RESERVED(1:1, uint32_t)              
+    uint32_t WnR:1;                      /*!< \brief bit:    11  Write not Read bit */
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    uint32_t CM:1;                       /*!< \brief bit:    13  Cache maintenance fault */
+    RESERVED(2:18, uint32_t)             
+  } l;                                   /*!< \brief Structure used for bit  access in long format */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} DFSR_Type;
+
+#define DFSR_CM_Pos                      13U                                    /*!< \brief DFSR: CM Position */
+#define DFSR_CM_Msk                      (1UL << DFSR_CM_Pos)                   /*!< \brief DFSR: CM Mask */
+
+#define DFSR_Ext_Pos                     12U                                    /*!< \brief DFSR: Ext Position */
+#define DFSR_Ext_Msk                     (1UL << DFSR_Ext_Pos)                  /*!< \brief DFSR: Ext Mask */
+
+#define DFSR_WnR_Pos                     11U                                    /*!< \brief DFSR: WnR Position */
+#define DFSR_WnR_Msk                     (1UL << DFSR_WnR_Pos)                  /*!< \brief DFSR: WnR Mask */
+
+#define DFSR_FS1_Pos                     10U                                    /*!< \brief DFSR: FS1 Position */
+#define DFSR_FS1_Msk                     (1UL << DFSR_FS1_Pos)                  /*!< \brief DFSR: FS1 Mask */
+
+#define DFSR_LPAE_Pos                    9U                                    /*!< \brief DFSR: LPAE Position */
+#define DFSR_LPAE_Msk                    (1UL << DFSR_LPAE_Pos)                /*!< \brief DFSR: LPAE Mask */
+
+#define DFSR_Domain_Pos                  4U                                     /*!< \brief DFSR: Domain Position */
+#define DFSR_Domain_Msk                  (0xFUL << DFSR_Domain_Pos)             /*!< \brief DFSR: Domain Mask */
+
+#define DFSR_FS0_Pos                     0U                                     /*!< \brief DFSR: FS0 Position */
+#define DFSR_FS0_Msk                     (0xFUL << DFSR_FS0_Pos)                /*!< \brief DFSR: FS0 Mask */
+
+#define DFSR_STATUS_Pos                  0U                                     /*!< \brief DFSR: STATUS Position */
+#define DFSR_STATUS_Msk                  (0x3FUL << DFSR_STATUS_Pos)            /*!< \brief DFSR: STATUS Mask */
+
+/* CP15 Register IFSR */
+typedef union
+{
+  struct
+  {
+    uint32_t FS0:4;                      /*!< \brief bit: 0.. 3  Fault Status bits bit 0-3 */
+    RESERVED(0:5, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    uint32_t FS1:1;                      /*!< \brief bit:    10  Fault Status bits bit 4 */
+    RESERVED(1:1, uint32_t)              
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    RESERVED(2:19, uint32_t)             
+  } s;                                   /*!< \brief Structure used for bit access in short format */
+  struct
+  {
+    uint32_t STATUS:6;                   /*!< \brief bit: 0.. 5  Fault Status bits */
+    RESERVED(0:3, uint32_t)              
+    uint32_t LPAE:1;                     /*!< \brief bit:     9  Large Physical Address Extension */
+    RESERVED(1:2, uint32_t)              
+    uint32_t ExT:1;                      /*!< \brief bit:    12  External abort type */
+    RESERVED(2:19, uint32_t)             
+  } l;                                   /*!< \brief Structure used for bit access in long format */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} IFSR_Type;
+
+#define IFSR_ExT_Pos                     12U                                    /*!< \brief IFSR: ExT Position */
+#define IFSR_ExT_Msk                     (1UL << IFSR_ExT_Pos)                  /*!< \brief IFSR: ExT Mask */
+
+#define IFSR_FS1_Pos                     10U                                    /*!< \brief IFSR: FS1 Position */
+#define IFSR_FS1_Msk                     (1UL << IFSR_FS1_Pos)                  /*!< \brief IFSR: FS1 Mask */
+
+#define IFSR_LPAE_Pos                    9U                                     /*!< \brief IFSR: LPAE Position */
+#define IFSR_LPAE_Msk                    (0x1UL << IFSR_LPAE_Pos)               /*!< \brief IFSR: LPAE Mask */
+
+#define IFSR_FS0_Pos                     0U                                     /*!< \brief IFSR: FS0 Position */
+#define IFSR_FS0_Msk                     (0xFUL << IFSR_FS0_Pos)                /*!< \brief IFSR: FS0 Mask */
+
+#define IFSR_STATUS_Pos                  0U                                     /*!< \brief IFSR: STATUS Position */
+#define IFSR_STATUS_Msk                  (0x3FUL << IFSR_STATUS_Pos)            /*!< \brief IFSR: STATUS Mask */
+
+/* CP15 Register ISR */
+typedef union
+{
+  struct
+  {
+    RESERVED(0:6, uint32_t)              
+    uint32_t F:1;                        /*!< \brief bit:     6  FIQ pending bit */
+    uint32_t I:1;                        /*!< \brief bit:     7  IRQ pending bit */
+    uint32_t A:1;                        /*!< \brief bit:     8  External abort pending bit */
+    RESERVED(1:23, uint32_t)             
+  } b;                                   /*!< \brief Structure used for bit  access */
+  uint32_t w;                            /*!< \brief Type      used for word access */
+} ISR_Type;
+
+#define ISR_A_Pos                        13U                                    /*!< \brief ISR: A Position */
+#define ISR_A_Msk                        (1UL << ISR_A_Pos)                     /*!< \brief ISR: A Mask */
+
+#define ISR_I_Pos                        12U                                    /*!< \brief ISR: I Position */
+#define ISR_I_Msk                        (1UL << ISR_I_Pos)                     /*!< \brief ISR: I Mask */
+
+#define ISR_F_Pos                        11U                                    /*!< \brief ISR: F Position */
+#define ISR_F_Msk                        (1UL << ISR_F_Pos)                     /*!< \brief ISR: F Mask */
+
+/* DACR Register */
+#define DACR_D_Pos_(n)                   (2u*n)                                 /*!< \brief DACR: Dn Position */
+#define DACR_D_Msk_(n)                   (3UL << DACR_D_Pos_(n))                /*!< \brief DACR: Dn Mask */
+#define DACR_Dn_NOACCESS                 0U                                     /*!< \brief DACR Dn field: No access */
+#define DACR_Dn_CLIENT                   1U                                     /*!< \brief DACR Dn field: Client */
+#define DACR_Dn_MANAGER                  3U                                     /*!< \brief DACR Dn field: Manager */
+
+/**
+  \brief     Mask and shift a bit field value for use in a register bit range.
+  \param [in] field  Name of the register bit field.
+  \param [in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param [in] field  Name of the register bit field.
+  \param [in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+
+/**
+ \brief  Union type to access the L2C_310 Cache Controller.
+*/
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+typedef struct
+{
+  __IM  uint32_t CACHE_ID;                   /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register               */
+  __IM  uint32_t CACHE_TYPE;                 /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register             */
+        RESERVED(0[0x3e], uint32_t)
+  __IOM uint32_t CONTROL;                    /*!< \brief Offset: 0x0100 (R/W) Control Register                */
+  __IOM uint32_t AUX_CNT;                    /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control               */
+        RESERVED(1[0x3e], uint32_t)
+  __IOM uint32_t EVENT_CONTROL;              /*!< \brief Offset: 0x0200 (R/W) Event Counter Control           */
+  __IOM uint32_t EVENT_COUNTER1_CONF;        /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration   */
+  __IOM uint32_t EVENT_COUNTER0_CONF;        /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration   */
+        RESERVED(2[0x2], uint32_t)
+  __IOM uint32_t INTERRUPT_MASK;             /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask                  */
+  __IM  uint32_t MASKED_INT_STATUS;          /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status         */
+  __IM  uint32_t RAW_INT_STATUS;             /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status            */
+  __OM  uint32_t INTERRUPT_CLEAR;            /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear                 */
+        RESERVED(3[0x143], uint32_t)
+  __IOM uint32_t CACHE_SYNC;                 /*!< \brief Offset: 0x0730 (R/W) Cache Sync                      */
+        RESERVED(4[0xf], uint32_t)
+  __IOM uint32_t INV_LINE_PA;                /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA           */
+        RESERVED(6[2], uint32_t)
+  __IOM uint32_t INV_WAY;                    /*!< \brief Offset: 0x077c (R/W) Invalidate by Way               */
+        RESERVED(5[0xc], uint32_t)
+  __IOM uint32_t CLEAN_LINE_PA;              /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA                */
+        RESERVED(7[1], uint32_t)
+  __IOM uint32_t CLEAN_LINE_INDEX_WAY;       /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way         */
+  __IOM uint32_t CLEAN_WAY;                  /*!< \brief Offset: 0x07bc (R/W) Clean by Way                    */
+        RESERVED(8[0xc], uint32_t)
+  __IOM uint32_t CLEAN_INV_LINE_PA;          /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA  */
+        RESERVED(9[1], uint32_t)
+  __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way  */
+  __IOM uint32_t CLEAN_INV_WAY;              /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way     */
+        RESERVED(10[0x40], uint32_t)
+  __IOM uint32_t DATA_LOCK_0_WAY;            /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way          */
+  __IOM uint32_t INST_LOCK_0_WAY;            /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way   */
+  __IOM uint32_t DATA_LOCK_1_WAY;            /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way          */
+  __IOM uint32_t INST_LOCK_1_WAY;            /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way   */
+  __IOM uint32_t DATA_LOCK_2_WAY;            /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way          */
+  __IOM uint32_t INST_LOCK_2_WAY;            /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way   */
+  __IOM uint32_t DATA_LOCK_3_WAY;            /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way          */
+  __IOM uint32_t INST_LOCK_3_WAY;            /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way   */
+  __IOM uint32_t DATA_LOCK_4_WAY;            /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way          */
+  __IOM uint32_t INST_LOCK_4_WAY;            /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way   */
+  __IOM uint32_t DATA_LOCK_5_WAY;            /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way          */
+  __IOM uint32_t INST_LOCK_5_WAY;            /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way   */
+  __IOM uint32_t DATA_LOCK_6_WAY;            /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way          */
+  __IOM uint32_t INST_LOCK_6_WAY;            /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way   */
+  __IOM uint32_t DATA_LOCK_7_WAY;            /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way          */
+  __IOM uint32_t INST_LOCK_7_WAY;            /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way   */
+        RESERVED(11[0x4], uint32_t)
+  __IOM uint32_t LOCK_LINE_EN;               /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable         */
+  __IOM uint32_t UNLOCK_ALL_BY_WAY;          /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way         */
+        RESERVED(12[0xaa], uint32_t)
+  __IOM uint32_t ADDRESS_FILTER_START;       /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start         */
+  __IOM uint32_t ADDRESS_FILTER_END;         /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End           */
+        RESERVED(13[0xce], uint32_t)
+  __IOM uint32_t DEBUG_CONTROL;              /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register          */
+} L2C_310_TypeDef;
+
+#define L2C_310           ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
+#endif
+
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+    
+/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
+*/
+typedef struct
+{
+  __IOM uint32_t CTLR;                 /*!< \brief  Offset: 0x000 (R/W) Distributor Control Register */
+  __IM  uint32_t TYPER;                /*!< \brief  Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+  __IM  uint32_t IIDR;                 /*!< \brief  Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
+        RESERVED(0, uint32_t)
+  __IOM uint32_t STATUSR;              /*!< \brief  Offset: 0x010 (R/W) Error Reporting Status Register, optional */
+        RESERVED(1[11], uint32_t)
+  __OM  uint32_t SETSPI_NSR;           /*!< \brief  Offset: 0x040 ( /W) Set SPI Register */
+        RESERVED(2, uint32_t)
+  __OM  uint32_t CLRSPI_NSR;           /*!< \brief  Offset: 0x048 ( /W) Clear SPI Register */
+        RESERVED(3, uint32_t)
+  __OM  uint32_t SETSPI_SR;            /*!< \brief  Offset: 0x050 ( /W) Set SPI, Secure Register */
+        RESERVED(4, uint32_t)
+  __OM  uint32_t CLRSPI_SR;            /*!< \brief  Offset: 0x058 ( /W) Clear SPI, Secure Register */
+        RESERVED(5[9], uint32_t)
+  __IOM uint32_t IGROUPR[32];          /*!< \brief  Offset: 0x080 (R/W) Interrupt Group Registers */
+  __IOM uint32_t ISENABLER[32];        /*!< \brief  Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
+  __IOM uint32_t ICENABLER[32];        /*!< \brief  Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
+  __IOM uint32_t ISPENDR[32];          /*!< \brief  Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
+  __IOM uint32_t ICPENDR[32];          /*!< \brief  Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
+  __IOM uint32_t ISACTIVER[32];        /*!< \brief  Offset: 0x300 (R/W) Interrupt Set-Active Registers */
+  __IOM uint32_t ICACTIVER[32];        /*!< \brief  Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
+  __IOM uint32_t IPRIORITYR[255];      /*!< \brief  Offset: 0x400 (R/W) Interrupt Priority Registers */
+        RESERVED(6, uint32_t)
+  __IOM uint32_t  ITARGETSR[255];      /*!< \brief  Offset: 0x800 (R/W) Interrupt Targets Registers */
+        RESERVED(7, uint32_t)
+  __IOM uint32_t ICFGR[64];            /*!< \brief  Offset: 0xC00 (R/W) Interrupt Configuration Registers */
+  __IOM uint32_t IGRPMODR[32];         /*!< \brief  Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
+        RESERVED(8[32], uint32_t)
+  __IOM uint32_t NSACR[64];            /*!< \brief  Offset: 0xE00 (R/W) Non-secure Access Control Registers */
+  __OM  uint32_t SGIR;                 /*!< \brief  Offset: 0xF00 ( /W) Software Generated Interrupt Register */
+        RESERVED(9[3], uint32_t)
+  __IOM uint32_t CPENDSGIR[4];         /*!< \brief  Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
+  __IOM uint32_t SPENDSGIR[4];         /*!< \brief  Offset: 0xF20 (R/W) SGI Set-Pending Registers */
+        RESERVED(10[5236], uint32_t)
+  __IOM uint64_t IROUTER[988];         /*!< \brief  Offset: 0x6100(R/W) Interrupt Routing Registers */
+}  GICDistributor_Type;
+
+#define GICDistributor      ((GICDistributor_Type      *)     GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
+
+/** \brief  Structure type to access the Generic Interrupt Controller Interface (GICC)
+*/
+typedef struct
+{
+  __IOM uint32_t CTLR;                 /*!< \brief  Offset: 0x000 (R/W) CPU Interface Control Register */
+  __IOM uint32_t PMR;                  /*!< \brief  Offset: 0x004 (R/W) Interrupt Priority Mask Register */
+  __IOM uint32_t BPR;                  /*!< \brief  Offset: 0x008 (R/W) Binary Point Register */
+  __IM  uint32_t IAR;                  /*!< \brief  Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
+  __OM  uint32_t EOIR;                 /*!< \brief  Offset: 0x010 ( /W) End Of Interrupt Register */
+  __IM  uint32_t RPR;                  /*!< \brief  Offset: 0x014 (R/ ) Running Priority Register */
+  __IM  uint32_t HPPIR;                /*!< \brief  Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
+  __IOM uint32_t ABPR;                 /*!< \brief  Offset: 0x01C (R/W) Aliased Binary Point Register */
+  __IM  uint32_t AIAR;                 /*!< \brief  Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
+  __OM  uint32_t AEOIR;                /*!< \brief  Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
+  __IM  uint32_t AHPPIR;               /*!< \brief  Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
+  __IOM uint32_t STATUSR;              /*!< \brief  Offset: 0x02C (R/W) Error Reporting Status Register, optional */
+        RESERVED(1[40], uint32_t)
+  __IOM uint32_t APR[4];               /*!< \brief  Offset: 0x0D0 (R/W) Active Priority Register */
+  __IOM uint32_t NSAPR[4];             /*!< \brief  Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
+        RESERVED(2[3], uint32_t)
+  __IM  uint32_t IIDR;                 /*!< \brief  Offset: 0x0FC (R/ ) CPU Interface Identification Register */
+        RESERVED(3[960], uint32_t)
+  __OM  uint32_t DIR;                  /*!< \brief  Offset: 0x1000( /W) Deactivate Interrupt Register */
+}  GICInterface_Type;
+
+#define GICInterface        ((GICInterface_Type        *)     GIC_INTERFACE_BASE )   /*!< \brief GIC Interface register set access pointer */
+#endif
+
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Structure type to access the Private Timer
+*/
+typedef struct
+{
+  __IOM uint32_t LOAD;            //!< \brief  Offset: 0x000 (R/W) Private Timer Load Register
+  __IOM uint32_t COUNTER;         //!< \brief  Offset: 0x004 (R/W) Private Timer Counter Register
+  __IOM uint32_t CONTROL;         //!< \brief  Offset: 0x008 (R/W) Private Timer Control Register
+  __IOM uint32_t ISR;             //!< \brief  Offset: 0x00C (R/W) Private Timer Interrupt Status Register
+        RESERVED(0[4], uint32_t)
+  __IOM uint32_t WLOAD;           //!< \brief  Offset: 0x020 (R/W) Watchdog Load Register
+  __IOM uint32_t WCOUNTER;        //!< \brief  Offset: 0x024 (R/W) Watchdog Counter Register
+  __IOM uint32_t WCONTROL;        //!< \brief  Offset: 0x028 (R/W) Watchdog Control Register
+  __IOM uint32_t WISR;            //!< \brief  Offset: 0x02C (R/W) Watchdog Interrupt Status Register
+  __IOM uint32_t WRESET;          //!< \brief  Offset: 0x030 (R/W) Watchdog Reset Status Register
+  __OM  uint32_t WDISABLE;        //!< \brief  Offset: 0x034 ( /W) Watchdog Disable Register
+} Timer_Type;
+#define PTIM ((Timer_Type *) TIMER_BASE )   /*!< \brief Timer register struct */
+#endif
+#endif
+
+ /*******************************************************************************
+  *                Hardware Abstraction Layer
+   Core Function Interface contains:
+   - L1 Cache Functions
+   - L2C-310 Cache Controller Functions 
+   - PL1 Timer Functions
+   - GIC Functions
+   - MMU Functions
+  ******************************************************************************/
+ 
+/* ##########################  L1 Cache functions  ################################# */
+
+/** \brief Enable Caches by setting I and C bits in SCTLR register.
+*/
+__STATIC_INLINE void L1C_EnableCaches(void) {
+  __set_SCTLR( __get_SCTLR() | (1u << SCTLR_I_Pos) | (1u << SCTLR_C_Pos));
+  __ISB();
+}
+
+/** \brief Disable Caches by clearing I and C bits in SCTLR register.
+*/
+__STATIC_INLINE void L1C_DisableCaches(void) {
+  __set_SCTLR( __get_SCTLR() & ~(1u << SCTLR_I_Pos) & ~(1u << SCTLR_C_Pos));
+  __ISB();
+}
+
+/** \brief  Enable Branch Prediction by setting Z bit in SCTLR register.
+*/
+__STATIC_INLINE void L1C_EnableBTAC(void) {
+  __set_SCTLR( __get_SCTLR() | (1u << SCTLR_Z_Pos));
+  __ISB();
+}
+
+/** \brief  Disable Branch Prediction by clearing Z bit in SCTLR register.
+*/
+__STATIC_INLINE void L1C_DisableBTAC(void) {
+  __set_SCTLR( __get_SCTLR() & ~(1u << SCTLR_Z_Pos));
+  __ISB();
+}
+
+/** \brief  Invalidate entire branch predictor array
+*/
+__STATIC_INLINE void L1C_InvalidateBTAC(void) {
+  __set_BPIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+/** \brief  Invalidate the whole instruction cache
+*/
+__STATIC_INLINE void L1C_InvalidateICacheAll(void) {
+  __set_ICIALLU(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean data cache line by address.
+* \param [in] va Pointer to data to clear the cache for.
+*/
+__STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
+  __set_DCCMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate data cache line by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
+  __set_DCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate data cache by address.
+* \param [in] va Pointer to data to invalidate the cache for.
+*/
+__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
+  __set_DCCIMVAC((uint32_t)va);
+  __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+* \see __L1C_CleanInvalidateCache
+*/
+__STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
+  __L1C_CleanInvalidateCache(op);
+}
+
+/** \brief  Invalidate the whole data cache.
+*/
+__STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(0);
+}
+
+/** \brief  Clean the whole data cache.
+ */
+__STATIC_INLINE void L1C_CleanDCacheAll(void) {
+  L1C_CleanInvalidateCache(1);
+}
+
+/** \brief  Clean and invalidate the whole data cache.
+ */
+__STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
+  L1C_CleanInvalidateCache(2);
+}
+
+
+/* ##########################  L2 Cache functions  ################################# */
+#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+/** \brief Cache Sync operation by writing CACHE_SYNC register.
+*/
+__STATIC_INLINE void L2C_Sync(void)
+{
+  L2C_310->CACHE_SYNC = 0x0;
+}
+
+/** \brief Read cache controller cache ID from CACHE_ID register.
+ * \return L2C_310_TypeDef::CACHE_ID
+ */
+__STATIC_INLINE int L2C_GetID (void)
+{
+  return L2C_310->CACHE_ID;
+}
+
+/** \brief Read cache controller cache type from CACHE_TYPE register.
+*  \return L2C_310_TypeDef::CACHE_TYPE
+*/
+__STATIC_INLINE int L2C_GetType (void)
+{
+  return L2C_310->CACHE_TYPE;
+}
+
+/** \brief Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_InvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1u << 16u)) {
+    assoc = 16u;
+  } else {
+    assoc =  8u;
+  }
+  
+  L2C_310->INV_WAY = (1u << assoc) - 1u;
+  while(L2C_310->INV_WAY & ((1u << assoc) - 1u)); //poll invalidate
+
+  L2C_Sync();
+}
+
+/** \brief Clean and Invalidate all cache by way
+*/
+__STATIC_INLINE void L2C_CleanInvAllByWay (void)
+{
+  unsigned int assoc;
+
+  if (L2C_310->AUX_CNT & (1u << 16u)) {
+    assoc = 16u;
+  } else {
+    assoc =  8u;
+  }
+
+  L2C_310->CLEAN_INV_WAY = (1u << assoc) - 1u;
+  while(L2C_310->CLEAN_INV_WAY & ((1u << assoc) - 1u)); //poll invalidate
+
+  L2C_Sync();
+}
+
+/** \brief Enable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Enable(void)
+{
+  L2C_310->CONTROL = 0;
+  L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
+  L2C_310->DEBUG_CONTROL = 0;
+  L2C_310->DATA_LOCK_0_WAY = 0;
+  L2C_310->CACHE_SYNC = 0;
+  L2C_310->CONTROL = 0x01;
+  L2C_Sync();
+}
+
+/** \brief Disable Level 2 Cache
+*/
+__STATIC_INLINE void L2C_Disable(void)
+{
+  L2C_310->CONTROL = 0x00;
+  L2C_Sync();
+}
+
+/** \brief Invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_InvPa (void *pa)
+{
+  L2C_310->INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+/** \brief Clean cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanPa (void *pa)
+{
+  L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+
+/** \brief Clean and invalidate cache by physical address
+* \param [in] pa Pointer to data to invalidate cache for.
+*/
+__STATIC_INLINE void L2C_CleanInvPa (void *pa)
+{
+  L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+  L2C_Sync();
+}
+#endif
+
+/* ##########################  GIC functions  ###################################### */
+#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+  
+/** \brief  Enable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_EnableDistributor(void)
+{
+  GICDistributor->CTLR |= 1U;
+}
+
+/** \brief Disable the interrupt distributor using the GIC's CTLR register.
+*/
+__STATIC_INLINE void GIC_DisableDistributor(void)
+{
+  GICDistributor->CTLR &=~1U;
+}
+
+/** \brief Read the GIC's TYPER register.
+* \return GICDistributor_Type::TYPER
+*/
+__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
+{
+  return (GICDistributor->TYPER);
+}
+
+/** \brief Reads the GIC's IIDR register.
+* \return GICDistributor_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
+{
+  return (GICDistributor->IIDR);
+}
+
+/** \brief Sets the GIC's ITARGETSR register for the given interrupt.
+* \param [in] IRQn Interrupt to be configured.
+* \param [in] cpu_target CPU interfaces to assign this interrupt to.
+*/
+__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+  uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+  GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the GIC's ITARGETSR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return GICDistributor_Type::ITARGETSR
+*/
+__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+  return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Enable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_EnableInterface(void)
+{
+  GICInterface->CTLR |= 1U; //enable interface
+}
+
+/** \brief Disable the CPU's interrupt interface.
+*/
+__STATIC_INLINE void GIC_DisableInterface(void)
+{
+  GICInterface->CTLR &=~1U; //disable distributor
+}
+
+/** \brief Read the CPU's IAR register.
+* \return GICInterface_Type::IAR
+*/
+__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
+{
+  return (IRQn_Type)(GICInterface->IAR);
+}
+
+/** \brief Writes the given interrupt number to the CPU's EOIR register.
+* \param [in] IRQn The interrupt to be signaled as finished.
+*/
+__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+  GICInterface->EOIR = IRQn;
+}
+
+/** \brief Enables the given interrupt using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt enable status using GIC's ISENABLER register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
+*/
+__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+
+/** \brief Disables the given interrupt using GIC's ICENABLER register.
+* \param [in] IRQn The interrupt to be disabled.
+*/
+__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+  GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
+}
+
+/** \brief Get interrupt pending status from GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - interrupt is not pending, 1 - interrupt is pendig.
+*/
+__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  uint32_t pend;
+
+  if (IRQn >= 16U) {
+    pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+    // No CPU identification offered
+    if (pend != 0U) {
+      pend = 1U;
+    } else {
+      pend = 0U;
+    }
+  }
+
+  return (pend);
+}
+
+/** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if (IRQn >= 16U) {
+    GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+    // Forward the interrupt to the CPU interface that requested it
+    GICDistributor->SGIR = (IRQn | 0x02000000U);
+  }
+}
+
+/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
+* \param [in] IRQn The interrupt to be enabled.
+*/
+__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if (IRQn >= 16U) {
+    GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
+  } else {
+    // INTID 0-15 Software Generated Interrupt
+    GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
+  }
+}
+
+/** \brief Sets the interrupt configuration using GIC's ICFGR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+*                                           Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
+{
+  uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
+  uint32_t shift = (IRQn % 16U) << 1U;
+
+  icfgr &= (~(3U         << shift));
+  icfgr |= (  int_config << shift);
+
+  GICDistributor->ICFGR[IRQn / 16U] = icfgr;
+}
+
+/** \brief Get the interrupt configuration from the GIC's ICFGR register.
+* \param [in] IRQn Interrupt to acquire the configuration for.
+* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
+*                                 Bit 1: 0 - level sensitive, 1 - edge triggered
+*/
+__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
+{
+  return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
+}
+
+/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be configured.
+* \param [in] priority The priority for the interrupt, lower values denote higher priorities.
+*/
+__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
+  GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
+}
+
+/** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
+* \param [in] IRQn The interrupt to be queried.
+*/
+__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+  return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
+}
+
+/** \brief Set the interrupt priority mask using CPU's PMR register.
+* \param [in] priority Priority mask to be set.
+*/
+__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
+{
+  GICInterface->PMR = priority & 0xFFUL; //set priority mask
+}
+
+/** \brief Read the current interrupt priority mask from CPU's PMR register.
+* \result GICInterface_Type::PMR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
+{
+  return GICInterface->PMR;
+}
+
+/** \brief Configures the group priority and subpriority split point using CPU's BPR register.
+* \param [in] binary_point Amount of bits used as subpriority.
+*/
+__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+  GICInterface->BPR = binary_point & 7U; //set binary point
+}
+
+/** \brief Read the current group priority and subpriority split point from CPU's BPR register.
+* \return GICInterface_Type::BPR
+*/
+__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
+{
+  return GICInterface->BPR;
+}
+
+/** \brief Get the status for a given interrupt.
+* \param [in] IRQn The interrupt to get status for.
+* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
+*/
+__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+  uint32_t pending, active;
+
+  active = ((GICDistributor->ISACTIVER[IRQn / 32U])  >> (IRQn % 32U)) & 1UL;
+  pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
+
+  return ((active<<1U) | pending);
+}
+
+/** \brief Generate a software interrupt using GIC's SGIR register.
+* \param [in] IRQn Software interrupt to be generated.
+* \param [in] target_list List of CPUs the software interrupt should be forwarded to.
+* \param [in] filter_list Filter to be applied to determine interrupt receivers.
+*/
+__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+  GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
+}
+
+/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
+* \return GICInterface_Type::HPPIR
+*/
+__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) 
+{ 
+  return GICInterface->HPPIR; 
+}
+
+/** \brief Provides information about the implementer and revision of the CPU interface.
+* \return GICInterface_Type::IIDR
+*/
+__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
+{ 
+  return GICInterface->IIDR; 
+}
+
+/** \brief Set the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
+{
+  uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
+  uint32_t shift   = (IRQn % 32U);
+
+  igroupr &= (~(1U          << shift));
+  igroupr |= ( (group & 1U) << shift);
+
+  GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
+}
+#define GIC_SetSecurity         GIC_SetGroup
+
+/** \brief Get the interrupt group from the GIC's IGROUPR register.
+* \param [in] IRQn The interrupt to be queried.
+* \return 0 - Group 0, 1 - Group 1
+*/
+__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
+{
+  return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
+}
+#define GIC_GetSecurity         GIC_GetGroup
+
+/** \brief Initialize the interrupt distributor.
+*/
+__STATIC_INLINE void GIC_DistInit(void)
+{
+  IRQn_Type i;
+  uint32_t num_irq = 0;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableDistributor();
+  //Get the maximum number of interrupts that the GIC supports
+  num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0, 0xff);
+  priority_field = GIC_GetPriority((IRQn_Type)0);
+
+  for (i = (IRQn_Type)32; i < num_irq; i++)
+  {
+      //Disable the SPI interrupt
+      GIC_DisableIRQ(i);
+      if (i > 15) {
+        //Set level-sensitive (and N-N model)
+        GIC_SetConfiguration(i, 0);
+      }
+      //Set priority
+      GIC_SetPriority(i, priority_field/2);
+      //Set target list to CPU0
+      GIC_SetTarget(i, 1);
+  }
+  //Enable distributor
+  GIC_EnableDistributor();
+}
+
+/** \brief Initialize the CPU's interrupt interface
+*/
+__STATIC_INLINE void GIC_CPUInterfaceInit(void)
+{
+  IRQn_Type i;
+  uint32_t priority_field;
+
+  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
+  //configuring all of the interrupts as Secure.
+
+  //Disable interrupt forwarding
+  GIC_DisableInterface();
+
+  /* Priority level is implementation defined.
+   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
+   priority field and read back the value stored.*/
+  GIC_SetPriority((IRQn_Type)0, 0xff);
+  priority_field = GIC_GetPriority((IRQn_Type)0);
+
+  //SGI and PPI
+  for (i = (IRQn_Type)0; i < 32; i++)
+  {
+    if(i > 15) {
+      //Set level-sensitive (and N-N model) for PPI
+      GIC_SetConfiguration(i, 0U);
+    }
+    //Disable SGI and PPI interrupts
+    GIC_DisableIRQ(i);
+    //Set priority
+    GIC_SetPriority(i, priority_field/2);
+  }
+  //Enable interface
+  GIC_EnableInterface();
+  //Set binary point to 0
+  GIC_SetBinaryPoint(0);
+  //Set priority mask
+  GIC_SetInterfacePriorityMask(0xff);
+}
+
+/** \brief Initialize and enable the GIC
+*/
+__STATIC_INLINE void GIC_Enable(void)
+{
+  GIC_DistInit();
+  GIC_CPUInterfaceInit(); //per CPU
+}
+#endif
+
+/* ##########################  Generic Timer functions  ############################ */
+#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+  
+/* PL1 Physical Timer */
+#if (__CORTEX_A == 7U) || defined(DOXYGEN)
+  
+/** \brief Physical Timer Control register */
+typedef union
+{
+  struct
+  {
+    uint32_t ENABLE:1;      /*!< \brief bit: 0      Enables the timer. */
+    uint32_t IMASK:1;       /*!< \brief bit: 1      Timer output signal mask bit. */
+    uint32_t ISTATUS:1;     /*!< \brief bit: 2      The status of the timer. */
+    RESERVED(0:29, uint32_t)
+  } b;                      /*!< \brief Structure used for bit  access */
+  uint32_t w;               /*!< \brief Type      used for word access */
+} CNTP_CTL_Type;
+
+/** \brief Configures the frequency the timer shall run at.
+* \param [in] value The timer frequency in Hz.
+*/
+__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) {
+  __set_CNTFRQ(value);
+  __ISB();
+}
+
+/** \brief Sets the reset value of the timer.
+* \param [in] value The value the timer is loaded with.
+*/
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
+  __set_CNTP_TVAL(value);
+  __ISB();
+}
+
+/** \brief Get the current counter value.
+* \return Current counter value.
+*/
+__STATIC_INLINE uint32_t PL1_GetCurrentValue() {
+  return(__get_CNTP_TVAL());
+}
+
+/** \brief Configure the timer by setting the control value.
+* \param [in] value New timer control value.
+*/
+__STATIC_INLINE void PL1_SetControl(uint32_t value) {
+  __set_CNTP_CTL(value);
+  __ISB();
+}
+
+/** \brief Get the control value.
+* \return Control value.
+*/
+__STATIC_INLINE uint32_t PL1_GetControl() {
+  return(__get_CNTP_CTL());
+}
+#endif
+
+/* Private Timer */
+#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
+/** \brief Set the load value to timers LOAD register.
+* \param [in] value The load value to be set.
+*/
+__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
+  PTIM->LOAD = value;
+}
+
+/** \brief Get the load value from timers LOAD register.
+* \return Timer_Type::LOAD
+*/
+__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
+  return(PTIM->LOAD);
+}
+
+/** \brief Set current counter value from its COUNTER register.
+*/
+__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) {
+  PTIM->COUNTER = value;
+}
+
+/** \brief Get current counter value from timers COUNTER register.
+* \result Timer_Type::COUNTER
+*/
+__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
+  return(PTIM->COUNTER);
+}
+
+/** \brief Configure the timer using its CONTROL register.
+* \param [in] value The new configuration value to be set.
+*/
+__STATIC_INLINE void PTIM_SetControl(uint32_t value) {
+  PTIM->CONTROL = value;
+}
+
+/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
+* \return Timer_Type::CONTROL
+*/
+__STATIC_INLINE uint32_t PTIM_GetControl(void) {
+  return(PTIM->CONTROL);
+}
+
+/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
+* \return 0 - flag is not set, 1- flag is set
+*/
+__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) {
+  return (PTIM->ISR & 1UL);
+}
+
+/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
+*/
+__STATIC_INLINE void PTIM_ClearEventFlag(void) {
+  PTIM->ISR = 1;
+}
+#endif
+#endif
+
+/* ##########################  MMU functions  ###################################### */
+
+#define SECTION_DESCRIPTOR      (0x2)
+#define SECTION_MASK            (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
+#define SECTION_B_SHIFT         (2)
+#define SECTION_C_SHIFT         (3)
+#define SECTION_TEX0_SHIFT      (12)
+#define SECTION_TEX1_SHIFT      (13)
+#define SECTION_TEX2_SHIFT      (14)
+
+#define SECTION_XN_MASK         (0xFFFFFFEF)
+#define SECTION_XN_SHIFT        (4)
+
+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT    (5)
+
+#define SECTION_P_MASK          (0xFFFFFDFF)
+#define SECTION_P_SHIFT         (9)
+
+#define SECTION_AP_MASK         (0xFFFF73FF)
+#define SECTION_AP_SHIFT        (10)
+#define SECTION_AP2_SHIFT       (15)
+
+#define SECTION_S_MASK          (0xFFFEFFFF)
+#define SECTION_S_SHIFT         (16)
+
+#define SECTION_NG_MASK         (0xFFFDFFFF)
+#define SECTION_NG_SHIFT        (17)
+
+#define SECTION_NS_MASK         (0xFFF7FFFF)
+#define SECTION_NS_SHIFT        (19)
+
+#define PAGE_L1_DESCRIPTOR      (0x1)
+#define PAGE_L1_MASK            (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC         (0x2)
+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC        (0x1)
+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT         (2)
+#define PAGE_4K_C_SHIFT         (3)
+#define PAGE_4K_TEX0_SHIFT      (6)
+#define PAGE_4K_TEX1_SHIFT      (7)
+#define PAGE_4K_TEX2_SHIFT      (8)
+
+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT        (2)
+#define PAGE_64K_C_SHIFT        (3)
+#define PAGE_64K_TEX0_SHIFT     (12)
+#define PAGE_64K_TEX1_SHIFT     (13)
+#define PAGE_64K_TEX2_SHIFT     (14)
+
+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
+#define PAGE_B_SHIFT            (2)
+#define PAGE_C_SHIFT            (3)
+#define PAGE_TEX_SHIFT          (12)
+
+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT        (0)
+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT       (15)
+
+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT       (5)
+
+#define PAGE_P_MASK             (0xFFFFFDFF)
+#define PAGE_P_SHIFT            (9)
+
+#define PAGE_AP_MASK            (0xFFFFFDCF)
+#define PAGE_AP_SHIFT           (4)
+#define PAGE_AP2_SHIFT          (9)
+
+#define PAGE_S_MASK             (0xFFFFFBFF)
+#define PAGE_S_SHIFT            (10)
+
+#define PAGE_NG_MASK            (0xFFFFF7FF)
+#define PAGE_NG_SHIFT           (11)
+
+#define PAGE_NS_MASK            (0xFFFFFFF7)
+#define PAGE_NS_SHIFT           (3)
+
+#define OFFSET_1M               (0x00100000)
+#define OFFSET_64K              (0x00010000)
+#define OFFSET_4K               (0x00001000)
+
+#define DESCRIPTOR_FAULT        (0x00000000)
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+   SECTION,
+   PAGE_4k,
+   PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+   NORMAL,
+   DEVICE,
+   SHARED_DEVICE,
+   NON_SHARED_DEVICE,
+   STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+   NON_CACHEABLE,
+   WB_WA,
+   WT,
+   WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+   ECC_DISABLED,
+   ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+   EXECUTE,
+   NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+   GLOBAL,
+   NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+   NON_SHARED,
+   SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+   SECURE,
+   NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+   NO_ACCESS,
+   RW,
+   READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+    mmu_region_size_Type rg_t;
+    mmu_memory_Type mem_t;
+    uint8_t domain;
+    mmu_cacheability_Type inner_norm_t;
+    mmu_cacheability_Type outer_norm_t;
+    mmu_ecc_check_Type e_t;
+    mmu_execute_Type xn_t;
+    mmu_global_Type g_t;
+    mmu_secure_Type sec_t;
+    mmu_access_Type priv_t;
+    mmu_access_Type user_t;
+    mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+//Following macros define the descriptors and attributes
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
+#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetSectionDescriptor(&descriptor_l1, region);
+//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
+
+/** \brief  Set section execution-never attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+  *descriptor_l1 &= SECTION_XN_MASK;
+  *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Section domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= SECTION_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section access privileges
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l1 &= SECTION_AP_MASK;
+  *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+  *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set section shareability
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_S_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Global attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+  *descriptor_l1 &= SECTION_NG_MASK;
+  *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set section Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= SECTION_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+  return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief  Set 4k/64k page execution-never attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
+  \param [in]              page  Page size: PAGE_4k, PAGE_64k,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+  if (page == PAGE_4k)
+  {
+      *descriptor_l2 &= PAGE_XN_4K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+  }
+  else
+  {
+      *descriptor_l2 &= PAGE_XN_64K_MASK;
+      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page domain
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]            domain  Page domain
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
+{
+  *descriptor_l1 &= PAGE_DOMAIN_MASK;
+  *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page parity check
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+  *descriptor_l1 &= SECTION_P_MASK;
+  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page access privileges
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+  \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+  \param [in]               afe  Access flag enable
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+{
+  uint32_t ap = 0;
+
+  if (afe == 0) { //full access
+    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+    else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x6; }
+  }
+
+  else { //Simplified access
+    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+    else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+    else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+  }
+
+  *descriptor_l2 &= PAGE_AP_MASK;
+  *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+  *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+  return 0;
+}
+
+/** \brief  Set 4k/64k page shareability
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+  *descriptor_l2 &= PAGE_S_MASK;
+  *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Global attribute
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+  *descriptor_l2 &= PAGE_NG_MASK;
+  *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+  return 0;
+}
+
+/** \brief  Set 4k/64k page Security attribute
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+  *descriptor_l1 &= PAGE_NS_MASK;
+  *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+  return 0;
+}
+
+/** \brief  Set Section memory attributes
+
+  \param [out]    descriptor_l1  L1 descriptor.
+  \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+  *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+  if (STRONGLY_ORDERED == mem)
+  {
+    return 0;
+  }
+  else if (SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+  }
+  else if (NON_SHARED_DEVICE == mem)
+  {
+    *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+  }
+  else if (NORMAL == mem)
+  {
+   *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+   switch(inner)
+   {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+        break;
+    }
+    switch(outer)
+    {
+      case NON_CACHEABLE:
+        break;
+      case WB_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+        break;
+      case WT:
+        *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+        break;
+      case WB_NO_WA:
+        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+        break;
+    }
+  }
+  return 0;
+}
+
+/** \brief  Set 4k/64k page memory attributes
+
+  \param [out]    descriptor_l2  L2 descriptor.
+  \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+  \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+  \param [in]              page  Page size
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+  *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+  if (page == PAGE_64k)
+  {
+    //same as section
+    MMU_MemorySection(descriptor_l2, mem, outer, inner);
+  }
+  else
+  {
+    if (STRONGLY_ORDERED == mem)
+    {
+      return 0;
+    }
+    else if (SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+    }
+    else if (NON_SHARED_DEVICE == mem)
+    {
+      *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+    }
+    else if (NORMAL == mem)
+    {
+      *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+      switch(inner)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+          break;
+      }
+      switch(outer)
+      {
+        case NON_CACHEABLE:
+          break;
+        case WB_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+        case WT:
+          *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+          break;
+        case WB_NO_WA:
+          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+          break;
+      }
+    }
+  }
+
+  return 0;
+}
+
+/** \brief  Create a L1 section descriptor
+
+  \param [out]     descriptor  L1 descriptor
+  \param [in]      reg  Section attributes
+  
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+
+  MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+  MMU_XNSection(descriptor,reg.xn_t);
+  MMU_DomainSection(descriptor, reg.domain);
+  MMU_PSection(descriptor, reg.e_t);
+  MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
+  MMU_SharedSection(descriptor,reg.sh_t);
+  MMU_GlobalSection(descriptor,reg.g_t);
+  MMU_SecureSection(descriptor,reg.sec_t);
+  *descriptor &= SECTION_MASK;
+  *descriptor |= SECTION_DESCRIPTOR;
+ 
+  return 0;
+}
+
+
+/** \brief  Create a L1 and L2 4k/64k page descriptor
+
+  \param [out]       descriptor  L1 descriptor
+  \param [out]      descriptor2  L2 descriptor
+  \param [in]               reg  4k/64k page attributes
+
+  \return          0
+*/
+__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+  *descriptor  = 0;
+  *descriptor2 = 0;
+
+  switch (reg.rg_t)
+  {
+    case PAGE_4k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_4K_MASK;
+      *descriptor2 |= PAGE_L2_4K_DESC;
+      break;
+
+    case PAGE_64k:
+      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+      MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
+      MMU_DomainPage(descriptor, reg.domain);
+      MMU_PPage(descriptor, reg.e_t);
+      MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
+      MMU_SharedPage(descriptor2,reg.sh_t);
+      MMU_GlobalPage(descriptor2,reg.g_t);
+      MMU_SecurePage(descriptor,reg.sec_t);
+      *descriptor &= PAGE_L1_MASK;
+      *descriptor |= PAGE_L1_DESCRIPTOR;
+      *descriptor2 &= PAGE_L2_64K_MASK;
+      *descriptor2 |= PAGE_L2_64K_DESC;
+      break;
+
+    case SECTION:
+      //error
+      break;
+  }
+  
+  return 0;
+}
+
+/** \brief  Create a 1MB Section
+
+  \param [in]               ttb  Translation table base address
+  \param [in]      base_address  Section base address
+  \param [in]             count  Number of sections to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+  uint32_t offset;
+  uint32_t entry;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = (base_address & 0xFFF00000) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb = ttb + offset;
+
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb++ = entry;
+    entry += OFFSET_1M;
+  }
+}
+
+/** \brief  Create a 4k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  4k base address
+  \param [in]             count  Number of 4k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i;
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //4 bytes aligned
+    *ttb_l2++ = entry2;
+    entry2 += OFFSET_4K;
+  }
+}
+
+/** \brief  Create a 64k page entry
+
+  \param [in]               ttb  L1 table base address
+  \param [in]      base_address  64k base address
+  \param [in]             count  Number of 64k pages to create
+  \param [in]     descriptor_l1  L1 descriptor (region attributes)
+  \param [in]            ttb_l2  L2 table base address
+  \param [in]     descriptor_l2  L2 descriptor (region attributes)
+
+*/
+__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+  uint32_t offset, offset2;
+  uint32_t entry, entry2;
+  uint32_t i,j;
+
+
+  offset = base_address >> 20;
+  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+  //4 bytes aligned
+  ttb += offset;
+  //create l1_entry
+  *ttb = entry;
+
+  offset2 = (base_address & 0xff000) >> 12;
+  ttb_l2 += offset2;
+  entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+  for (i = 0; i < count; i++ )
+  {
+    //create 16 entries
+    for (j = 0; j < 16; j++)
+    {
+      //4 bytes aligned
+      *ttb_l2++ = entry2;
+    }
+    entry2 += OFFSET_64K;
+  }
+}
+
+/** \brief  Enable MMU
+*/
+__STATIC_INLINE void MMU_Enable(void) {
+  // Set M bit 0 to enable the MMU
+  // Set AFE bit to enable simplified access permissions model
+  // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+  __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+  __ISB();
+}
+
+/** \brief  Disable MMU
+*/
+__STATIC_INLINE void MMU_Disable(void) {
+  // Clear M bit 0 to disable the MMU
+  __set_SCTLR( __get_SCTLR() & ~1);
+  __ISB();
+}
+
+/** \brief  Invalidate entire unified TLB
+*/
+
+__STATIC_INLINE void MMU_InvalidateTLB(void) {
+  __set_TLBIALL(0);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CA_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/irq_ctrl.h b/os/common/ext/ARM/CMSIS/Core_A/Include/irq_ctrl.h
new file mode 100644
index 000000000..4299c2831
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core_A/Include/irq_ctrl.h
@@ -0,0 +1,180 @@
+/**************************************************************************//**
+ * @file     irq_ctrl.h
+ * @brief    Interrupt Controller API header file
+ * @version  V1.0.0
+ * @date     23. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
+#include <stdint.h>
+
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+/// Interrupt handler data type
+typedef void (*IRQHandler_t) (void);
+#endif
+
+#ifndef IRQN_ID_T
+#define IRQN_ID_T
+/// Interrupt ID number data type
+typedef int32_t IRQn_ID_t;
+#endif
+
+/* Interrupt mode bit-masks */
+#define IRQ_MODE_TRIG_Pos           (0U)
+#define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+#define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
+#define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
+
+#define IRQ_MODE_TYPE_Pos           (3U)
+#define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)
+#define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line
+#define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line
+
+#define IRQ_MODE_DOMAIN_Pos         (4U)
+#define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)
+#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain
+#define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain
+
+#define IRQ_MODE_CPU_Pos            (5U)
+#define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)
+#define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs
+#define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0
+#define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1
+#define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2
+#define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3
+#define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4
+#define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5
+#define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
+#define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
+
+#define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
+
+/* Interrupt priority bit-masks */
+#define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask
+#define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error
+
+/// Initialize interrupt controller.
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Initialize (void);
+
+/// Register interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     handler       interrupt handler function address
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
+
+/// Get the registered interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \return registered interrupt handler function address.
+IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
+
+/// Enable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Enable (IRQn_ID_t irqn);
+
+/// Disable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Disable (IRQn_ID_t irqn);
+
+/// Get interrupt enable state.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
+uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
+
+/// Configure interrupt request mode.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     mode          mode configuration
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
+
+/// Get interrupt mode configuration.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+uint32_t IRQ_GetMode (IRQn_ID_t irqn);
+
+/// Get ID number of current interrupt request (IRQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveIRQ (void);
+
+/// Get ID number of current fast interrupt request (FIQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveFIQ (void);
+
+/// Signal end of interrupt processing.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
+
+/// Set interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPending (IRQn_ID_t irqn);
+
+/// Get interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
+uint32_t IRQ_GetPending (IRQn_ID_t irqn);
+
+/// Clear interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_ClearPending (IRQn_ID_t irqn);
+
+/// Set interrupt priority value.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     priority      interrupt priority value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
+
+/// Get interrupt priority.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
+
+/// Set priority masking threshold.
+/// \param[in]     priority      priority masking threshold value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityMask (uint32_t priority);
+
+/// Get priority masking threshold
+/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityMask (void);
+
+/// Set priority grouping field split point
+/// \param[in]     bits          number of MSB bits included in the group priority field comparison
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
+
+/// Get priority grouping field split point
+/// \return current number of MSB bits included in the group priority field comparison with
+///         optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityGroupBits (void);
+
+#endif  // IRQ_CTRL_H_
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Source/irq_ctrl_gic.c b/os/common/ext/ARM/CMSIS/Core_A/Source/irq_ctrl_gic.c
new file mode 100644
index 000000000..6c440a190
--- /dev/null
+++ b/os/common/ext/ARM/CMSIS/Core_A/Source/irq_ctrl_gic.c
@@ -0,0 +1,404 @@
+/**************************************************************************//**
+ * @file     irq_ctrl_gic.c
+ * @brief    Interrupt controller handling implementation for GIC
+ * @version  V1.0.0
+ * @date     30. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT      (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t   IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+  uint32_t i;
+
+  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+    IRQTable[i] = (IRQHandler_t)NULL;
+  }
+  GIC_Enable();
+  return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    IRQTable[irqn] = handler;
+    status =  0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+  IRQHandler_t h;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    h = IRQTable[irqn];
+  } else {
+    h = (IRQHandler_t)0;
+  }
+
+  return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    GIC_EnableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    GIC_DisableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+  uint32_t enable;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+  } else {
+    enable = 0U;
+  }
+
+  return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+  int32_t status;
+  uint32_t val;
+  uint8_t cfg;
+  uint8_t secure;
+  uint8_t cpu;
+
+  status = 0;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    // Check triggering mode
+    val = (mode & IRQ_MODE_TRIG_Msk);
+
+    if (val == IRQ_MODE_TRIG_LEVEL) {
+      cfg = 0x00U;
+    } else if (val == IRQ_MODE_TRIG_EDGE) {
+      cfg = 0x02U;
+    } else {
+      status = -1;
+    }
+
+    // Check interrupt type
+    val = mode & IRQ_MODE_TYPE_Msk;
+
+    if (val != IRQ_MODE_TYPE_IRQ) {
+      status = -1;
+    }
+
+    // Check interrupt domain
+    val = mode & IRQ_MODE_DOMAIN_Msk;
+
+    if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+      secure = 0;
+    } else {
+      // Check security extensions support
+      val = GIC_DistributorInfo() & (1UL << 10U);
+
+      if (val != 0U) {
+        // Security extensions are supported
+        secure = 1;
+      } else {
+        status = -1;
+      }
+    }
+
+    // Check interrupt CPU targets
+    val = mode & IRQ_MODE_CPU_Msk;
+
+    if (val == IRQ_MODE_CPU_ALL) {
+      cpu = 0xFF;
+    } else {
+      cpu = val >> IRQ_MODE_CPU_Pos;
+    }
+
+    // Apply configuration if no mode error
+    if (status == 0) {
+      GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+      GIC_SetTarget       ((IRQn_Type)irqn, cpu);
+
+      if (secure != 0U) {
+        GIC_SetGroup ((IRQn_Type)irqn, secure);
+      }
+    }
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+  uint32_t mode;
+  uint32_t val;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    mode = IRQ_MODE_TYPE_IRQ;
+
+    // Get trigger mode
+    val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+    if ((val & 2U) != 0U) {
+      // Corresponding interrupt is edge triggered
+      mode |= IRQ_MODE_TRIG_EDGE;
+    } else {
+      // Corresponding interrupt is level triggered
+      mode |= IRQ_MODE_TRIG_LEVEL;
+    }
+
+    // Get interrupt CPU targets
+    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+  } else {
+    mode = IRQ_MODE_ERROR;
+  }
+
+  return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+  IRQn_ID_t irqn;
+  uint32_t prio;
+
+  /* Dummy read to avoid GIC 390 errata 801120 */
+  GIC_GetHighPendingIRQ();
+
+  irqn = GIC_AcknowledgePending();
+
+  __DSB();
+
+  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */
+  /* The following workaround code is for a single-core system.  It would be       */
+  /* different in a multi-core system.                                             */
+  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+  /* so unlock it, otherwise service the interrupt as normal.                      */
+  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */
+  /* so will not occur here.                                                       */
+
+  if ((irqn == 0) || (irqn >= 0x3FE)) {
+    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+    prio = GIC_GetPriority((IRQn_Type)0);
+    GIC_SetPriority ((IRQn_Type)0, prio);
+
+    __DSB();
+
+    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+      /* If the ID is 0, is active and has not been seen before */
+      IRQ_ID0 = 1U;
+    }
+    /* End of Workaround GIC 390 errata 733075 */
+  }
+
+  return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+  return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    GIC_EndInterrupt ((IRQn_Type)irqn);
+
+    if (irqn == 0) {
+      IRQ_ID0 = 0U;
+    }
+
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+  uint32_t pending;
+
+  if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+  } else {
+    pending = 0U;
+  }
+
+  return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPriority ((IRQn_Type)irqn, priority);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+  uint32_t priority;
+
+  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+    priority = GIC_GetPriority ((IRQn_Type)irqn);
+  } else {
+    priority = IRQ_PRIORITY_ERROR;
+  }
+
+  return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+  GIC_SetInterfacePriorityMask (priority);
+  return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+  return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+  int32_t status;
+
+  if (bits == IRQ_PRIORITY_Msk) {
+    bits = 7U;
+  }
+
+  if (bits < 8U) {
+    GIC_SetBinaryPoint (7U - bits);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+  uint32_t bp;
+
+  bp = GIC_GetBinaryPoint() & 0x07U;
+
+  return (7U - bp);
+}
+
+#endif
diff --git a/os/common/ext/CMSIS/readme.txt b/os/common/ext/ARM/CMSIS/readme.txt
index e9d6eb03b..e9d6eb03b 100644..100755
--- a/os/common/ext/CMSIS/readme.txt
+++ b/os/common/ext/ARM/CMSIS/readme.txt
diff --git a/os/common/ext/CMSIS/generic/generic_cm0.h b/os/common/ext/CMSIS/generic/generic_cm0.h
deleted file mode 100644
index bdee40ff3..000000000
--- a/os/common/ext/CMSIS/generic/generic_cm0.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    generic_cm0.h

- * @brief   CMSIS header for a generic Cortex-M0 platform.

- *

- * @addtogroup GENERIC_CMSIS_DEVICE

- * @{

- */

-

-#ifndef __GENERIC_CM0_H

-#define __GENERIC_CM0_H

-

-#define __CM0_REV                   0

-#define __MPU_PRESENT               0

-#if !defined(__NVIC_PRIO_BITS) || defined(__DOXYGEN__)

-#define __NVIC_PRIO_BITS            2

-#endif

-#if !defined(__Vendor_SysTickConfig) || defined(__DOXYGEN__)

-#define __Vendor_SysTickConfig      0

-#endif

-

-typedef enum {

-  NonMaskableInt_IRQn         = -14,

-  HardFault_IRQn              = -13,

-  SVC_IRQn                    = -5,

-  PendSV_IRQn                 = -2,

-  SysTick_IRQn                = -1,

-  Vector40_IRQn               = 0,

-  Vector44_IRQn               = 1,

-  Vector48_IRQn               = 2,

-  Vector4C_IRQn               = 3,

-  Vector50_IRQn               = 4,

-  Vector54_IRQn               = 5,

-  Vector58_IRQn               = 6,

-  Vector5C_IRQn               = 7,

-  Vector60_IRQn               = 8,

-  Vector64_IRQn               = 9,

-  Vector68_IRQn               = 10,

-  Vector6C_IRQn               = 11,

-  Vector70_IRQn               = 12,

-  Vector74_IRQn               = 13,

-  Vector78_IRQn               = 14,

-  Vector7C_IRQn               = 15,

-  Vector80_IRQn               = 16,

-  Vector84_IRQn               = 17,

-  Vector88_IRQn               = 18,

-  Vector8C_IRQn               = 19,

-  Vector90_IRQn               = 20,

-  Vector94_IRQn               = 21,

-  Vector98_IRQn               = 22,

-  Vector9C_IRQn               = 23,

-  VectorA0_IRQn               = 24,

-  VectorA4_IRQn               = 25,

-  VectorA8_IRQn               = 26,

-  VectorAC_IRQn               = 27,

-  VectorB0_IRQn               = 28,

-  VectorB4_IRQn               = 29,

-  VectorB8_IRQn               = 30,

-  VectorBC_IRQn               = 31

-} IRQn_Type;

-

-

-#include "core_cm0.h"

-#include "system_generic_cm0.h"

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __GENERIC_CM0_H */

-

-/** @} */

diff --git a/os/common/ext/CMSIS/generic/readme.txt b/os/common/ext/CMSIS/generic/readme.txt
deleted file mode 100644
index 8f6a52a39..000000000
--- a/os/common/ext/CMSIS/generic/readme.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Generic CMSIS device files for a generic Cortex-M, usable when the MCU vendor

-does not provide a proper device file.
\ No newline at end of file
diff --git a/os/common/ext/CMSIS/generic/system_generic.h b/os/common/ext/CMSIS/generic/system_generic.h
deleted file mode 100644
index 6d3f1d907..000000000
--- a/os/common/ext/CMSIS/generic/system_generic.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    system_generic.h

- * @brief   CMSIS header for a generic Cortex-M platform.

- *

- * @addtogroup GENERIC_CMSIS_DEVICE

- * @{

- */

-

-#ifndef __SYSTEM_GENERIC_H

-#define __SYSTEM_GENERIC_H

-

-extern uint32_t SystemCoreClock;

-

-#ifdef __cplusplus

-extern "C" {

-#endif 

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /*__SYSTEM_GENERIC_H */

-

-/** @} */

diff --git a/os/common/ext/CMSIS/include/arm_common_tables.h b/os/common/ext/CMSIS/include/arm_common_tables.h
deleted file mode 100644
index d5d72417b..000000000
--- a/os/common/ext/CMSIS/include/arm_common_tables.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------

-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.

-*

-* $Date:        19. October 2015

-* $Revision: 	V.1.4.5 a

-*

-* Project: 	    CMSIS DSP Library

-* Title:	    arm_common_tables.h

-*

-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions

-*

-* Target Processor: Cortex-M4/Cortex-M3

-*

-* Redistribution and use in source and binary forms, with or without

-* modification, are permitted provided that the following conditions

-* are met:

-*   - Redistributions of source code must retain the above copyright

-*     notice, this list of conditions and the following disclaimer.

-*   - Redistributions in binary form must reproduce the above copyright

-*     notice, this list of conditions and the following disclaimer in

-*     the documentation and/or other materials provided with the

-*     distribution.

-*   - Neither the name of ARM LIMITED nor the names of its contributors

-*     may be used to endorse or promote products derived from this

-*     software without specific prior written permission.

-*

-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-* POSSIBILITY OF SUCH DAMAGE.

-* -------------------------------------------------------------------- */

-

-#ifndef _ARM_COMMON_TABLES_H

-#define _ARM_COMMON_TABLES_H

-

-#include "arm_math.h"

-

-extern const uint16_t armBitRevTable[1024];

-extern const q15_t armRecipTableQ15[64];

-extern const q31_t armRecipTableQ31[64];

-/* extern const q31_t realCoefAQ31[1024]; */

-/* extern const q31_t realCoefBQ31[1024]; */

-extern const float32_t twiddleCoef_16[32];

-extern const float32_t twiddleCoef_32[64];

-extern const float32_t twiddleCoef_64[128];

-extern const float32_t twiddleCoef_128[256];

-extern const float32_t twiddleCoef_256[512];

-extern const float32_t twiddleCoef_512[1024];

-extern const float32_t twiddleCoef_1024[2048];

-extern const float32_t twiddleCoef_2048[4096];

-extern const float32_t twiddleCoef_4096[8192];

-#define twiddleCoef twiddleCoef_4096

-extern const q31_t twiddleCoef_16_q31[24];

-extern const q31_t twiddleCoef_32_q31[48];

-extern const q31_t twiddleCoef_64_q31[96];

-extern const q31_t twiddleCoef_128_q31[192];

-extern const q31_t twiddleCoef_256_q31[384];

-extern const q31_t twiddleCoef_512_q31[768];

-extern const q31_t twiddleCoef_1024_q31[1536];

-extern const q31_t twiddleCoef_2048_q31[3072];

-extern const q31_t twiddleCoef_4096_q31[6144];

-extern const q15_t twiddleCoef_16_q15[24];

-extern const q15_t twiddleCoef_32_q15[48];

-extern const q15_t twiddleCoef_64_q15[96];

-extern const q15_t twiddleCoef_128_q15[192];

-extern const q15_t twiddleCoef_256_q15[384];

-extern const q15_t twiddleCoef_512_q15[768];

-extern const q15_t twiddleCoef_1024_q15[1536];

-extern const q15_t twiddleCoef_2048_q15[3072];

-extern const q15_t twiddleCoef_4096_q15[6144];

-extern const float32_t twiddleCoef_rfft_32[32];

-extern const float32_t twiddleCoef_rfft_64[64];

-extern const float32_t twiddleCoef_rfft_128[128];

-extern const float32_t twiddleCoef_rfft_256[256];

-extern const float32_t twiddleCoef_rfft_512[512];

-extern const float32_t twiddleCoef_rfft_1024[1024];

-extern const float32_t twiddleCoef_rfft_2048[2048];

-extern const float32_t twiddleCoef_rfft_4096[4096];

-

-

-/* floating-point bit reversal tables */

-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )

-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )

-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )

-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )

-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )

-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )

-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)

-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)

-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)

-

-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];

-

-/* fixed-point bit reversal tables */

-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )

-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )

-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )

-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )

-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )

-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )

-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )

-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)

-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)

-

-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];

-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];

-

-/* Tables for Fast Math Sine and Cosine */

-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];

-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];

-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];

-

-#endif /*  ARM_COMMON_TABLES_H */

diff --git a/os/common/ext/CMSIS/include/arm_const_structs.h b/os/common/ext/CMSIS/include/arm_const_structs.h
deleted file mode 100644
index 54595f55d..000000000
--- a/os/common/ext/CMSIS/include/arm_const_structs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------

-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.

-*

-* $Date:        19. March 2015

-* $Revision: 	V.1.4.5

-*

-* Project: 	    CMSIS DSP Library

-* Title:	    arm_const_structs.h

-*

-* Description:	This file has constant structs that are initialized for

-*              user convenience.  For example, some can be given as

-*              arguments to the arm_cfft_f32() function.

-*

-* Target Processor: Cortex-M4/Cortex-M3

-*

-* Redistribution and use in source and binary forms, with or without

-* modification, are permitted provided that the following conditions

-* are met:

-*   - Redistributions of source code must retain the above copyright

-*     notice, this list of conditions and the following disclaimer.

-*   - Redistributions in binary form must reproduce the above copyright

-*     notice, this list of conditions and the following disclaimer in

-*     the documentation and/or other materials provided with the

-*     distribution.

-*   - Neither the name of ARM LIMITED nor the names of its contributors

-*     may be used to endorse or promote products derived from this

-*     software without specific prior written permission.

-*

-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-* POSSIBILITY OF SUCH DAMAGE.

-* -------------------------------------------------------------------- */

-

-#ifndef _ARM_CONST_STRUCTS_H

-#define _ARM_CONST_STRUCTS_H

-

-#include "arm_math.h"

-#include "arm_common_tables.h"

-

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;

-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;

-

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;

-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;

-

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;

-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;

-

-#endif

diff --git a/os/common/ext/CMSIS/include/arm_math.h b/os/common/ext/CMSIS/include/arm_math.h
deleted file mode 100644
index 580cbbde6..000000000
--- a/os/common/ext/CMSIS/include/arm_math.h
+++ /dev/null
@@ -1,7154 +0,0 @@
-/* ----------------------------------------------------------------------

-* Copyright (C) 2010-2015 ARM Limited. All rights reserved.

-*

-* $Date:        20. October 2015

-* $Revision:    V1.4.5 b

-*

-* Project:      CMSIS DSP Library

-* Title:        arm_math.h

-*

-* Description:  Public header file for CMSIS DSP Library

-*

-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0

-*

-* Redistribution and use in source and binary forms, with or without

-* modification, are permitted provided that the following conditions

-* are met:

-*   - Redistributions of source code must retain the above copyright

-*     notice, this list of conditions and the following disclaimer.

-*   - Redistributions in binary form must reproduce the above copyright

-*     notice, this list of conditions and the following disclaimer in

-*     the documentation and/or other materials provided with the

-*     distribution.

-*   - Neither the name of ARM LIMITED nor the names of its contributors

-*     may be used to endorse or promote products derived from this

-*     software without specific prior written permission.

-*

-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,

-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN

-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-* POSSIBILITY OF SUCH DAMAGE.

- * -------------------------------------------------------------------- */

-

-/**

-   \mainpage CMSIS DSP Software Library

-   *

-   * Introduction

-   * ------------

-   *

-   * This user manual describes the CMSIS DSP software library,

-   * a suite of common signal processing functions for use on Cortex-M processor based devices.

-   *

-   * The library is divided into a number of functions each covering a specific category:

-   * - Basic math functions

-   * - Fast math functions

-   * - Complex math functions

-   * - Filters

-   * - Matrix functions

-   * - Transforms

-   * - Motor control functions

-   * - Statistical functions

-   * - Support functions

-   * - Interpolation functions

-   *

-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,

-   * 32-bit integer and 32-bit floating-point values.

-   *

-   * Using the Library

-   * ------------

-   *

-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.

-   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)

-   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)

-   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)

-   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)

-   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)

-   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)

-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)

-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)

-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)

-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)

-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)

-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)

-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)

-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)

-   *

-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.

-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single

-   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.

-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or

-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.

-   *

-   * Examples

-   * --------

-   *

-   * The library ships with a number of examples which demonstrate how to use the library functions.

-   *

-   * Toolchain Support

-   * ------------

-   *

-   * The library has been developed and tested with MDK-ARM version 5.14.0.0

-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.

-   *

-   * Building the Library

-   * ------------

-   *

-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.

-   * - arm_cortexM_math.uvprojx

-   *

-   *

-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.

-   *

-   * Pre-processor Macros

-   * ------------

-   *

-   * Each library project have differant pre-processor macros.

-   *

-   * - UNALIGNED_SUPPORT_DISABLE:

-   *

-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access

-   *

-   * - ARM_MATH_BIG_ENDIAN:

-   *

-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.

-   *

-   * - ARM_MATH_MATRIX_CHECK:

-   *

-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices

-   *

-   * - ARM_MATH_ROUNDING:

-   *

-   * Define macro ARM_MATH_ROUNDING for rounding on support functions

-   *

-   * - ARM_MATH_CMx:

-   *

-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target

-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and

-   * ARM_MATH_CM7 for building the library on cortex-M7.

-   *

-   * - __FPU_PRESENT:

-   *

-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries

-   *

-   * <hr>

-   * CMSIS-DSP in ARM::CMSIS Pack

-   * -----------------------------

-   *

-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:

-   * |File/Folder                   |Content                                                                 |

-   * |------------------------------|------------------------------------------------------------------------|

-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |

-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |

-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |

-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |

-   *

-   * <hr>

-   * Revision History of CMSIS-DSP

-   * ------------

-   * Please refer to \ref ChangeLog_pg.

-   *

-   * Copyright Notice

-   * ------------

-   *

-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.

-   */

-

-

-/**

- * @defgroup groupMath Basic Math Functions

- */

-

-/**

- * @defgroup groupFastMath Fast Math Functions

- * This set of functions provides a fast approximation to sine, cosine, and square root.

- * As compared to most of the other functions in the CMSIS math library, the fast math functions

- * operate on individual values and not arrays.

- * There are separate functions for Q15, Q31, and floating-point data.

- *

- */

-

-/**

- * @defgroup groupCmplxMath Complex Math Functions

- * This set of functions operates on complex data vectors.

- * The data in the complex arrays is stored in an interleaved fashion

- * (real, imag, real, imag, ...).

- * In the API functions, the number of samples in a complex array refers

- * to the number of complex values; the array contains twice this number of

- * real values.

- */

-

-/**

- * @defgroup groupFilters Filtering Functions

- */

-

-/**

- * @defgroup groupMatrix Matrix Functions

- *

- * This set of functions provides basic matrix math operations.

- * The functions operate on matrix data structures.  For example,

- * the type

- * definition for the floating-point matrix structure is shown

- * below:

- * <pre>

- *     typedef struct

- *     {

- *       uint16_t numRows;     // number of rows of the matrix.

- *       uint16_t numCols;     // number of columns of the matrix.

- *       float32_t *pData;     // points to the data of the matrix.

- *     } arm_matrix_instance_f32;

- * </pre>

- * There are similar definitions for Q15 and Q31 data types.

- *

- * The structure specifies the size of the matrix and then points to

- * an array of data.  The array is of size <code>numRows X numCols</code>

- * and the values are arranged in row order.  That is, the

- * matrix element (i, j) is stored at:

- * <pre>

- *     pData[i*numCols + j]

- * </pre>

- *

- * \par Init Functions

- * There is an associated initialization function for each type of matrix

- * data structure.

- * The initialization function sets the values of the internal structure fields.

- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>

- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.

- *

- * \par

- * Use of the initialization function is optional. However, if initialization function is used

- * then the instance structure cannot be placed into a const data section.

- * To place the instance structure in a const data

- * section, manually initialize the data structure.  For example:

- * <pre>

- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>

- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>

- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>

- * </pre>

- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>

- * specifies the number of columns, and <code>pData</code> points to the

- * data array.

- *

- * \par Size Checking

- * By default all of the matrix functions perform size checking on the input and

- * output matrices.  For example, the matrix addition function verifies that the

- * two input matrices and the output matrix all have the same number of rows and

- * columns.  If the size check fails the functions return:

- * <pre>

- *     ARM_MATH_SIZE_MISMATCH

- * </pre>

- * Otherwise the functions return

- * <pre>

- *     ARM_MATH_SUCCESS

- * </pre>

- * There is some overhead associated with this matrix size checking.

- * The matrix size checking is enabled via the \#define

- * <pre>

- *     ARM_MATH_MATRIX_CHECK

- * </pre>

- * within the library project settings.  By default this macro is defined

- * and size checking is enabled.  By changing the project settings and

- * undefining this macro size checking is eliminated and the functions

- * run a bit faster.  With size checking disabled the functions always

- * return <code>ARM_MATH_SUCCESS</code>.

- */

-

-/**

- * @defgroup groupTransforms Transform Functions

- */

-

-/**

- * @defgroup groupController Controller Functions

- */

-

-/**

- * @defgroup groupStats Statistics Functions

- */

-/**

- * @defgroup groupSupport Support Functions

- */

-

-/**

- * @defgroup groupInterpolation Interpolation Functions

- * These functions perform 1- and 2-dimensional interpolation of data.

- * Linear interpolation is used for 1-dimensional data and

- * bilinear interpolation is used for 2-dimensional data.

- */

-

-/**

- * @defgroup groupExamples Examples

- */

-#ifndef _ARM_MATH_H

-#define _ARM_MATH_H

-

-/* ignore some GCC warnings */

-#if defined ( __GNUC__ )

-#pragma GCC diagnostic push

-#pragma GCC diagnostic ignored "-Wsign-conversion"

-#pragma GCC diagnostic ignored "-Wconversion"

-#pragma GCC diagnostic ignored "-Wunused-parameter"

-#endif

-

-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */

-

-#if defined(ARM_MATH_CM7)

-  #include "core_cm7.h"

-#elif defined (ARM_MATH_CM4)

-  #include "core_cm4.h"

-#elif defined (ARM_MATH_CM3)

-  #include "core_cm3.h"

-#elif defined (ARM_MATH_CM0)

-  #include "core_cm0.h"

-  #define ARM_MATH_CM0_FAMILY

-#elif defined (ARM_MATH_CM0PLUS)

-  #include "core_cm0plus.h"

-  #define ARM_MATH_CM0_FAMILY

-#else

-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"

-#endif

-

-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */

-#include "string.h"

-#include "math.h"

-#ifdef   __cplusplus

-extern "C"

-{

-#endif

-

-

-  /**

-   * @brief Macros required for reciprocal calculation in Normalized LMS

-   */

-

-#define DELTA_Q31          (0x100)

-#define DELTA_Q15          0x5

-#define INDEX_MASK         0x0000003F

-#ifndef PI

-#define PI                 3.14159265358979f

-#endif

-

-  /**

-   * @brief Macros required for SINE and COSINE Fast math approximations

-   */

-

-#define FAST_MATH_TABLE_SIZE  512

-#define FAST_MATH_Q31_SHIFT   (32 - 10)

-#define FAST_MATH_Q15_SHIFT   (16 - 10)

-#define CONTROLLER_Q31_SHIFT  (32 - 9)

-#define TABLE_SIZE  256

-#define TABLE_SPACING_Q31     0x400000

-#define TABLE_SPACING_Q15     0x80

-

-  /**

-   * @brief Macros required for SINE and COSINE Controller functions

-   */

-  /* 1.31(q31) Fixed value of 2/360 */

-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */

-#define INPUT_SPACING         0xB60B61

-

-  /**

-   * @brief Macro for Unaligned Support

-   */

-#ifndef UNALIGNED_SUPPORT_DISABLE

-    #define ALIGN4

-#else

-  #if defined  (__GNUC__)

-    #define ALIGN4 __attribute__((aligned(4)))

-  #else

-    #define ALIGN4 __align(4)

-  #endif

-#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */

-

-  /**

-   * @brief Error status returned by some functions in the library.

-   */

-

-  typedef enum

-  {

-    ARM_MATH_SUCCESS = 0,                /**< No error */

-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */

-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */

-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */

-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */

-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */

-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */

-  } arm_status;

-

-  /**

-   * @brief 8-bit fractional data type in 1.7 format.

-   */

-  typedef int8_t q7_t;

-

-  /**

-   * @brief 16-bit fractional data type in 1.15 format.

-   */

-  typedef int16_t q15_t;

-

-  /**

-   * @brief 32-bit fractional data type in 1.31 format.

-   */

-  typedef int32_t q31_t;

-

-  /**

-   * @brief 64-bit fractional data type in 1.63 format.

-   */

-  typedef int64_t q63_t;

-

-  /**

-   * @brief 32-bit floating-point type definition.

-   */

-  typedef float float32_t;

-

-  /**

-   * @brief 64-bit floating-point type definition.

-   */

-  typedef double float64_t;

-

-  /**

-   * @brief definition to read/write two 16 bit values.

-   */

-#if defined __CC_ARM

-  #define __SIMD32_TYPE int32_t __packed

-  #define CMSIS_UNUSED __attribute__((unused))

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define __SIMD32_TYPE int32_t

-  #define CMSIS_UNUSED __attribute__((unused))

-

-#elif defined __GNUC__

-  #define __SIMD32_TYPE int32_t

-  #define CMSIS_UNUSED __attribute__((unused))

-

-#elif defined __ICCARM__

-  #define __SIMD32_TYPE int32_t __packed

-  #define CMSIS_UNUSED

-

-#elif defined __CSMC__

-  #define __SIMD32_TYPE int32_t

-  #define CMSIS_UNUSED

-

-#elif defined __TASKING__

-  #define __SIMD32_TYPE __unaligned int32_t

-  #define CMSIS_UNUSED

-

-#else

-  #error Unknown compiler

-#endif

-

-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))

-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))

-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))

-#define __SIMD64(addr)        (*(int64_t **) & (addr))

-

-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)

-  /**

-   * @brief definition to pack two 16 bit values.

-   */

-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \

-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )

-#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \

-                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )

-

-#endif

-

-

-   /**

-   * @brief definition to pack four 8 bit values.

-   */

-#ifndef ARM_MATH_BIG_ENDIAN

-

-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \

-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \

-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \

-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )

-#else

-

-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \

-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \

-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \

-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )

-

-#endif

-

-

-  /**

-   * @brief Clips Q63 to Q31 values.

-   */

-  static __INLINE q31_t clip_q63_to_q31(

-  q63_t x)

-  {

-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?

-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;

-  }

-

-  /**

-   * @brief Clips Q63 to Q15 values.

-   */

-  static __INLINE q15_t clip_q63_to_q15(

-  q63_t x)

-  {

-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?

-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);

-  }

-

-  /**

-   * @brief Clips Q31 to Q7 values.

-   */

-  static __INLINE q7_t clip_q31_to_q7(

-  q31_t x)

-  {

-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?

-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;

-  }

-

-  /**

-   * @brief Clips Q31 to Q15 values.

-   */

-  static __INLINE q15_t clip_q31_to_q15(

-  q31_t x)

-  {

-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?

-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;

-  }

-

-  /**

-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.

-   */

-

-  static __INLINE q63_t mult32x64(

-  q63_t x,

-  q31_t y)

-  {

-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +

-            (((q63_t) (x >> 32) * y)));

-  }

-

-/*

-  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )

-  #define __CLZ __clz

-  #endif

- */

-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */

-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )

-  static __INLINE uint32_t __CLZ(

-  q31_t data);

-

-  static __INLINE uint32_t __CLZ(

-  q31_t data)

-  {

-    uint32_t count = 0;

-    uint32_t mask = 0x80000000;

-

-    while((data & mask) == 0)

-    {

-      count += 1u;

-      mask = mask >> 1u;

-    }

-

-    return (count);

-  }

-#endif

-

-  /**

-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.

-   */

-

-  static __INLINE uint32_t arm_recip_q31(

-  q31_t in,

-  q31_t * dst,

-  q31_t * pRecipTable)

-  {

-    q31_t out;

-    uint32_t tempVal;

-    uint32_t index, i;

-    uint32_t signBits;

-

-    if(in > 0)

-    {

-      signBits = ((uint32_t) (__CLZ( in) - 1));

-    }

-    else

-    {

-      signBits = ((uint32_t) (__CLZ(-in) - 1));

-    }

-

-    /* Convert input sample to 1.31 format */

-    in = (in << signBits);

-

-    /* calculation of index for initial approximated Val */

-    index = (uint32_t)(in >> 24);

-    index = (index & INDEX_MASK);

-

-    /* 1.31 with exp 1 */

-    out = pRecipTable[index];

-

-    /* calculation of reciprocal value */

-    /* running approximation for two iterations */

-    for (i = 0u; i < 2u; i++)

-    {

-      tempVal = (uint32_t) (((q63_t) in * out) >> 31);

-      tempVal = 0x7FFFFFFFu - tempVal;

-      /*      1.31 with exp 1 */

-      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */

-      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);

-    }

-

-    /* write output */

-    *dst = out;

-

-    /* return num of signbits of out = 1/in value */

-    return (signBits + 1u);

-  }

-

-

-  /**

-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.

-   */

-  static __INLINE uint32_t arm_recip_q15(

-  q15_t in,

-  q15_t * dst,

-  q15_t * pRecipTable)

-  {

-    q15_t out = 0;

-    uint32_t tempVal = 0;

-    uint32_t index = 0, i = 0;

-    uint32_t signBits = 0;

-

-    if(in > 0)

-    {

-      signBits = ((uint32_t)(__CLZ( in) - 17));

-    }

-    else

-    {

-      signBits = ((uint32_t)(__CLZ(-in) - 17));

-    }

-

-    /* Convert input sample to 1.15 format */

-    in = (in << signBits);

-

-    /* calculation of index for initial approximated Val */

-    index = (uint32_t)(in >>  8);

-    index = (index & INDEX_MASK);

-

-    /*      1.15 with exp 1  */

-    out = pRecipTable[index];

-

-    /* calculation of reciprocal value */

-    /* running approximation for two iterations */

-    for (i = 0u; i < 2u; i++)

-    {

-      tempVal = (uint32_t) (((q31_t) in * out) >> 15);

-      tempVal = 0x7FFFu - tempVal;

-      /*      1.15 with exp 1 */

-      out = (q15_t) (((q31_t) out * tempVal) >> 14);

-      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */

-    }

-

-    /* write output */

-    *dst = out;

-

-    /* return num of signbits of out = 1/in value */

-    return (signBits + 1);

-  }

-

-

-  /*

-   * @brief C custom defined intrinisic function for only M0 processors

-   */

-#if defined(ARM_MATH_CM0_FAMILY)

-  static __INLINE q31_t __SSAT(

-  q31_t x,

-  uint32_t y)

-  {

-    int32_t posMax, negMin;

-    uint32_t i;

-

-    posMax = 1;

-    for (i = 0; i < (y - 1); i++)

-    {

-      posMax = posMax * 2;

-    }

-

-    if(x > 0)

-    {

-      posMax = (posMax - 1);

-

-      if(x > posMax)

-      {

-        x = posMax;

-      }

-    }

-    else

-    {

-      negMin = -posMax;

-

-      if(x < negMin)

-      {

-        x = negMin;

-      }

-    }

-    return (x);

-  }

-#endif /* end of ARM_MATH_CM0_FAMILY */

-

-

-  /*

-   * @brief C custom defined intrinsic function for M3 and M0 processors

-   */

-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)

-

-  /*

-   * @brief C custom defined QADD8 for M3 and M0 processors

-   */

-  static __INLINE uint32_t __QADD8(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s, t, u;

-

-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;

-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;

-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;

-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;

-

-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined QSUB8 for M3 and M0 processors

-   */

-  static __INLINE uint32_t __QSUB8(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s, t, u;

-

-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;

-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;

-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;

-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;

-

-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined QADD16 for M3 and M0 processors

-   */

-  static __INLINE uint32_t __QADD16(

-  uint32_t x,

-  uint32_t y)

-  {

-/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */

-    q31_t r = 0, s = 0;

-

-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;

-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined SHADD16 for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SHADD16(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s;

-

-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined QSUB16 for M3 and M0 processors

-   */

-  static __INLINE uint32_t __QSUB16(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s;

-

-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;

-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined SHSUB16 for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SHSUB16(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s;

-

-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined QASX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __QASX(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s;

-

-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;

-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined SHASX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SHASX(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s;

-

-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined QSAX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __QSAX(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s;

-

-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;

-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined SHSAX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SHSAX(

-  uint32_t x,

-  uint32_t y)

-  {

-    q31_t r, s;

-

-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;

-

-    return ((uint32_t)((s << 16) | (r      )));

-  }

-

-

-  /*

-   * @brief C custom defined SMUSDX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SMUSDX(

-  uint32_t x,

-  uint32_t y)

-  {

-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));

-  }

-

-  /*

-   * @brief C custom defined SMUADX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SMUADX(

-  uint32_t x,

-  uint32_t y)

-  {

-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));

-  }

-

-

-  /*

-   * @brief C custom defined QADD for M3 and M0 processors

-   */

-  static __INLINE int32_t __QADD(

-  int32_t x,

-  int32_t y)

-  {

-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));

-  }

-

-

-  /*

-   * @brief C custom defined QSUB for M3 and M0 processors

-   */

-  static __INLINE int32_t __QSUB(

-  int32_t x,

-  int32_t y)

-  {

-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));

-  }

-

-

-  /*

-   * @brief C custom defined SMLAD for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SMLAD(

-  uint32_t x,

-  uint32_t y,

-  uint32_t sum)

-  {

-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +

-                       ( ((q31_t)sum    )                                  )   ));

-  }

-

-

-  /*

-   * @brief C custom defined SMLADX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SMLADX(

-  uint32_t x,

-  uint32_t y,

-  uint32_t sum)

-  {

-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +

-                       ( ((q31_t)sum    )                                  )   ));

-  }

-

-

-  /*

-   * @brief C custom defined SMLSDX for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SMLSDX(

-  uint32_t x,

-  uint32_t y,

-  uint32_t sum)

-  {

-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +

-                       ( ((q31_t)sum    )                                  )   ));

-  }

-

-

-  /*

-   * @brief C custom defined SMLALD for M3 and M0 processors

-   */

-  static __INLINE uint64_t __SMLALD(

-  uint32_t x,

-  uint32_t y,

-  uint64_t sum)

-  {

-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */

-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +

-                       ( ((q63_t)sum    )                                  )   ));

-  }

-

-

-  /*

-   * @brief C custom defined SMLALDX for M3 and M0 processors

-   */

-  static __INLINE uint64_t __SMLALDX(

-  uint32_t x,

-  uint32_t y,

-  uint64_t sum)

-  {

-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */

-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +

-                       ( ((q63_t)sum    )                                  )   ));

-  }

-

-

-  /*

-   * @brief C custom defined SMUAD for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SMUAD(

-  uint32_t x,

-  uint32_t y)

-  {

-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));

-  }

-

-

-  /*

-   * @brief C custom defined SMUSD for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SMUSD(

-  uint32_t x,

-  uint32_t y)

-  {

-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -

-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));

-  }

-

-

-  /*

-   * @brief C custom defined SXTB16 for M3 and M0 processors

-   */

-  static __INLINE uint32_t __SXTB16(

-  uint32_t x)

-  {

-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |

-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));

-  }

-

-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */

-

-

-  /**

-   * @brief Instance structure for the Q7 FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */

-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/

-  } arm_fir_instance_q7;

-

-  /**

-   * @brief Instance structure for the Q15 FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */

-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/

-  } arm_fir_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */

-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */

-  } arm_fir_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */

-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */

-  } arm_fir_instance_f32;

-

-

-  /**

-   * @brief Processing function for the Q7 FIR filter.

-   * @param[in]  S          points to an instance of the Q7 FIR filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_q7(

-  const arm_fir_instance_q7 * S,

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q7 FIR filter.

-   * @param[in,out] S          points to an instance of the Q7 FIR structure.

-   * @param[in]     numTaps    Number of filter coefficients in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of samples that are processed.

-   */

-  void arm_fir_init_q7(

-  arm_fir_instance_q7 * S,

-  uint16_t numTaps,

-  q7_t * pCoeffs,

-  q7_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q15 FIR filter.

-   * @param[in]  S          points to an instance of the Q15 FIR structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_q15(

-  const arm_fir_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.

-   * @param[in]  S          points to an instance of the Q15 FIR filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_fast_q15(

-  const arm_fir_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q15 FIR filter.

-   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.

-   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of samples that are processed at a time.

-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if

-   * <code>numTaps</code> is not a supported value.

-   */

-  arm_status arm_fir_init_q15(

-  arm_fir_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 FIR filter.

-   * @param[in]  S          points to an instance of the Q31 FIR filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_q31(

-  const arm_fir_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.

-   * @param[in]  S          points to an instance of the Q31 FIR structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_fast_q31(

-  const arm_fir_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q31 FIR filter.

-   * @param[in,out] S          points to an instance of the Q31 FIR structure.

-   * @param[in]     numTaps    Number of filter coefficients in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of samples that are processed at a time.

-   */

-  void arm_fir_init_q31(

-  arm_fir_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the floating-point FIR filter.

-   * @param[in]  S          points to an instance of the floating-point FIR structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_f32(

-  const arm_fir_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point FIR filter.

-   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.

-   * @param[in]     numTaps    Number of filter coefficients in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of samples that are processed at a time.

-   */

-  void arm_fir_init_f32(

-  arm_fir_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q15 Biquad cascade filter.

-   */

-  typedef struct

-  {

-    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */

-    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */

-    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */

-  } arm_biquad_casd_df1_inst_q15;

-

-  /**

-   * @brief Instance structure for the Q31 Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */

-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */

-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */

-  } arm_biquad_casd_df1_inst_q31;

-

-  /**

-   * @brief Instance structure for the floating-point Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */

-    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */

-  } arm_biquad_casd_df1_inst_f32;

-

-

-  /**

-   * @brief Processing function for the Q15 Biquad cascade filter.

-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_df1_q15(

-  const arm_biquad_casd_df1_inst_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q15 Biquad cascade filter.

-   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.

-   * @param[in]     numStages  number of 2nd order stages in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format

-   */

-  void arm_biquad_cascade_df1_init_q15(

-  arm_biquad_casd_df1_inst_q15 * S,

-  uint8_t numStages,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  int8_t postShift);

-

-

-  /**

-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.

-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_df1_fast_q15(

-  const arm_biquad_casd_df1_inst_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 Biquad cascade filter

-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_df1_q31(

-  const arm_biquad_casd_df1_inst_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.

-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_df1_fast_q31(

-  const arm_biquad_casd_df1_inst_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q31 Biquad cascade filter.

-   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.

-   * @param[in]     numStages  number of 2nd order stages in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format

-   */

-  void arm_biquad_cascade_df1_init_q31(

-  arm_biquad_casd_df1_inst_q31 * S,

-  uint8_t numStages,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  int8_t postShift);

-

-

-  /**

-   * @brief Processing function for the floating-point Biquad cascade filter.

-   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_df1_f32(

-  const arm_biquad_casd_df1_inst_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point Biquad cascade filter.

-   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.

-   * @param[in]     numStages  number of 2nd order stages in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   */

-  void arm_biquad_cascade_df1_init_f32(

-  arm_biquad_casd_df1_inst_f32 * S,

-  uint8_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-

-  /**

-   * @brief Instance structure for the floating-point matrix structure.

-   */

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    float32_t *pData;     /**< points to the data of the matrix. */

-  } arm_matrix_instance_f32;

-

-

-  /**

-   * @brief Instance structure for the floating-point matrix structure.

-   */

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    float64_t *pData;     /**< points to the data of the matrix. */

-  } arm_matrix_instance_f64;

-

-  /**

-   * @brief Instance structure for the Q15 matrix structure.

-   */

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    q15_t *pData;         /**< points to the data of the matrix. */

-  } arm_matrix_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 matrix structure.

-   */

-  typedef struct

-  {

-    uint16_t numRows;     /**< number of rows of the matrix.     */

-    uint16_t numCols;     /**< number of columns of the matrix.  */

-    q31_t *pData;         /**< points to the data of the matrix. */

-  } arm_matrix_instance_q31;

-

-

-  /**

-   * @brief Floating-point matrix addition.

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_add_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-

-  /**

-   * @brief Q15 matrix addition.

-   * @param[in]   pSrcA  points to the first input matrix structure

-   * @param[in]   pSrcB  points to the second input matrix structure

-   * @param[out]  pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_add_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst);

-

-

-  /**

-   * @brief Q31 matrix addition.

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_add_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point, complex, matrix multiplication.

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_cmplx_mult_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-

-  /**

-   * @brief Q15, complex,  matrix multiplication.

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_cmplx_mult_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst,

-  q15_t * pScratch);

-

-

-  /**

-   * @brief Q31, complex, matrix multiplication.

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_cmplx_mult_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point matrix transpose.

-   * @param[in]  pSrc  points to the input matrix

-   * @param[out] pDst  points to the output matrix

-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>

-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_trans_f32(

-  const arm_matrix_instance_f32 * pSrc,

-  arm_matrix_instance_f32 * pDst);

-

-

-  /**

-   * @brief Q15 matrix transpose.

-   * @param[in]  pSrc  points to the input matrix

-   * @param[out] pDst  points to the output matrix

-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>

-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_trans_q15(

-  const arm_matrix_instance_q15 * pSrc,

-  arm_matrix_instance_q15 * pDst);

-

-

-  /**

-   * @brief Q31 matrix transpose.

-   * @param[in]  pSrc  points to the input matrix

-   * @param[out] pDst  points to the output matrix

-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>

-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_trans_q31(

-  const arm_matrix_instance_q31 * pSrc,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point matrix multiplication

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_mult_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-

-  /**

-   * @brief Q15 matrix multiplication

-   * @param[in]  pSrcA   points to the first input matrix structure

-   * @param[in]  pSrcB   points to the second input matrix structure

-   * @param[out] pDst    points to output matrix structure

-   * @param[in]  pState  points to the array for storing intermediate results

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_mult_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst,

-  q15_t * pState);

-

-

-  /**

-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA   points to the first input matrix structure

-   * @param[in]  pSrcB   points to the second input matrix structure

-   * @param[out] pDst    points to output matrix structure

-   * @param[in]  pState  points to the array for storing intermediate results

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_mult_fast_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst,

-  q15_t * pState);

-

-

-  /**

-   * @brief Q31 matrix multiplication

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_mult_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_mult_fast_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point matrix subtraction

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_sub_f32(

-  const arm_matrix_instance_f32 * pSrcA,

-  const arm_matrix_instance_f32 * pSrcB,

-  arm_matrix_instance_f32 * pDst);

-

-

-  /**

-   * @brief Q15 matrix subtraction

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_sub_q15(

-  const arm_matrix_instance_q15 * pSrcA,

-  const arm_matrix_instance_q15 * pSrcB,

-  arm_matrix_instance_q15 * pDst);

-

-

-  /**

-   * @brief Q31 matrix subtraction

-   * @param[in]  pSrcA  points to the first input matrix structure

-   * @param[in]  pSrcB  points to the second input matrix structure

-   * @param[out] pDst   points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_sub_q31(

-  const arm_matrix_instance_q31 * pSrcA,

-  const arm_matrix_instance_q31 * pSrcB,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief Floating-point matrix scaling.

-   * @param[in]  pSrc   points to the input matrix

-   * @param[in]  scale  scale factor

-   * @param[out] pDst   points to the output matrix

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_scale_f32(

-  const arm_matrix_instance_f32 * pSrc,

-  float32_t scale,

-  arm_matrix_instance_f32 * pDst);

-

-

-  /**

-   * @brief Q15 matrix scaling.

-   * @param[in]  pSrc        points to input matrix

-   * @param[in]  scaleFract  fractional portion of the scale factor

-   * @param[in]  shift       number of bits to shift the result by

-   * @param[out] pDst        points to output matrix

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_scale_q15(

-  const arm_matrix_instance_q15 * pSrc,

-  q15_t scaleFract,

-  int32_t shift,

-  arm_matrix_instance_q15 * pDst);

-

-

-  /**

-   * @brief Q31 matrix scaling.

-   * @param[in]  pSrc        points to input matrix

-   * @param[in]  scaleFract  fractional portion of the scale factor

-   * @param[in]  shift       number of bits to shift the result by

-   * @param[out] pDst        points to output matrix structure

-   * @return     The function returns either

-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.

-   */

-  arm_status arm_mat_scale_q31(

-  const arm_matrix_instance_q31 * pSrc,

-  q31_t scaleFract,

-  int32_t shift,

-  arm_matrix_instance_q31 * pDst);

-

-

-  /**

-   * @brief  Q31 matrix initialization.

-   * @param[in,out] S         points to an instance of the floating-point matrix structure.

-   * @param[in]     nRows     number of rows in the matrix.

-   * @param[in]     nColumns  number of columns in the matrix.

-   * @param[in]     pData     points to the matrix data array.

-   */

-  void arm_mat_init_q31(

-  arm_matrix_instance_q31 * S,

-  uint16_t nRows,

-  uint16_t nColumns,

-  q31_t * pData);

-

-

-  /**

-   * @brief  Q15 matrix initialization.

-   * @param[in,out] S         points to an instance of the floating-point matrix structure.

-   * @param[in]     nRows     number of rows in the matrix.

-   * @param[in]     nColumns  number of columns in the matrix.

-   * @param[in]     pData     points to the matrix data array.

-   */

-  void arm_mat_init_q15(

-  arm_matrix_instance_q15 * S,

-  uint16_t nRows,

-  uint16_t nColumns,

-  q15_t * pData);

-

-

-  /**

-   * @brief  Floating-point matrix initialization.

-   * @param[in,out] S         points to an instance of the floating-point matrix structure.

-   * @param[in]     nRows     number of rows in the matrix.

-   * @param[in]     nColumns  number of columns in the matrix.

-   * @param[in]     pData     points to the matrix data array.

-   */

-  void arm_mat_init_f32(

-  arm_matrix_instance_f32 * S,

-  uint16_t nRows,

-  uint16_t nColumns,

-  float32_t * pData);

-

-

-

-  /**

-   * @brief Instance structure for the Q15 PID Control.

-   */

-  typedef struct

-  {

-    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */

-#ifdef ARM_MATH_CM0_FAMILY

-    q15_t A1;

-    q15_t A2;

-#else

-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/

-#endif

-    q15_t state[3];     /**< The state array of length 3. */

-    q15_t Kp;           /**< The proportional gain. */

-    q15_t Ki;           /**< The integral gain. */

-    q15_t Kd;           /**< The derivative gain. */

-  } arm_pid_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 PID Control.

-   */

-  typedef struct

-  {

-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */

-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */

-    q31_t A2;            /**< The derived gain, A2 = Kd . */

-    q31_t state[3];      /**< The state array of length 3. */

-    q31_t Kp;            /**< The proportional gain. */

-    q31_t Ki;            /**< The integral gain. */

-    q31_t Kd;            /**< The derivative gain. */

-  } arm_pid_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point PID Control.

-   */

-  typedef struct

-  {

-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */

-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */

-    float32_t A2;          /**< The derived gain, A2 = Kd . */

-    float32_t state[3];    /**< The state array of length 3. */

-    float32_t Kp;          /**< The proportional gain. */

-    float32_t Ki;          /**< The integral gain. */

-    float32_t Kd;          /**< The derivative gain. */

-  } arm_pid_instance_f32;

-

-

-

-  /**

-   * @brief  Initialization function for the floating-point PID Control.

-   * @param[in,out] S               points to an instance of the PID structure.

-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.

-   */

-  void arm_pid_init_f32(

-  arm_pid_instance_f32 * S,

-  int32_t resetStateFlag);

-

-

-  /**

-   * @brief  Reset function for the floating-point PID Control.

-   * @param[in,out] S  is an instance of the floating-point PID Control structure

-   */

-  void arm_pid_reset_f32(

-  arm_pid_instance_f32 * S);

-

-

-  /**

-   * @brief  Initialization function for the Q31 PID Control.

-   * @param[in,out] S               points to an instance of the Q15 PID structure.

-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.

-   */

-  void arm_pid_init_q31(

-  arm_pid_instance_q31 * S,

-  int32_t resetStateFlag);

-

-

-  /**

-   * @brief  Reset function for the Q31 PID Control.

-   * @param[in,out] S   points to an instance of the Q31 PID Control structure

-   */

-

-  void arm_pid_reset_q31(

-  arm_pid_instance_q31 * S);

-

-

-  /**

-   * @brief  Initialization function for the Q15 PID Control.

-   * @param[in,out] S               points to an instance of the Q15 PID structure.

-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.

-   */

-  void arm_pid_init_q15(

-  arm_pid_instance_q15 * S,

-  int32_t resetStateFlag);

-

-

-  /**

-   * @brief  Reset function for the Q15 PID Control.

-   * @param[in,out] S  points to an instance of the q15 PID Control structure

-   */

-  void arm_pid_reset_q15(

-  arm_pid_instance_q15 * S);

-

-

-  /**

-   * @brief Instance structure for the floating-point Linear Interpolate function.

-   */

-  typedef struct

-  {

-    uint32_t nValues;           /**< nValues */

-    float32_t x1;               /**< x1 */

-    float32_t xSpacing;         /**< xSpacing */

-    float32_t *pYData;          /**< pointer to the table of Y values */

-  } arm_linear_interp_instance_f32;

-

-  /**

-   * @brief Instance structure for the floating-point bilinear interpolation function.

-   */

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    float32_t *pData;   /**< points to the data table. */

-  } arm_bilinear_interp_instance_f32;

-

-   /**

-   * @brief Instance structure for the Q31 bilinear interpolation function.

-   */

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    q31_t *pData;       /**< points to the data table. */

-  } arm_bilinear_interp_instance_q31;

-

-   /**

-   * @brief Instance structure for the Q15 bilinear interpolation function.

-   */

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    q15_t *pData;       /**< points to the data table. */

-  } arm_bilinear_interp_instance_q15;

-

-   /**

-   * @brief Instance structure for the Q15 bilinear interpolation function.

-   */

-  typedef struct

-  {

-    uint16_t numRows;   /**< number of rows in the data table. */

-    uint16_t numCols;   /**< number of columns in the data table. */

-    q7_t *pData;        /**< points to the data table. */

-  } arm_bilinear_interp_instance_q7;

-

-

-  /**

-   * @brief Q7 vector multiplication.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_mult_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q15 vector multiplication.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_mult_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q31 vector multiplication.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_mult_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Floating-point vector multiplication.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_mult_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q15 CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix2_instance_q15;

-

-/* Deprecated */

-  arm_status arm_cfft_radix2_init_q15(

-  arm_cfft_radix2_instance_q15 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix2_q15(

-  const arm_cfft_radix2_instance_q15 * S,

-  q15_t * pSrc);

-

-

-  /**

-   * @brief Instance structure for the Q15 CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix4_instance_q15;

-

-/* Deprecated */

-  arm_status arm_cfft_radix4_init_q15(

-  arm_cfft_radix4_instance_q15 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix4_q15(

-  const arm_cfft_radix4_instance_q15 * S,

-  q15_t * pSrc);

-

-  /**

-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix2_instance_q31;

-

-/* Deprecated */

-  arm_status arm_cfft_radix2_init_q31(

-  arm_cfft_radix2_instance_q31 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix2_q31(

-  const arm_cfft_radix2_instance_q31 * S,

-  q31_t * pSrc);

-

-  /**

-   * @brief Instance structure for the Q31 CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                 /**< length of the FFT. */

-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */

-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-  } arm_cfft_radix4_instance_q31;

-

-/* Deprecated */

-  void arm_cfft_radix4_q31(

-  const arm_cfft_radix4_instance_q31 * S,

-  q31_t * pSrc);

-

-/* Deprecated */

-  arm_status arm_cfft_radix4_init_q31(

-  arm_cfft_radix4_instance_q31 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the floating-point CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */

-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-    float32_t onebyfftLen;             /**< value of 1/fftLen. */

-  } arm_cfft_radix2_instance_f32;

-

-/* Deprecated */

-  arm_status arm_cfft_radix2_init_f32(

-  arm_cfft_radix2_instance_f32 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix2_f32(

-  const arm_cfft_radix2_instance_f32 * S,

-  float32_t * pSrc);

-

-  /**

-   * @brief Instance structure for the floating-point CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */

-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */

-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */

-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */

-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */

-    float32_t onebyfftLen;             /**< value of 1/fftLen. */

-  } arm_cfft_radix4_instance_f32;

-

-/* Deprecated */

-  arm_status arm_cfft_radix4_init_f32(

-  arm_cfft_radix4_instance_f32 * S,

-  uint16_t fftLen,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-/* Deprecated */

-  void arm_cfft_radix4_f32(

-  const arm_cfft_radix4_instance_f32 * S,

-  float32_t * pSrc);

-

-  /**

-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */

-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

-    uint16_t bitRevLength;             /**< bit reversal table length. */

-  } arm_cfft_instance_q15;

-

-void arm_cfft_q15(

-    const arm_cfft_instance_q15 * S,

-    q15_t * p1,

-    uint8_t ifftFlag,

-    uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */

-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

-    uint16_t bitRevLength;             /**< bit reversal table length. */

-  } arm_cfft_instance_q31;

-

-void arm_cfft_q31(

-    const arm_cfft_instance_q31 * S,

-    q31_t * p1,

-    uint8_t ifftFlag,

-    uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the floating-point CFFT/CIFFT function.

-   */

-  typedef struct

-  {

-    uint16_t fftLen;                   /**< length of the FFT. */

-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */

-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */

-    uint16_t bitRevLength;             /**< bit reversal table length. */

-  } arm_cfft_instance_f32;

-

-  void arm_cfft_f32(

-  const arm_cfft_instance_f32 * S,

-  float32_t * p1,

-  uint8_t ifftFlag,

-  uint8_t bitReverseFlag);

-

-  /**

-   * @brief Instance structure for the Q15 RFFT/RIFFT function.

-   */

-  typedef struct

-  {

-    uint32_t fftLenReal;                      /**< length of the real FFT. */

-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */

-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */

-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */

-  } arm_rfft_instance_q15;

-

-  arm_status arm_rfft_init_q15(

-  arm_rfft_instance_q15 * S,

-  uint32_t fftLenReal,

-  uint32_t ifftFlagR,

-  uint32_t bitReverseFlag);

-

-  void arm_rfft_q15(

-  const arm_rfft_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst);

-

-  /**

-   * @brief Instance structure for the Q31 RFFT/RIFFT function.

-   */

-  typedef struct

-  {

-    uint32_t fftLenReal;                        /**< length of the real FFT. */

-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */

-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */

-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */

-  } arm_rfft_instance_q31;

-

-  arm_status arm_rfft_init_q31(

-  arm_rfft_instance_q31 * S,

-  uint32_t fftLenReal,

-  uint32_t ifftFlagR,

-  uint32_t bitReverseFlag);

-

-  void arm_rfft_q31(

-  const arm_rfft_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst);

-

-  /**

-   * @brief Instance structure for the floating-point RFFT/RIFFT function.

-   */

-  typedef struct

-  {

-    uint32_t fftLenReal;                        /**< length of the real FFT. */

-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */

-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */

-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */

-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */

-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */

-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */

-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */

-  } arm_rfft_instance_f32;

-

-  arm_status arm_rfft_init_f32(

-  arm_rfft_instance_f32 * S,

-  arm_cfft_radix4_instance_f32 * S_CFFT,

-  uint32_t fftLenReal,

-  uint32_t ifftFlagR,

-  uint32_t bitReverseFlag);

-

-  void arm_rfft_f32(

-  const arm_rfft_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst);

-

-  /**

-   * @brief Instance structure for the floating-point RFFT/RIFFT function.

-   */

-typedef struct

-  {

-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */

-    uint16_t fftLenRFFT;             /**< length of the real sequence */

-    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */

-  } arm_rfft_fast_instance_f32 ;

-

-arm_status arm_rfft_fast_init_f32 (

-   arm_rfft_fast_instance_f32 * S,

-   uint16_t fftLen);

-

-void arm_rfft_fast_f32(

-  arm_rfft_fast_instance_f32 * S,

-  float32_t * p, float32_t * pOut,

-  uint8_t ifftFlag);

-

-  /**

-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.

-   */

-  typedef struct

-  {

-    uint16_t N;                          /**< length of the DCT4. */

-    uint16_t Nby2;                       /**< half of the length of the DCT4. */

-    float32_t normalize;                 /**< normalizing factor. */

-    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */

-    float32_t *pCosFactor;               /**< points to the cosFactor table. */

-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */

-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */

-  } arm_dct4_instance_f32;

-

-

-  /**

-   * @brief  Initialization function for the floating-point DCT4/IDCT4.

-   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.

-   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.

-   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.

-   * @param[in]     N          length of the DCT4.

-   * @param[in]     Nby2       half of the length of the DCT4.

-   * @param[in]     normalize  normalizing factor.

-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.

-   */

-  arm_status arm_dct4_init_f32(

-  arm_dct4_instance_f32 * S,

-  arm_rfft_instance_f32 * S_RFFT,

-  arm_cfft_radix4_instance_f32 * S_CFFT,

-  uint16_t N,

-  uint16_t Nby2,

-  float32_t normalize);

-

-

-  /**

-   * @brief Processing function for the floating-point DCT4/IDCT4.

-   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.

-   * @param[in]     pState         points to state buffer.

-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.

-   */

-  void arm_dct4_f32(

-  const arm_dct4_instance_f32 * S,

-  float32_t * pState,

-  float32_t * pInlineBuffer);

-

-

-  /**

-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.

-   */

-  typedef struct

-  {

-    uint16_t N;                          /**< length of the DCT4. */

-    uint16_t Nby2;                       /**< half of the length of the DCT4. */

-    q31_t normalize;                     /**< normalizing factor. */

-    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */

-    q31_t *pCosFactor;                   /**< points to the cosFactor table. */

-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */

-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */

-  } arm_dct4_instance_q31;

-

-

-  /**

-   * @brief  Initialization function for the Q31 DCT4/IDCT4.

-   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.

-   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure

-   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure

-   * @param[in]     N          length of the DCT4.

-   * @param[in]     Nby2       half of the length of the DCT4.

-   * @param[in]     normalize  normalizing factor.

-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.

-   */

-  arm_status arm_dct4_init_q31(

-  arm_dct4_instance_q31 * S,

-  arm_rfft_instance_q31 * S_RFFT,

-  arm_cfft_radix4_instance_q31 * S_CFFT,

-  uint16_t N,

-  uint16_t Nby2,

-  q31_t normalize);

-

-

-  /**

-   * @brief Processing function for the Q31 DCT4/IDCT4.

-   * @param[in]     S              points to an instance of the Q31 DCT4 structure.

-   * @param[in]     pState         points to state buffer.

-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.

-   */

-  void arm_dct4_q31(

-  const arm_dct4_instance_q31 * S,

-  q31_t * pState,

-  q31_t * pInlineBuffer);

-

-

-  /**

-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.

-   */

-  typedef struct

-  {

-    uint16_t N;                          /**< length of the DCT4. */

-    uint16_t Nby2;                       /**< half of the length of the DCT4. */

-    q15_t normalize;                     /**< normalizing factor. */

-    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */

-    q15_t *pCosFactor;                   /**< points to the cosFactor table. */

-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */

-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */

-  } arm_dct4_instance_q15;

-

-

-  /**

-   * @brief  Initialization function for the Q15 DCT4/IDCT4.

-   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.

-   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.

-   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.

-   * @param[in]     N          length of the DCT4.

-   * @param[in]     Nby2       half of the length of the DCT4.

-   * @param[in]     normalize  normalizing factor.

-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.

-   */

-  arm_status arm_dct4_init_q15(

-  arm_dct4_instance_q15 * S,

-  arm_rfft_instance_q15 * S_RFFT,

-  arm_cfft_radix4_instance_q15 * S_CFFT,

-  uint16_t N,

-  uint16_t Nby2,

-  q15_t normalize);

-

-

-  /**

-   * @brief Processing function for the Q15 DCT4/IDCT4.

-   * @param[in]     S              points to an instance of the Q15 DCT4 structure.

-   * @param[in]     pState         points to state buffer.

-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.

-   */

-  void arm_dct4_q15(

-  const arm_dct4_instance_q15 * S,

-  q15_t * pState,

-  q15_t * pInlineBuffer);

-

-

-  /**

-   * @brief Floating-point vector addition.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_add_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q7 vector addition.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_add_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q15 vector addition.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_add_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q31 vector addition.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_add_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Floating-point vector subtraction.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_sub_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q7 vector subtraction.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_sub_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q15 vector subtraction.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_sub_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q31 vector subtraction.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_sub_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Multiplies a floating-point vector by a scalar.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  scale      scale factor to be applied

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_scale_f32(

-  float32_t * pSrc,

-  float32_t scale,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Multiplies a Q7 vector by a scalar.

-   * @param[in]  pSrc        points to the input vector

-   * @param[in]  scaleFract  fractional portion of the scale value

-   * @param[in]  shift       number of bits to shift the result by

-   * @param[out] pDst        points to the output vector

-   * @param[in]  blockSize   number of samples in the vector

-   */

-  void arm_scale_q7(

-  q7_t * pSrc,

-  q7_t scaleFract,

-  int8_t shift,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Multiplies a Q15 vector by a scalar.

-   * @param[in]  pSrc        points to the input vector

-   * @param[in]  scaleFract  fractional portion of the scale value

-   * @param[in]  shift       number of bits to shift the result by

-   * @param[out] pDst        points to the output vector

-   * @param[in]  blockSize   number of samples in the vector

-   */

-  void arm_scale_q15(

-  q15_t * pSrc,

-  q15_t scaleFract,

-  int8_t shift,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Multiplies a Q31 vector by a scalar.

-   * @param[in]  pSrc        points to the input vector

-   * @param[in]  scaleFract  fractional portion of the scale value

-   * @param[in]  shift       number of bits to shift the result by

-   * @param[out] pDst        points to the output vector

-   * @param[in]  blockSize   number of samples in the vector

-   */

-  void arm_scale_q31(

-  q31_t * pSrc,

-  q31_t scaleFract,

-  int8_t shift,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q7 vector absolute value.

-   * @param[in]  pSrc       points to the input buffer

-   * @param[out] pDst       points to the output buffer

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_abs_q7(

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Floating-point vector absolute value.

-   * @param[in]  pSrc       points to the input buffer

-   * @param[out] pDst       points to the output buffer

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_abs_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q15 vector absolute value.

-   * @param[in]  pSrc       points to the input buffer

-   * @param[out] pDst       points to the output buffer

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_abs_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Q31 vector absolute value.

-   * @param[in]  pSrc       points to the input buffer

-   * @param[out] pDst       points to the output buffer

-   * @param[in]  blockSize  number of samples in each vector

-   */

-  void arm_abs_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Dot product of floating-point vectors.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[in]  blockSize  number of samples in each vector

-   * @param[out] result     output result returned here

-   */

-  void arm_dot_prod_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  uint32_t blockSize,

-  float32_t * result);

-

-

-  /**

-   * @brief Dot product of Q7 vectors.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[in]  blockSize  number of samples in each vector

-   * @param[out] result     output result returned here

-   */

-  void arm_dot_prod_q7(

-  q7_t * pSrcA,

-  q7_t * pSrcB,

-  uint32_t blockSize,

-  q31_t * result);

-

-

-  /**

-   * @brief Dot product of Q15 vectors.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[in]  blockSize  number of samples in each vector

-   * @param[out] result     output result returned here

-   */

-  void arm_dot_prod_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  uint32_t blockSize,

-  q63_t * result);

-

-

-  /**

-   * @brief Dot product of Q31 vectors.

-   * @param[in]  pSrcA      points to the first input vector

-   * @param[in]  pSrcB      points to the second input vector

-   * @param[in]  blockSize  number of samples in each vector

-   * @param[out] result     output result returned here

-   */

-  void arm_dot_prod_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  uint32_t blockSize,

-  q63_t * result);

-

-

-  /**

-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_shift_q7(

-  q7_t * pSrc,

-  int8_t shiftBits,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_shift_q15(

-  q15_t * pSrc,

-  int8_t shiftBits,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_shift_q31(

-  q31_t * pSrc,

-  int8_t shiftBits,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Adds a constant offset to a floating-point vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  offset     is the offset to be added

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_offset_f32(

-  float32_t * pSrc,

-  float32_t offset,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Adds a constant offset to a Q7 vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  offset     is the offset to be added

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_offset_q7(

-  q7_t * pSrc,

-  q7_t offset,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Adds a constant offset to a Q15 vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  offset     is the offset to be added

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_offset_q15(

-  q15_t * pSrc,

-  q15_t offset,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Adds a constant offset to a Q31 vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[in]  offset     is the offset to be added

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_offset_q31(

-  q31_t * pSrc,

-  q31_t offset,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Negates the elements of a floating-point vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_negate_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Negates the elements of a Q7 vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_negate_q7(

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Negates the elements of a Q15 vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_negate_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Negates the elements of a Q31 vector.

-   * @param[in]  pSrc       points to the input vector

-   * @param[out] pDst       points to the output vector

-   * @param[in]  blockSize  number of samples in the vector

-   */

-  void arm_negate_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Copies the elements of a floating-point vector.

-   * @param[in]  pSrc       input pointer

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_copy_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Copies the elements of a Q7 vector.

-   * @param[in]  pSrc       input pointer

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_copy_q7(

-  q7_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Copies the elements of a Q15 vector.

-   * @param[in]  pSrc       input pointer

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_copy_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Copies the elements of a Q31 vector.

-   * @param[in]  pSrc       input pointer

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_copy_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Fills a constant value into a floating-point vector.

-   * @param[in]  value      input value to be filled

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_fill_f32(

-  float32_t value,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Fills a constant value into a Q7 vector.

-   * @param[in]  value      input value to be filled

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_fill_q7(

-  q7_t value,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Fills a constant value into a Q15 vector.

-   * @param[in]  value      input value to be filled

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_fill_q15(

-  q15_t value,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Fills a constant value into a Q31 vector.

-   * @param[in]  value      input value to be filled

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_fill_q31(

-  q31_t value,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-/**

- * @brief Convolution of floating-point sequences.

- * @param[in]  pSrcA    points to the first input sequence.

- * @param[in]  srcALen  length of the first input sequence.

- * @param[in]  pSrcB    points to the second input sequence.

- * @param[in]  srcBLen  length of the second input sequence.

- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.

- */

-  void arm_conv_f32(

-  float32_t * pSrcA,

-  uint32_t srcALen,

-  float32_t * pSrcB,

-  uint32_t srcBLen,

-  float32_t * pDst);

-

-

-  /**

-   * @brief Convolution of Q15 sequences.

-   * @param[in]  pSrcA      points to the first input sequence.

-   * @param[in]  srcALen    length of the first input sequence.

-   * @param[in]  pSrcB      points to the second input sequence.

-   * @param[in]  srcBLen    length of the second input sequence.

-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.

-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).

-   */

-  void arm_conv_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-/**

- * @brief Convolution of Q15 sequences.

- * @param[in]  pSrcA    points to the first input sequence.

- * @param[in]  srcALen  length of the first input sequence.

- * @param[in]  pSrcB    points to the second input sequence.

- * @param[in]  srcBLen  length of the second input sequence.

- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.

- */

-  void arm_conv_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst);

-

-

-  /**

-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.

-   */

-  void arm_conv_fast_q15(

-          q15_t * pSrcA,

-          uint32_t srcALen,

-          q15_t * pSrcB,

-          uint32_t srcBLen,

-          q15_t * pDst);

-

-

-  /**

-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA      points to the first input sequence.

-   * @param[in]  srcALen    length of the first input sequence.

-   * @param[in]  pSrcB      points to the second input sequence.

-   * @param[in]  srcBLen    length of the second input sequence.

-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.

-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).

-   */

-  void arm_conv_fast_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-  /**

-   * @brief Convolution of Q31 sequences.

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.

-   */

-  void arm_conv_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-

-  /**

-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.

-   */

-  void arm_conv_fast_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-

-    /**

-   * @brief Convolution of Q7 sequences.

-   * @param[in]  pSrcA      points to the first input sequence.

-   * @param[in]  srcALen    length of the first input sequence.

-   * @param[in]  pSrcB      points to the second input sequence.

-   * @param[in]  srcBLen    length of the second input sequence.

-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.

-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).

-   */

-  void arm_conv_opt_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-  /**

-   * @brief Convolution of Q7 sequences.

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.

-   */

-  void arm_conv_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst);

-

-

-  /**

-   * @brief Partial convolution of floating-point sequences.

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_f32(

-  float32_t * pSrcA,

-  uint32_t srcALen,

-  float32_t * pSrcB,

-  uint32_t srcBLen,

-  float32_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q15 sequences.

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-  /**

-   * @brief Partial convolution of Q15 sequences.

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_fast_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_fast_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-  /**

-   * @brief Partial convolution of Q31 sequences.

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_fast_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Partial convolution of Q7 sequences

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_opt_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-/**

-   * @brief Partial convolution of Q7 sequences.

-   * @param[in]  pSrcA       points to the first input sequence.

-   * @param[in]  srcALen     length of the first input sequence.

-   * @param[in]  pSrcB       points to the second input sequence.

-   * @param[in]  srcBLen     length of the second input sequence.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  firstIndex  is the first output sample to start with.

-   * @param[in]  numPoints   is the number of output points to be computed.

-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

-   */

-  arm_status arm_conv_partial_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  uint32_t firstIndex,

-  uint32_t numPoints);

-

-

-  /**

-   * @brief Instance structure for the Q15 FIR decimator.

-   */

-  typedef struct

-  {

-    uint8_t M;                  /**< decimation factor. */

-    uint16_t numTaps;           /**< number of coefficients in the filter. */

-    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/

-    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-  } arm_fir_decimate_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR decimator.

-   */

-  typedef struct

-  {

-    uint8_t M;                  /**< decimation factor. */

-    uint16_t numTaps;           /**< number of coefficients in the filter. */

-    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/

-    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-  } arm_fir_decimate_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR decimator.

-   */

-  typedef struct

-  {

-    uint8_t M;                  /**< decimation factor. */

-    uint16_t numTaps;           /**< number of coefficients in the filter. */

-    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/

-    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-  } arm_fir_decimate_instance_f32;

-

-

-  /**

-   * @brief Processing function for the floating-point FIR decimator.

-   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of input samples to process per call.

-   */

-  void arm_fir_decimate_f32(

-  const arm_fir_decimate_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point FIR decimator.

-   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.

-   * @param[in]     numTaps    number of coefficients in the filter.

-   * @param[in]     M          decimation factor.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of input samples to process per call.

-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * <code>blockSize</code> is not a multiple of <code>M</code>.

-   */

-  arm_status arm_fir_decimate_init_f32(

-  arm_fir_decimate_instance_f32 * S,

-  uint16_t numTaps,

-  uint8_t M,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q15 FIR decimator.

-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of input samples to process per call.

-   */

-  void arm_fir_decimate_q15(

-  const arm_fir_decimate_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.

-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of input samples to process per call.

-   */

-  void arm_fir_decimate_fast_q15(

-  const arm_fir_decimate_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q15 FIR decimator.

-   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.

-   * @param[in]     numTaps    number of coefficients in the filter.

-   * @param[in]     M          decimation factor.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of input samples to process per call.

-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * <code>blockSize</code> is not a multiple of <code>M</code>.

-   */

-  arm_status arm_fir_decimate_init_q15(

-  arm_fir_decimate_instance_q15 * S,

-  uint16_t numTaps,

-  uint8_t M,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 FIR decimator.

-   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.

-   * @param[in]  pSrc  points to the block of input data.

-   * @param[out] pDst  points to the block of output data

-   * @param[in] blockSize number of input samples to process per call.

-   */

-  void arm_fir_decimate_q31(

-  const arm_fir_decimate_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.

-   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of input samples to process per call.

-   */

-  void arm_fir_decimate_fast_q31(

-  arm_fir_decimate_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q31 FIR decimator.

-   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.

-   * @param[in]     numTaps    number of coefficients in the filter.

-   * @param[in]     M          decimation factor.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of input samples to process per call.

-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * <code>blockSize</code> is not a multiple of <code>M</code>.

-   */

-  arm_status arm_fir_decimate_init_q31(

-  arm_fir_decimate_instance_q31 * S,

-  uint16_t numTaps,

-  uint8_t M,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q15 FIR interpolator.

-   */

-  typedef struct

-  {

-    uint8_t L;                      /**< upsample factor. */

-    uint16_t phaseLength;           /**< length of each polyphase filter component. */

-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */

-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */

-  } arm_fir_interpolate_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR interpolator.

-   */

-  typedef struct

-  {

-    uint8_t L;                      /**< upsample factor. */

-    uint16_t phaseLength;           /**< length of each polyphase filter component. */

-    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */

-    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */

-  } arm_fir_interpolate_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR interpolator.

-   */

-  typedef struct

-  {

-    uint8_t L;                     /**< upsample factor. */

-    uint16_t phaseLength;          /**< length of each polyphase filter component. */

-    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */

-    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */

-  } arm_fir_interpolate_instance_f32;

-

-

-  /**

-   * @brief Processing function for the Q15 FIR interpolator.

-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of input samples to process per call.

-   */

-  void arm_fir_interpolate_q15(

-  const arm_fir_interpolate_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q15 FIR interpolator.

-   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.

-   * @param[in]     L          upsample factor.

-   * @param[in]     numTaps    number of filter coefficients in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficient buffer.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of input samples to process per call.

-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.

-   */

-  arm_status arm_fir_interpolate_init_q15(

-  arm_fir_interpolate_instance_q15 * S,

-  uint8_t L,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 FIR interpolator.

-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of input samples to process per call.

-   */

-  void arm_fir_interpolate_q31(

-  const arm_fir_interpolate_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q31 FIR interpolator.

-   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.

-   * @param[in]     L          upsample factor.

-   * @param[in]     numTaps    number of filter coefficients in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficient buffer.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of input samples to process per call.

-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.

-   */

-  arm_status arm_fir_interpolate_init_q31(

-  arm_fir_interpolate_instance_q31 * S,

-  uint8_t L,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the floating-point FIR interpolator.

-   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of input samples to process per call.

-   */

-  void arm_fir_interpolate_f32(

-  const arm_fir_interpolate_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point FIR interpolator.

-   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.

-   * @param[in]     L          upsample factor.

-   * @param[in]     numTaps    number of filter coefficients in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficient buffer.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     blockSize  number of input samples to process per call.

-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if

-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.

-   */

-  arm_status arm_fir_interpolate_init_f32(

-  arm_fir_interpolate_instance_f32 * S,

-  uint8_t L,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */

-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */

-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */

-  } arm_biquad_cas_df1_32x64_ins_q31;

-

-

-  /**

-   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cas_df1_32x64_q31(

-  const arm_biquad_cas_df1_32x64_ins_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.

-   * @param[in]     numStages  number of 2nd order stages in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format

-   */

-  void arm_biquad_cas_df1_32x64_init_q31(

-  arm_biquad_cas_df1_32x64_ins_q31 * S,

-  uint8_t numStages,

-  q31_t * pCoeffs,

-  q63_t * pState,

-  uint8_t postShift);

-

-

-  /**

-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */

-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

-  } arm_biquad_cascade_df2T_instance_f32;

-

-  /**

-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */

-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

-  } arm_biquad_cascade_stereo_df2T_instance_f32;

-

-  /**

-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.

-   */

-  typedef struct

-  {

-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */

-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */

-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */

-  } arm_biquad_cascade_df2T_instance_f64;

-

-

-  /**

-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in]  S          points to an instance of the filter data structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_df2T_f32(

-  const arm_biquad_cascade_df2T_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels

-   * @param[in]  S          points to an instance of the filter data structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_stereo_df2T_f32(

-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in]  S          points to an instance of the filter data structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_biquad_cascade_df2T_f64(

-  const arm_biquad_cascade_df2T_instance_f64 * S,

-  float64_t * pSrc,

-  float64_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in,out] S          points to an instance of the filter data structure.

-   * @param[in]     numStages  number of 2nd order stages in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   */

-  void arm_biquad_cascade_df2T_init_f32(

-  arm_biquad_cascade_df2T_instance_f32 * S,

-  uint8_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-

-  /**

-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in,out] S          points to an instance of the filter data structure.

-   * @param[in]     numStages  number of 2nd order stages in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   */

-  void arm_biquad_cascade_stereo_df2T_init_f32(

-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,

-  uint8_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-

-  /**

-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.

-   * @param[in,out] S          points to an instance of the filter data structure.

-   * @param[in]     numStages  number of 2nd order stages in the filter.

-   * @param[in]     pCoeffs    points to the filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   */

-  void arm_biquad_cascade_df2T_init_f64(

-  arm_biquad_cascade_df2T_instance_f64 * S,

-  uint8_t numStages,

-  float64_t * pCoeffs,

-  float64_t * pState);

-

-

-  /**

-   * @brief Instance structure for the Q15 FIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                  /**< number of filter stages. */

-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */

-    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */

-  } arm_fir_lattice_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 FIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                  /**< number of filter stages. */

-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */

-    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */

-  } arm_fir_lattice_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point FIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                  /**< number of filter stages. */

-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */

-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */

-  } arm_fir_lattice_instance_f32;

-

-

-  /**

-   * @brief Initialization function for the Q15 FIR lattice filter.

-   * @param[in] S          points to an instance of the Q15 FIR lattice structure.

-   * @param[in] numStages  number of filter stages.

-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.

-   * @param[in] pState     points to the state buffer.  The array is of length numStages.

-   */

-  void arm_fir_lattice_init_q15(

-  arm_fir_lattice_instance_q15 * S,

-  uint16_t numStages,

-  q15_t * pCoeffs,

-  q15_t * pState);

-

-

-  /**

-   * @brief Processing function for the Q15 FIR lattice filter.

-   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_lattice_q15(

-  const arm_fir_lattice_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for the Q31 FIR lattice filter.

-   * @param[in] S          points to an instance of the Q31 FIR lattice structure.

-   * @param[in] numStages  number of filter stages.

-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.

-   * @param[in] pState     points to the state buffer.   The array is of length numStages.

-   */

-  void arm_fir_lattice_init_q31(

-  arm_fir_lattice_instance_q31 * S,

-  uint16_t numStages,

-  q31_t * pCoeffs,

-  q31_t * pState);

-

-

-  /**

-   * @brief Processing function for the Q31 FIR lattice filter.

-   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_lattice_q31(

-  const arm_fir_lattice_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-/**

- * @brief Initialization function for the floating-point FIR lattice filter.

- * @param[in] S          points to an instance of the floating-point FIR lattice structure.

- * @param[in] numStages  number of filter stages.

- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.

- * @param[in] pState     points to the state buffer.  The array is of length numStages.

- */

-  void arm_fir_lattice_init_f32(

-  arm_fir_lattice_instance_f32 * S,

-  uint16_t numStages,

-  float32_t * pCoeffs,

-  float32_t * pState);

-

-

-  /**

-   * @brief Processing function for the floating-point FIR lattice filter.

-   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_fir_lattice_f32(

-  const arm_fir_lattice_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q15 IIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                  /**< number of stages in the filter. */

-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */

-    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */

-    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */

-  } arm_iir_lattice_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q31 IIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                  /**< number of stages in the filter. */

-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */

-    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */

-    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */

-  } arm_iir_lattice_instance_q31;

-

-  /**

-   * @brief Instance structure for the floating-point IIR lattice filter.

-   */

-  typedef struct

-  {

-    uint16_t numStages;                  /**< number of stages in the filter. */

-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */

-    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */

-    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */

-  } arm_iir_lattice_instance_f32;

-

-

-  /**

-   * @brief Processing function for the floating-point IIR lattice filter.

-   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_iir_lattice_f32(

-  const arm_iir_lattice_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for the floating-point IIR lattice filter.

-   * @param[in] S          points to an instance of the floating-point IIR lattice structure.

-   * @param[in] numStages  number of stages in the filter.

-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.

-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.

-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.

-   * @param[in] blockSize  number of samples to process.

-   */

-  void arm_iir_lattice_init_f32(

-  arm_iir_lattice_instance_f32 * S,

-  uint16_t numStages,

-  float32_t * pkCoeffs,

-  float32_t * pvCoeffs,

-  float32_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 IIR lattice filter.

-   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_iir_lattice_q31(

-  const arm_iir_lattice_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for the Q31 IIR lattice filter.

-   * @param[in] S          points to an instance of the Q31 IIR lattice structure.

-   * @param[in] numStages  number of stages in the filter.

-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.

-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.

-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.

-   * @param[in] blockSize  number of samples to process.

-   */

-  void arm_iir_lattice_init_q31(

-  arm_iir_lattice_instance_q31 * S,

-  uint16_t numStages,

-  q31_t * pkCoeffs,

-  q31_t * pvCoeffs,

-  q31_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q15 IIR lattice filter.

-   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[out] pDst       points to the block of output data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_iir_lattice_q15(

-  const arm_iir_lattice_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-/**

- * @brief Initialization function for the Q15 IIR lattice filter.

- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.

- * @param[in] numStages  number of stages in the filter.

- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.

- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.

- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.

- * @param[in] blockSize  number of samples to process per call.

- */

-  void arm_iir_lattice_init_q15(

-  arm_iir_lattice_instance_q15 * S,

-  uint16_t numStages,

-  q15_t * pkCoeffs,

-  q15_t * pvCoeffs,

-  q15_t * pState,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the floating-point LMS filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;    /**< number of coefficients in the filter. */

-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */

-    float32_t mu;        /**< step size that controls filter coefficient updates. */

-  } arm_lms_instance_f32;

-

-

-  /**

-   * @brief Processing function for floating-point LMS filter.

-   * @param[in]  S          points to an instance of the floating-point LMS filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[in]  pRef       points to the block of reference data.

-   * @param[out] pOut       points to the block of output data.

-   * @param[out] pErr       points to the block of error data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_lms_f32(

-  const arm_lms_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pRef,

-  float32_t * pOut,

-  float32_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for floating-point LMS filter.

-   * @param[in] S          points to an instance of the floating-point LMS filter structure.

-   * @param[in] numTaps    number of filter coefficients.

-   * @param[in] pCoeffs    points to the coefficient buffer.

-   * @param[in] pState     points to state buffer.

-   * @param[in] mu         step size that controls filter coefficient updates.

-   * @param[in] blockSize  number of samples to process.

-   */

-  void arm_lms_init_f32(

-  arm_lms_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  float32_t mu,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q15 LMS filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;    /**< number of coefficients in the filter. */

-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */

-    q15_t mu;            /**< step size that controls filter coefficient updates. */

-    uint32_t postShift;  /**< bit shift applied to coefficients. */

-  } arm_lms_instance_q15;

-

-

-  /**

-   * @brief Initialization function for the Q15 LMS filter.

-   * @param[in] S          points to an instance of the Q15 LMS filter structure.

-   * @param[in] numTaps    number of filter coefficients.

-   * @param[in] pCoeffs    points to the coefficient buffer.

-   * @param[in] pState     points to the state buffer.

-   * @param[in] mu         step size that controls filter coefficient updates.

-   * @param[in] blockSize  number of samples to process.

-   * @param[in] postShift  bit shift applied to coefficients.

-   */

-  void arm_lms_init_q15(

-  arm_lms_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  q15_t mu,

-  uint32_t blockSize,

-  uint32_t postShift);

-

-

-  /**

-   * @brief Processing function for Q15 LMS filter.

-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[in]  pRef       points to the block of reference data.

-   * @param[out] pOut       points to the block of output data.

-   * @param[out] pErr       points to the block of error data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_lms_q15(

-  const arm_lms_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pRef,

-  q15_t * pOut,

-  q15_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q31 LMS filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;    /**< number of coefficients in the filter. */

-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */

-    q31_t mu;            /**< step size that controls filter coefficient updates. */

-    uint32_t postShift;  /**< bit shift applied to coefficients. */

-  } arm_lms_instance_q31;

-

-

-  /**

-   * @brief Processing function for Q31 LMS filter.

-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[in]  pRef       points to the block of reference data.

-   * @param[out] pOut       points to the block of output data.

-   * @param[out] pErr       points to the block of error data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_lms_q31(

-  const arm_lms_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pRef,

-  q31_t * pOut,

-  q31_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for Q31 LMS filter.

-   * @param[in] S          points to an instance of the Q31 LMS filter structure.

-   * @param[in] numTaps    number of filter coefficients.

-   * @param[in] pCoeffs    points to coefficient buffer.

-   * @param[in] pState     points to state buffer.

-   * @param[in] mu         step size that controls filter coefficient updates.

-   * @param[in] blockSize  number of samples to process.

-   * @param[in] postShift  bit shift applied to coefficients.

-   */

-  void arm_lms_init_q31(

-  arm_lms_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  q31_t mu,

-  uint32_t blockSize,

-  uint32_t postShift);

-

-

-  /**

-   * @brief Instance structure for the floating-point normalized LMS filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;     /**< number of coefficients in the filter. */

-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */

-    float32_t mu;         /**< step size that control filter coefficient updates. */

-    float32_t energy;     /**< saves previous frame energy. */

-    float32_t x0;         /**< saves previous input sample. */

-  } arm_lms_norm_instance_f32;

-

-

-  /**

-   * @brief Processing function for floating-point normalized LMS filter.

-   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[in]  pRef       points to the block of reference data.

-   * @param[out] pOut       points to the block of output data.

-   * @param[out] pErr       points to the block of error data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_lms_norm_f32(

-  arm_lms_norm_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pRef,

-  float32_t * pOut,

-  float32_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for floating-point normalized LMS filter.

-   * @param[in] S          points to an instance of the floating-point LMS filter structure.

-   * @param[in] numTaps    number of filter coefficients.

-   * @param[in] pCoeffs    points to coefficient buffer.

-   * @param[in] pState     points to state buffer.

-   * @param[in] mu         step size that controls filter coefficient updates.

-   * @param[in] blockSize  number of samples to process.

-   */

-  void arm_lms_norm_init_f32(

-  arm_lms_norm_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  float32_t mu,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Instance structure for the Q31 normalized LMS filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;     /**< number of coefficients in the filter. */

-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */

-    q31_t mu;             /**< step size that controls filter coefficient updates. */

-    uint8_t postShift;    /**< bit shift applied to coefficients. */

-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */

-    q31_t energy;         /**< saves previous frame energy. */

-    q31_t x0;             /**< saves previous input sample. */

-  } arm_lms_norm_instance_q31;

-

-

-  /**

-   * @brief Processing function for Q31 normalized LMS filter.

-   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[in]  pRef       points to the block of reference data.

-   * @param[out] pOut       points to the block of output data.

-   * @param[out] pErr       points to the block of error data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_lms_norm_q31(

-  arm_lms_norm_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pRef,

-  q31_t * pOut,

-  q31_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for Q31 normalized LMS filter.

-   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.

-   * @param[in] numTaps    number of filter coefficients.

-   * @param[in] pCoeffs    points to coefficient buffer.

-   * @param[in] pState     points to state buffer.

-   * @param[in] mu         step size that controls filter coefficient updates.

-   * @param[in] blockSize  number of samples to process.

-   * @param[in] postShift  bit shift applied to coefficients.

-   */

-  void arm_lms_norm_init_q31(

-  arm_lms_norm_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  q31_t mu,

-  uint32_t blockSize,

-  uint8_t postShift);

-

-

-  /**

-   * @brief Instance structure for the Q15 normalized LMS filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;     /**< Number of coefficients in the filter. */

-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */

-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */

-    q15_t mu;             /**< step size that controls filter coefficient updates. */

-    uint8_t postShift;    /**< bit shift applied to coefficients. */

-    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */

-    q15_t energy;         /**< saves previous frame energy. */

-    q15_t x0;             /**< saves previous input sample. */

-  } arm_lms_norm_instance_q15;

-

-

-  /**

-   * @brief Processing function for Q15 normalized LMS filter.

-   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.

-   * @param[in]  pSrc       points to the block of input data.

-   * @param[in]  pRef       points to the block of reference data.

-   * @param[out] pOut       points to the block of output data.

-   * @param[out] pErr       points to the block of error data.

-   * @param[in]  blockSize  number of samples to process.

-   */

-  void arm_lms_norm_q15(

-  arm_lms_norm_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pRef,

-  q15_t * pOut,

-  q15_t * pErr,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Initialization function for Q15 normalized LMS filter.

-   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.

-   * @param[in] numTaps    number of filter coefficients.

-   * @param[in] pCoeffs    points to coefficient buffer.

-   * @param[in] pState     points to state buffer.

-   * @param[in] mu         step size that controls filter coefficient updates.

-   * @param[in] blockSize  number of samples to process.

-   * @param[in] postShift  bit shift applied to coefficients.

-   */

-  void arm_lms_norm_init_q15(

-  arm_lms_norm_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  q15_t mu,

-  uint32_t blockSize,

-  uint8_t postShift);

-

-

-  /**

-   * @brief Correlation of floating-point sequences.

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   */

-  void arm_correlate_f32(

-  float32_t * pSrcA,

-  uint32_t srcALen,

-  float32_t * pSrcB,

-  uint32_t srcBLen,

-  float32_t * pDst);

-

-

-   /**

-   * @brief Correlation of Q15 sequences

-   * @param[in]  pSrcA     points to the first input sequence.

-   * @param[in]  srcALen   length of the first input sequence.

-   * @param[in]  pSrcB     points to the second input sequence.

-   * @param[in]  srcBLen   length of the second input sequence.

-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   */

-  void arm_correlate_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch);

-

-

-  /**

-   * @brief Correlation of Q15 sequences.

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   */

-

-  void arm_correlate_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst);

-

-

-  /**

-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   */

-

-  void arm_correlate_fast_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst);

-

-

-  /**

-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.

-   * @param[in]  pSrcA     points to the first input sequence.

-   * @param[in]  srcALen   length of the first input sequence.

-   * @param[in]  pSrcB     points to the second input sequence.

-   * @param[in]  srcBLen   length of the second input sequence.

-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   */

-  void arm_correlate_fast_opt_q15(

-  q15_t * pSrcA,

-  uint32_t srcALen,

-  q15_t * pSrcB,

-  uint32_t srcBLen,

-  q15_t * pDst,

-  q15_t * pScratch);

-

-

-  /**

-   * @brief Correlation of Q31 sequences.

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   */

-  void arm_correlate_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-

-  /**

-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   */

-  void arm_correlate_fast_q31(

-  q31_t * pSrcA,

-  uint32_t srcALen,

-  q31_t * pSrcB,

-  uint32_t srcBLen,

-  q31_t * pDst);

-

-

- /**

-   * @brief Correlation of Q7 sequences.

-   * @param[in]  pSrcA      points to the first input sequence.

-   * @param[in]  srcALen    length of the first input sequence.

-   * @param[in]  pSrcB      points to the second input sequence.

-   * @param[in]  srcBLen    length of the second input sequence.

-   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.

-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).

-   */

-  void arm_correlate_opt_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst,

-  q15_t * pScratch1,

-  q15_t * pScratch2);

-

-

-  /**

-   * @brief Correlation of Q7 sequences.

-   * @param[in]  pSrcA    points to the first input sequence.

-   * @param[in]  srcALen  length of the first input sequence.

-   * @param[in]  pSrcB    points to the second input sequence.

-   * @param[in]  srcBLen  length of the second input sequence.

-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.

-   */

-  void arm_correlate_q7(

-  q7_t * pSrcA,

-  uint32_t srcALen,

-  q7_t * pSrcB,

-  uint32_t srcBLen,

-  q7_t * pDst);

-

-

-  /**

-   * @brief Instance structure for the floating-point sparse FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_f32;

-

-  /**

-   * @brief Instance structure for the Q31 sparse FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_q31;

-

-  /**

-   * @brief Instance structure for the Q15 sparse FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_q15;

-

-  /**

-   * @brief Instance structure for the Q7 sparse FIR filter.

-   */

-  typedef struct

-  {

-    uint16_t numTaps;             /**< number of coefficients in the filter. */

-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */

-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */

-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/

-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */

-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */

-  } arm_fir_sparse_instance_q7;

-

-

-  /**

-   * @brief Processing function for the floating-point sparse FIR filter.

-   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.

-   * @param[in]  pSrc        points to the block of input data.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize   number of input samples to process per call.

-   */

-  void arm_fir_sparse_f32(

-  arm_fir_sparse_instance_f32 * S,

-  float32_t * pSrc,

-  float32_t * pDst,

-  float32_t * pScratchIn,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the floating-point sparse FIR filter.

-   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     pCoeffs    points to the array of filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     pTapDelay  points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   */

-  void arm_fir_sparse_init_f32(

-  arm_fir_sparse_instance_f32 * S,

-  uint16_t numTaps,

-  float32_t * pCoeffs,

-  float32_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q31 sparse FIR filter.

-   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.

-   * @param[in]  pSrc        points to the block of input data.

-   * @param[out] pDst        points to the block of output data

-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize   number of input samples to process per call.

-   */

-  void arm_fir_sparse_q31(

-  arm_fir_sparse_instance_q31 * S,

-  q31_t * pSrc,

-  q31_t * pDst,

-  q31_t * pScratchIn,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q31 sparse FIR filter.

-   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     pCoeffs    points to the array of filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     pTapDelay  points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   */

-  void arm_fir_sparse_init_q31(

-  arm_fir_sparse_instance_q31 * S,

-  uint16_t numTaps,

-  q31_t * pCoeffs,

-  q31_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q15 sparse FIR filter.

-   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.

-   * @param[in]  pSrc         points to the block of input data.

-   * @param[out] pDst         points to the block of output data

-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.

-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize    number of input samples to process per call.

-   */

-  void arm_fir_sparse_q15(

-  arm_fir_sparse_instance_q15 * S,

-  q15_t * pSrc,

-  q15_t * pDst,

-  q15_t * pScratchIn,

-  q31_t * pScratchOut,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q15 sparse FIR filter.

-   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     pCoeffs    points to the array of filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     pTapDelay  points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   */

-  void arm_fir_sparse_init_q15(

-  arm_fir_sparse_instance_q15 * S,

-  uint16_t numTaps,

-  q15_t * pCoeffs,

-  q15_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Processing function for the Q7 sparse FIR filter.

-   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.

-   * @param[in]  pSrc         points to the block of input data.

-   * @param[out] pDst         points to the block of output data

-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.

-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.

-   * @param[in]  blockSize    number of input samples to process per call.

-   */

-  void arm_fir_sparse_q7(

-  arm_fir_sparse_instance_q7 * S,

-  q7_t * pSrc,

-  q7_t * pDst,

-  q7_t * pScratchIn,

-  q31_t * pScratchOut,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Initialization function for the Q7 sparse FIR filter.

-   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.

-   * @param[in]     numTaps    number of nonzero coefficients in the filter.

-   * @param[in]     pCoeffs    points to the array of filter coefficients.

-   * @param[in]     pState     points to the state buffer.

-   * @param[in]     pTapDelay  points to the array of offset times.

-   * @param[in]     maxDelay   maximum offset time supported.

-   * @param[in]     blockSize  number of samples that will be processed per block.

-   */

-  void arm_fir_sparse_init_q7(

-  arm_fir_sparse_instance_q7 * S,

-  uint16_t numTaps,

-  q7_t * pCoeffs,

-  q7_t * pState,

-  int32_t * pTapDelay,

-  uint16_t maxDelay,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Floating-point sin_cos function.

-   * @param[in]  theta   input value in degrees

-   * @param[out] pSinVal  points to the processed sine output.

-   * @param[out] pCosVal  points to the processed cos output.

-   */

-  void arm_sin_cos_f32(

-  float32_t theta,

-  float32_t * pSinVal,

-  float32_t * pCosVal);

-

-

-  /**

-   * @brief  Q31 sin_cos function.

-   * @param[in]  theta    scaled input value in degrees

-   * @param[out] pSinVal  points to the processed sine output.

-   * @param[out] pCosVal  points to the processed cosine output.

-   */

-  void arm_sin_cos_q31(

-  q31_t theta,

-  q31_t * pSinVal,

-  q31_t * pCosVal);

-

-

-  /**

-   * @brief  Floating-point complex conjugate.

-   * @param[in]  pSrc        points to the input vector

-   * @param[out] pDst        points to the output vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   */

-  void arm_cmplx_conj_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-  /**

-   * @brief  Q31 complex conjugate.

-   * @param[in]  pSrc        points to the input vector

-   * @param[out] pDst        points to the output vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   */

-  void arm_cmplx_conj_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q15 complex conjugate.

-   * @param[in]  pSrc        points to the input vector

-   * @param[out] pDst        points to the output vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   */

-  void arm_cmplx_conj_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Floating-point complex magnitude squared

-   * @param[in]  pSrc        points to the complex input vector

-   * @param[out] pDst        points to the real output vector

-   * @param[in]  numSamples  number of complex samples in the input vector

-   */

-  void arm_cmplx_mag_squared_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q31 complex magnitude squared

-   * @param[in]  pSrc        points to the complex input vector

-   * @param[out] pDst        points to the real output vector

-   * @param[in]  numSamples  number of complex samples in the input vector

-   */

-  void arm_cmplx_mag_squared_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q15 complex magnitude squared

-   * @param[in]  pSrc        points to the complex input vector

-   * @param[out] pDst        points to the real output vector

-   * @param[in]  numSamples  number of complex samples in the input vector

-   */

-  void arm_cmplx_mag_squared_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-

- /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup PID PID Motor Control

-   *

-   * A Proportional Integral Derivative (PID) controller is a generic feedback control

-   * loop mechanism widely used in industrial control systems.

-   * A PID controller is the most commonly used type of feedback controller.

-   *

-   * This set of functions implements (PID) controllers

-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample

-   * of data and each call to the function returns a single processed value.

-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>

-   * is the input sample value. The functions return the output value.

-   *

-   * \par Algorithm:

-   * <pre>

-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]

-   *    A0 = Kp + Ki + Kd

-   *    A1 = (-Kp ) - (2 * Kd )

-   *    A2 = Kd  </pre>

-   *

-   * \par

-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant

-   *

-   * \par

-   * \image html PID.gif "Proportional Integral Derivative Controller"

-   *

-   * \par

-   * The PID controller calculates an "error" value as the difference between

-   * the measured output and the reference input.

-   * The controller attempts to minimize the error by adjusting the process control inputs.

-   * The proportional value determines the reaction to the current error,

-   * the integral value determines the reaction based on the sum of recent errors,

-   * and the derivative value determines the reaction based on the rate at which the error has been changing.

-   *

-   * \par Instance Structure

-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.

-   * A separate instance structure must be defined for each PID Controller.

-   * There are separate instance structure declarations for each of the 3 supported data types.

-   *

-   * \par Reset Functions

-   * There is also an associated reset function for each data type which clears the state array.

-   *

-   * \par Initialization Functions

-   * There is also an associated initialization function for each data type.

-   * The initialization function performs the following operations:

-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.

-   * - Zeros out the values in the state buffer.

-   *

-   * \par

-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.

-   *

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the fixed-point versions of the PID Controller functions.

-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup PID

-   * @{

-   */

-

-  /**

-   * @brief  Process function for the floating-point PID Control.

-   * @param[in,out] S   is an instance of the floating-point PID Control structure

-   * @param[in]     in  input sample to process

-   * @return out processed output sample.

-   */

-  static __INLINE float32_t arm_pid_f32(

-  arm_pid_instance_f32 * S,

-  float32_t in)

-  {

-    float32_t out;

-

-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */

-    out = (S->A0 * in) +

-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);

-

-    /* Update state */

-    S->state[1] = S->state[0];

-    S->state[0] = in;

-    S->state[2] = out;

-

-    /* return to application */

-    return (out);

-

-  }

-

-  /**

-   * @brief  Process function for the Q31 PID Control.

-   * @param[in,out] S  points to an instance of the Q31 PID Control structure

-   * @param[in]     in  input sample to process

-   * @return out processed output sample.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 64-bit accumulator.

-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.

-   * Thus, if the accumulator result overflows it wraps around rather than clip.

-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.

-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.

-   */

-  static __INLINE q31_t arm_pid_q31(

-  arm_pid_instance_q31 * S,

-  q31_t in)

-  {

-    q63_t acc;

-    q31_t out;

-

-    /* acc = A0 * x[n]  */

-    acc = (q63_t) S->A0 * in;

-

-    /* acc += A1 * x[n-1] */

-    acc += (q63_t) S->A1 * S->state[0];

-

-    /* acc += A2 * x[n-2]  */

-    acc += (q63_t) S->A2 * S->state[1];

-

-    /* convert output to 1.31 format to add y[n-1] */

-    out = (q31_t) (acc >> 31u);

-

-    /* out += y[n-1] */

-    out += S->state[2];

-

-    /* Update state */

-    S->state[1] = S->state[0];

-    S->state[0] = in;

-    S->state[2] = out;

-

-    /* return to application */

-    return (out);

-  }

-

-

-  /**

-   * @brief  Process function for the Q15 PID Control.

-   * @param[in,out] S   points to an instance of the Q15 PID Control structure

-   * @param[in]     in  input sample to process

-   * @return out processed output sample.

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using a 64-bit internal accumulator.

-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.

-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.

-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.

-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.

-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.

-   */

-  static __INLINE q15_t arm_pid_q15(

-  arm_pid_instance_q15 * S,

-  q15_t in)

-  {

-    q63_t acc;

-    q15_t out;

-

-#ifndef ARM_MATH_CM0_FAMILY

-    __SIMD32_TYPE *vstate;

-

-    /* Implementation of PID controller */

-

-    /* acc = A0 * x[n]  */

-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);

-

-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */

-    vstate = __SIMD32_CONST(S->state);

-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);

-#else

-    /* acc = A0 * x[n]  */

-    acc = ((q31_t) S->A0) * in;

-

-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */

-    acc += (q31_t) S->A1 * S->state[0];

-    acc += (q31_t) S->A2 * S->state[1];

-#endif

-

-    /* acc += y[n-1] */

-    acc += (q31_t) S->state[2] << 15;

-

-    /* saturate the output */

-    out = (q15_t) (__SSAT((acc >> 15), 16));

-

-    /* Update state */

-    S->state[1] = S->state[0];

-    S->state[0] = in;

-    S->state[2] = out;

-

-    /* return to application */

-    return (out);

-  }

-

-  /**

-   * @} end of PID group

-   */

-

-

-  /**

-   * @brief Floating-point matrix inverse.

-   * @param[in]  src   points to the instance of the input floating-point matrix structure.

-   * @param[out] dst   points to the instance of the output floating-point matrix structure.

-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.

-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.

-   */

-  arm_status arm_mat_inverse_f32(

-  const arm_matrix_instance_f32 * src,

-  arm_matrix_instance_f32 * dst);

-

-

-  /**

-   * @brief Floating-point matrix inverse.

-   * @param[in]  src   points to the instance of the input floating-point matrix structure.

-   * @param[out] dst   points to the instance of the output floating-point matrix structure.

-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.

-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.

-   */

-  arm_status arm_mat_inverse_f64(

-  const arm_matrix_instance_f64 * src,

-  arm_matrix_instance_f64 * dst);

-

-

-

-  /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup clarke Vector Clarke Transform

-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.

-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents

-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.

-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below

-   * \image html clarke.gif Stator current space vector and its components in (a,b).

-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>

-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html clarkeFormula.gif

-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and

-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Clarke transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup clarke

-   * @{

-   */

-

-  /**

-   *

-   * @brief  Floating-point Clarke transform

-   * @param[in]  Ia       input three-phase coordinate <code>a</code>

-   * @param[in]  Ib       input three-phase coordinate <code>b</code>

-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha

-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta

-   */

-  static __INLINE void arm_clarke_f32(

-  float32_t Ia,

-  float32_t Ib,

-  float32_t * pIalpha,

-  float32_t * pIbeta)

-  {

-    /* Calculate pIalpha using the equation, pIalpha = Ia */

-    *pIalpha = Ia;

-

-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */

-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);

-  }

-

-

-  /**

-   * @brief  Clarke transform for Q31 version

-   * @param[in]  Ia       input three-phase coordinate <code>a</code>

-   * @param[in]  Ib       input three-phase coordinate <code>b</code>

-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha

-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the addition, hence there is no risk of overflow.

-   */

-  static __INLINE void arm_clarke_q31(

-  q31_t Ia,

-  q31_t Ib,

-  q31_t * pIalpha,

-  q31_t * pIbeta)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-

-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */

-    *pIalpha = Ia;

-

-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */

-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);

-

-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */

-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);

-

-    /* pIbeta is calculated by adding the intermediate products */

-    *pIbeta = __QADD(product1, product2);

-  }

-

-  /**

-   * @} end of clarke group

-   */

-

-  /**

-   * @brief  Converts the elements of the Q7 vector to Q31 vector.

-   * @param[in]  pSrc       input pointer

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_q7_to_q31(

-  q7_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-

-  /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup inv_clarke Vector Inverse Clarke Transform

-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html clarkeInvFormula.gif

-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and

-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Clarke transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup inv_clarke

-   * @{

-   */

-

-   /**

-   * @brief  Floating-point Inverse Clarke transform

-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha

-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta

-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>

-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>

-   */

-  static __INLINE void arm_inv_clarke_f32(

-  float32_t Ialpha,

-  float32_t Ibeta,

-  float32_t * pIa,

-  float32_t * pIb)

-  {

-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */

-    *pIa = Ialpha;

-

-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */

-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;

-  }

-

-

-  /**

-   * @brief  Inverse Clarke transform for Q31 version

-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha

-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta

-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>

-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the subtraction, hence there is no risk of overflow.

-   */

-  static __INLINE void arm_inv_clarke_q31(

-  q31_t Ialpha,

-  q31_t Ibeta,

-  q31_t * pIa,

-  q31_t * pIb)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-

-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */

-    *pIa = Ialpha;

-

-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */

-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);

-

-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */

-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);

-

-    /* pIb is calculated by subtracting the products */

-    *pIb = __QSUB(product2, product1);

-  }

-

-  /**

-   * @} end of inv_clarke group

-   */

-

-  /**

-   * @brief  Converts the elements of the Q7 vector to Q15 vector.

-   * @param[in]  pSrc       input pointer

-   * @param[out] pDst       output pointer

-   * @param[in]  blockSize  number of samples to process

-   */

-  void arm_q7_to_q15(

-  q7_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-

-  /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup park Vector Park Transform

-   *

-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.

-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents

-   * from the stationary to the moving reference frame and control the spatial relationship between

-   * the stator vector current and rotor flux vector.

-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the

-   * current vector and the relationship from the two reference frames:

-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html parkFormula.gif

-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,

-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the

-   * cosine and sine values of theta (rotor flux position).

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Park transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup park

-   * @{

-   */

-

-  /**

-   * @brief Floating-point Park transform

-   * @param[in]  Ialpha  input two-phase vector coordinate alpha

-   * @param[in]  Ibeta   input two-phase vector coordinate beta

-   * @param[out] pId     points to output   rotor reference frame d

-   * @param[out] pIq     points to output   rotor reference frame q

-   * @param[in]  sinVal  sine value of rotation angle theta

-   * @param[in]  cosVal  cosine value of rotation angle theta

-   *

-   * The function implements the forward Park transform.

-   *

-   */

-  static __INLINE void arm_park_f32(

-  float32_t Ialpha,

-  float32_t Ibeta,

-  float32_t * pId,

-  float32_t * pIq,

-  float32_t sinVal,

-  float32_t cosVal)

-  {

-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */

-    *pId = Ialpha * cosVal + Ibeta * sinVal;

-

-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */

-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;

-  }

-

-

-  /**

-   * @brief  Park transform for Q31 version

-   * @param[in]  Ialpha  input two-phase vector coordinate alpha

-   * @param[in]  Ibeta   input two-phase vector coordinate beta

-   * @param[out] pId     points to output rotor reference frame d

-   * @param[out] pIq     points to output rotor reference frame q

-   * @param[in]  sinVal  sine value of rotation angle theta

-   * @param[in]  cosVal  cosine value of rotation angle theta

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.

-   */

-  static __INLINE void arm_park_q31(

-  q31_t Ialpha,

-  q31_t Ibeta,

-  q31_t * pId,

-  q31_t * pIq,

-  q31_t sinVal,

-  q31_t cosVal)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */

-

-    /* Intermediate product is calculated by (Ialpha * cosVal) */

-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);

-

-    /* Intermediate product is calculated by (Ibeta * sinVal) */

-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);

-

-

-    /* Intermediate product is calculated by (Ialpha * sinVal) */

-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);

-

-    /* Intermediate product is calculated by (Ibeta * cosVal) */

-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);

-

-    /* Calculate pId by adding the two intermediate products 1 and 2 */

-    *pId = __QADD(product1, product2);

-

-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */

-    *pIq = __QSUB(product4, product3);

-  }

-

-  /**

-   * @} end of park group

-   */

-

-  /**

-   * @brief  Converts the elements of the Q7 vector to floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[out] pDst       is output pointer

-   * @param[in]  blockSize  is the number of samples to process

-   */

-  void arm_q7_to_float(

-  q7_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @ingroup groupController

-   */

-

-  /**

-   * @defgroup inv_park Vector Inverse Park transform

-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.

-   *

-   * The function operates on a single sample of data and each call to the function returns the processed output.

-   * The library provides separate functions for Q31 and floating-point data types.

-   * \par Algorithm

-   * \image html parkInvFormula.gif

-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,

-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the

-   * cosine and sine values of theta (rotor flux position).

-   * \par Fixed-Point Behavior

-   * Care must be taken when using the Q31 version of the Park transform.

-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.

-   * Refer to the function specific documentation below for usage guidelines.

-   */

-

-  /**

-   * @addtogroup inv_park

-   * @{

-   */

-

-   /**

-   * @brief  Floating-point Inverse Park transform

-   * @param[in]  Id       input coordinate of rotor reference frame d

-   * @param[in]  Iq       input coordinate of rotor reference frame q

-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha

-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta

-   * @param[in]  sinVal   sine value of rotation angle theta

-   * @param[in]  cosVal   cosine value of rotation angle theta

-   */

-  static __INLINE void arm_inv_park_f32(

-  float32_t Id,

-  float32_t Iq,

-  float32_t * pIalpha,

-  float32_t * pIbeta,

-  float32_t sinVal,

-  float32_t cosVal)

-  {

-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */

-    *pIalpha = Id * cosVal - Iq * sinVal;

-

-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */

-    *pIbeta = Id * sinVal + Iq * cosVal;

-  }

-

-

-  /**

-   * @brief  Inverse Park transform for   Q31 version

-   * @param[in]  Id       input coordinate of rotor reference frame d

-   * @param[in]  Iq       input coordinate of rotor reference frame q

-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha

-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta

-   * @param[in]  sinVal   sine value of rotation angle theta

-   * @param[in]  cosVal   cosine value of rotation angle theta

-   *

-   * <b>Scaling and Overflow Behavior:</b>

-   * \par

-   * The function is implemented using an internal 32-bit accumulator.

-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.

-   * There is saturation on the addition, hence there is no risk of overflow.

-   */

-  static __INLINE void arm_inv_park_q31(

-  q31_t Id,

-  q31_t Iq,

-  q31_t * pIalpha,

-  q31_t * pIbeta,

-  q31_t sinVal,

-  q31_t cosVal)

-  {

-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */

-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */

-

-    /* Intermediate product is calculated by (Id * cosVal) */

-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);

-

-    /* Intermediate product is calculated by (Iq * sinVal) */

-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);

-

-

-    /* Intermediate product is calculated by (Id * sinVal) */

-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);

-

-    /* Intermediate product is calculated by (Iq * cosVal) */

-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);

-

-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */

-    *pIalpha = __QSUB(product1, product2);

-

-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */

-    *pIbeta = __QADD(product4, product3);

-  }

-

-  /**

-   * @} end of Inverse park group

-   */

-

-

-  /**

-   * @brief  Converts the elements of the Q31 vector to floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[out] pDst       is output pointer

-   * @param[in]  blockSize  is the number of samples to process

-   */

-  void arm_q31_to_float(

-  q31_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-  /**

-   * @ingroup groupInterpolation

-   */

-

-  /**

-   * @defgroup LinearInterpolate Linear Interpolation

-   *

-   * Linear interpolation is a method of curve fitting using linear polynomials.

-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line

-   *

-   * \par

-   * \image html LinearInterp.gif "Linear interpolation"

-   *

-   * \par

-   * A  Linear Interpolate function calculates an output value(y), for the input(x)

-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)

-   *

-   * \par Algorithm:

-   * <pre>

-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))

-   *       where x0, x1 are nearest values of input x

-   *             y0, y1 are nearest values to output y

-   * </pre>

-   *

-   * \par

-   * This set of functions implements Linear interpolation process

-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single

-   * sample of data and each call to the function returns a single processed value.

-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.

-   * <code>x</code> is the input sample value. The functions returns the output value.

-   *

-   * \par

-   * if x is outside of the table boundary, Linear interpolation returns first value of the table

-   * if x is below input range and returns last value of table if x is above range.

-   */

-

-  /**

-   * @addtogroup LinearInterpolate

-   * @{

-   */

-

-  /**

-   * @brief  Process function for the floating-point Linear Interpolation Function.

-   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure

-   * @param[in]     x  input sample to process

-   * @return y processed output sample.

-   *

-   */

-  static __INLINE float32_t arm_linear_interp_f32(

-  arm_linear_interp_instance_f32 * S,

-  float32_t x)

-  {

-    float32_t y;

-    float32_t x0, x1;                            /* Nearest input values */

-    float32_t y0, y1;                            /* Nearest output values */

-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */

-    int32_t i;                                   /* Index variable */

-    float32_t *pYData = S->pYData;               /* pointer to output table */

-

-    /* Calculation of index */

-    i = (int32_t) ((x - S->x1) / xSpacing);

-

-    if(i < 0)

-    {

-      /* Iniatilize output for below specified range as least output value of table */

-      y = pYData[0];

-    }

-    else if((uint32_t)i >= S->nValues)

-    {

-      /* Iniatilize output for above specified range as last output value of table */

-      y = pYData[S->nValues - 1];

-    }

-    else

-    {

-      /* Calculation of nearest input values */

-      x0 = S->x1 +  i      * xSpacing;

-      x1 = S->x1 + (i + 1) * xSpacing;

-

-      /* Read of nearest output values */

-      y0 = pYData[i];

-      y1 = pYData[i + 1];

-

-      /* Calculation of output */

-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));

-

-    }

-

-    /* returns output value */

-    return (y);

-  }

-

-

-   /**

-   *

-   * @brief  Process function for the Q31 Linear Interpolation Function.

-   * @param[in] pYData   pointer to Q31 Linear Interpolation table

-   * @param[in] x        input sample to process

-   * @param[in] nValues  number of table values

-   * @return y processed output sample.

-   *

-   * \par

-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.

-   * This function can support maximum of table size 2^12.

-   *

-   */

-  static __INLINE q31_t arm_linear_interp_q31(

-  q31_t * pYData,

-  q31_t x,

-  uint32_t nValues)

-  {

-    q31_t y;                                     /* output */

-    q31_t y0, y1;                                /* Nearest output values */

-    q31_t fract;                                 /* fractional part */

-    int32_t index;                               /* Index to read nearest output values */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    index = ((x & (q31_t)0xFFF00000) >> 20);

-

-    if(index >= (int32_t)(nValues - 1))

-    {

-      return (pYData[nValues - 1]);

-    }

-    else if(index < 0)

-    {

-      return (pYData[0]);

-    }

-    else

-    {

-      /* 20 bits for the fractional part */

-      /* shift left by 11 to keep fract in 1.31 format */

-      fract = (x & 0x000FFFFF) << 11;

-

-      /* Read two nearest output values from the index in 1.31(q31) format */

-      y0 = pYData[index];

-      y1 = pYData[index + 1];

-

-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */

-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));

-

-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */

-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));

-

-      /* Convert y to 1.31 format */

-      return (y << 1u);

-    }

-  }

-

-

-  /**

-   *

-   * @brief  Process function for the Q15 Linear Interpolation Function.

-   * @param[in] pYData   pointer to Q15 Linear Interpolation table

-   * @param[in] x        input sample to process

-   * @param[in] nValues  number of table values

-   * @return y processed output sample.

-   *

-   * \par

-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.

-   * This function can support maximum of table size 2^12.

-   *

-   */

-  static __INLINE q15_t arm_linear_interp_q15(

-  q15_t * pYData,

-  q31_t x,

-  uint32_t nValues)

-  {

-    q63_t y;                                     /* output */

-    q15_t y0, y1;                                /* Nearest output values */

-    q31_t fract;                                 /* fractional part */

-    int32_t index;                               /* Index to read nearest output values */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    index = ((x & (int32_t)0xFFF00000) >> 20);

-

-    if(index >= (int32_t)(nValues - 1))

-    {

-      return (pYData[nValues - 1]);

-    }

-    else if(index < 0)

-    {

-      return (pYData[0]);

-    }

-    else

-    {

-      /* 20 bits for the fractional part */

-      /* fract is in 12.20 format */

-      fract = (x & 0x000FFFFF);

-

-      /* Read two nearest output values from the index */

-      y0 = pYData[index];

-      y1 = pYData[index + 1];

-

-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */

-      y = ((q63_t) y0 * (0xFFFFF - fract));

-

-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */

-      y += ((q63_t) y1 * (fract));

-

-      /* convert y to 1.15 format */

-      return (q15_t) (y >> 20);

-    }

-  }

-

-

-  /**

-   *

-   * @brief  Process function for the Q7 Linear Interpolation Function.

-   * @param[in] pYData   pointer to Q7 Linear Interpolation table

-   * @param[in] x        input sample to process

-   * @param[in] nValues  number of table values

-   * @return y processed output sample.

-   *

-   * \par

-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.

-   * This function can support maximum of table size 2^12.

-   */

-  static __INLINE q7_t arm_linear_interp_q7(

-  q7_t * pYData,

-  q31_t x,

-  uint32_t nValues)

-  {

-    q31_t y;                                     /* output */

-    q7_t y0, y1;                                 /* Nearest output values */

-    q31_t fract;                                 /* fractional part */

-    uint32_t index;                              /* Index to read nearest output values */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    if (x < 0)

-    {

-      return (pYData[0]);

-    }

-    index = (x >> 20) & 0xfff;

-

-    if(index >= (nValues - 1))

-    {

-      return (pYData[nValues - 1]);

-    }

-    else

-    {

-      /* 20 bits for the fractional part */

-      /* fract is in 12.20 format */

-      fract = (x & 0x000FFFFF);

-

-      /* Read two nearest output values from the index and are in 1.7(q7) format */

-      y0 = pYData[index];

-      y1 = pYData[index + 1];

-

-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */

-      y = ((y0 * (0xFFFFF - fract)));

-

-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */

-      y += (y1 * fract);

-

-      /* convert y to 1.7(q7) format */

-      return (q7_t) (y >> 20);

-     }

-  }

-

-  /**

-   * @} end of LinearInterpolate group

-   */

-

-  /**

-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.

-   * @param[in] x  input value in radians.

-   * @return  sin(x).

-   */

-  float32_t arm_sin_f32(

-  float32_t x);

-

-

-  /**

-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.

-   * @param[in] x  Scaled input value in radians.

-   * @return  sin(x).

-   */

-  q31_t arm_sin_q31(

-  q31_t x);

-

-

-  /**

-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.

-   * @param[in] x  Scaled input value in radians.

-   * @return  sin(x).

-   */

-  q15_t arm_sin_q15(

-  q15_t x);

-

-

-  /**

-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.

-   * @param[in] x  input value in radians.

-   * @return  cos(x).

-   */

-  float32_t arm_cos_f32(

-  float32_t x);

-

-

-  /**

-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.

-   * @param[in] x  Scaled input value in radians.

-   * @return  cos(x).

-   */

-  q31_t arm_cos_q31(

-  q31_t x);

-

-

-  /**

-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.

-   * @param[in] x  Scaled input value in radians.

-   * @return  cos(x).

-   */

-  q15_t arm_cos_q15(

-  q15_t x);

-

-

-  /**

-   * @ingroup groupFastMath

-   */

-

-

-  /**

-   * @defgroup SQRT Square Root

-   *

-   * Computes the square root of a number.

-   * There are separate functions for Q15, Q31, and floating-point data types.

-   * The square root function is computed using the Newton-Raphson algorithm.

-   * This is an iterative algorithm of the form:

-   * <pre>

-   *      x1 = x0 - f(x0)/f'(x0)

-   * </pre>

-   * where <code>x1</code> is the current estimate,

-   * <code>x0</code> is the previous estimate, and

-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.

-   * For the square root function, the algorithm reduces to:

-   * <pre>

-   *     x0 = in/2                         [initial guess]

-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]

-   * </pre>

-   */

-

-

-  /**

-   * @addtogroup SQRT

-   * @{

-   */

-

-  /**

-   * @brief  Floating-point square root function.

-   * @param[in]  in    input value.

-   * @param[out] pOut  square root of input value.

-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if

-   * <code>in</code> is negative value and returns zero output for negative values.

-   */

-  static __INLINE arm_status arm_sqrt_f32(

-  float32_t in,

-  float32_t * pOut)

-  {

-    if(in >= 0.0f)

-    {

-

-#if   (__FPU_USED == 1) && defined ( __CC_ARM   )

-      *pOut = __sqrtf(in);

-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))

-      *pOut = __builtin_sqrtf(in);

-#elif (__FPU_USED == 1) && defined(__GNUC__)

-      *pOut = __builtin_sqrtf(in);

-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)

-      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));

-#else

-      *pOut = sqrtf(in);

-#endif

-

-      return (ARM_MATH_SUCCESS);

-    }

-    else

-    {

-      *pOut = 0.0f;

-      return (ARM_MATH_ARGUMENT_ERROR);

-    }

-  }

-

-

-  /**

-   * @brief Q31 square root function.

-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.

-   * @param[out] pOut  square root of input value.

-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if

-   * <code>in</code> is negative value and returns zero output for negative values.

-   */

-  arm_status arm_sqrt_q31(

-  q31_t in,

-  q31_t * pOut);

-

-

-  /**

-   * @brief  Q15 square root function.

-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.

-   * @param[out] pOut  square root of input value.

-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if

-   * <code>in</code> is negative value and returns zero output for negative values.

-   */

-  arm_status arm_sqrt_q15(

-  q15_t in,

-  q15_t * pOut);

-

-  /**

-   * @} end of SQRT group

-   */

-

-

-  /**

-   * @brief floating-point Circular write function.

-   */

-  static __INLINE void arm_circularWrite_f32(

-  int32_t * circBuffer,

-  int32_t L,

-  uint16_t * writeOffset,

-  int32_t bufferInc,

-  const int32_t * src,

-  int32_t srcInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t wOffset;

-

-    /* Copy the value of Index pointer that points

-     * to the current location where the input samples to be copied */

-    wOffset = *writeOffset;

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the input sample to the circular buffer */

-      circBuffer[wOffset] = *src;

-

-      /* Update the input pointer */

-      src += srcInc;

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      wOffset += bufferInc;

-      if(wOffset >= L)

-        wOffset -= L;

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *writeOffset = (uint16_t)wOffset;

-  }

-

-

-

-  /**

-   * @brief floating-point Circular Read function.

-   */

-  static __INLINE void arm_circularRead_f32(

-  int32_t * circBuffer,

-  int32_t L,

-  int32_t * readOffset,

-  int32_t bufferInc,

-  int32_t * dst,

-  int32_t * dst_base,

-  int32_t dst_length,

-  int32_t dstInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t rOffset, dst_end;

-

-    /* Copy the value of Index pointer that points

-     * to the current location from where the input samples to be read */

-    rOffset = *readOffset;

-    dst_end = (int32_t) (dst_base + dst_length);

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the sample from the circular buffer to the destination buffer */

-      *dst = circBuffer[rOffset];

-

-      /* Update the input pointer */

-      dst += dstInc;

-

-      if(dst == (int32_t *) dst_end)

-      {

-        dst = dst_base;

-      }

-

-      /* Circularly update rOffset.  Watch out for positive and negative value  */

-      rOffset += bufferInc;

-

-      if(rOffset >= L)

-      {

-        rOffset -= L;

-      }

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *readOffset = rOffset;

-  }

-

-

-  /**

-   * @brief Q15 Circular write function.

-   */

-  static __INLINE void arm_circularWrite_q15(

-  q15_t * circBuffer,

-  int32_t L,

-  uint16_t * writeOffset,

-  int32_t bufferInc,

-  const q15_t * src,

-  int32_t srcInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t wOffset;

-

-    /* Copy the value of Index pointer that points

-     * to the current location where the input samples to be copied */

-    wOffset = *writeOffset;

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the input sample to the circular buffer */

-      circBuffer[wOffset] = *src;

-

-      /* Update the input pointer */

-      src += srcInc;

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      wOffset += bufferInc;

-      if(wOffset >= L)

-        wOffset -= L;

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *writeOffset = (uint16_t)wOffset;

-  }

-

-

-  /**

-   * @brief Q15 Circular Read function.

-   */

-  static __INLINE void arm_circularRead_q15(

-  q15_t * circBuffer,

-  int32_t L,

-  int32_t * readOffset,

-  int32_t bufferInc,

-  q15_t * dst,

-  q15_t * dst_base,

-  int32_t dst_length,

-  int32_t dstInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0;

-    int32_t rOffset, dst_end;

-

-    /* Copy the value of Index pointer that points

-     * to the current location from where the input samples to be read */

-    rOffset = *readOffset;

-

-    dst_end = (int32_t) (dst_base + dst_length);

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the sample from the circular buffer to the destination buffer */

-      *dst = circBuffer[rOffset];

-

-      /* Update the input pointer */

-      dst += dstInc;

-

-      if(dst == (q15_t *) dst_end)

-      {

-        dst = dst_base;

-      }

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      rOffset += bufferInc;

-

-      if(rOffset >= L)

-      {

-        rOffset -= L;

-      }

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *readOffset = rOffset;

-  }

-

-

-  /**

-   * @brief Q7 Circular write function.

-   */

-  static __INLINE void arm_circularWrite_q7(

-  q7_t * circBuffer,

-  int32_t L,

-  uint16_t * writeOffset,

-  int32_t bufferInc,

-  const q7_t * src,

-  int32_t srcInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0u;

-    int32_t wOffset;

-

-    /* Copy the value of Index pointer that points

-     * to the current location where the input samples to be copied */

-    wOffset = *writeOffset;

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the input sample to the circular buffer */

-      circBuffer[wOffset] = *src;

-

-      /* Update the input pointer */

-      src += srcInc;

-

-      /* Circularly update wOffset.  Watch out for positive and negative value */

-      wOffset += bufferInc;

-      if(wOffset >= L)

-        wOffset -= L;

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *writeOffset = (uint16_t)wOffset;

-  }

-

-

-  /**

-   * @brief Q7 Circular Read function.

-   */

-  static __INLINE void arm_circularRead_q7(

-  q7_t * circBuffer,

-  int32_t L,

-  int32_t * readOffset,

-  int32_t bufferInc,

-  q7_t * dst,

-  q7_t * dst_base,

-  int32_t dst_length,

-  int32_t dstInc,

-  uint32_t blockSize)

-  {

-    uint32_t i = 0;

-    int32_t rOffset, dst_end;

-

-    /* Copy the value of Index pointer that points

-     * to the current location from where the input samples to be read */

-    rOffset = *readOffset;

-

-    dst_end = (int32_t) (dst_base + dst_length);

-

-    /* Loop over the blockSize */

-    i = blockSize;

-

-    while(i > 0u)

-    {

-      /* copy the sample from the circular buffer to the destination buffer */

-      *dst = circBuffer[rOffset];

-

-      /* Update the input pointer */

-      dst += dstInc;

-

-      if(dst == (q7_t *) dst_end)

-      {

-        dst = dst_base;

-      }

-

-      /* Circularly update rOffset.  Watch out for positive and negative value */

-      rOffset += bufferInc;

-

-      if(rOffset >= L)

-      {

-        rOffset -= L;

-      }

-

-      /* Decrement the loop counter */

-      i--;

-    }

-

-    /* Update the index pointer */

-    *readOffset = rOffset;

-  }

-

-

-  /**

-   * @brief  Sum of the squares of the elements of a Q31 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_power_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q63_t * pResult);

-

-

-  /**

-   * @brief  Sum of the squares of the elements of a floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_power_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-

-  /**

-   * @brief  Sum of the squares of the elements of a Q15 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_power_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q63_t * pResult);

-

-

-  /**

-   * @brief  Sum of the squares of the elements of a Q7 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_power_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-

-  /**

-   * @brief  Mean value of a Q7 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_mean_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q7_t * pResult);

-

-

-  /**

-   * @brief  Mean value of a Q15 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_mean_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-

-  /**

-   * @brief  Mean value of a Q31 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_mean_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-

-  /**

-   * @brief  Mean value of a floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_mean_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-

-  /**

-   * @brief  Variance of the elements of a floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_var_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-

-  /**

-   * @brief  Variance of the elements of a Q31 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_var_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-

-  /**

-   * @brief  Variance of the elements of a Q15 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_var_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-

-  /**

-   * @brief  Root Mean Square of the elements of a floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_rms_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-

-  /**

-   * @brief  Root Mean Square of the elements of a Q31 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_rms_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-

-  /**

-   * @brief  Root Mean Square of the elements of a Q15 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_rms_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-

-  /**

-   * @brief  Standard deviation of the elements of a floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_std_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult);

-

-

-  /**

-   * @brief  Standard deviation of the elements of a Q31 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_std_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult);

-

-

-  /**

-   * @brief  Standard deviation of the elements of a Q15 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output value.

-   */

-  void arm_std_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult);

-

-

-  /**

-   * @brief  Floating-point complex magnitude

-   * @param[in]  pSrc        points to the complex input vector

-   * @param[out] pDst        points to the real output vector

-   * @param[in]  numSamples  number of complex samples in the input vector

-   */

-  void arm_cmplx_mag_f32(

-  float32_t * pSrc,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q31 complex magnitude

-   * @param[in]  pSrc        points to the complex input vector

-   * @param[out] pDst        points to the real output vector

-   * @param[in]  numSamples  number of complex samples in the input vector

-   */

-  void arm_cmplx_mag_q31(

-  q31_t * pSrc,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q15 complex magnitude

-   * @param[in]  pSrc        points to the complex input vector

-   * @param[out] pDst        points to the real output vector

-   * @param[in]  numSamples  number of complex samples in the input vector

-   */

-  void arm_cmplx_mag_q15(

-  q15_t * pSrc,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q15 complex dot product

-   * @param[in]  pSrcA       points to the first input vector

-   * @param[in]  pSrcB       points to the second input vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   * @param[out] realResult  real part of the result returned here

-   * @param[out] imagResult  imaginary part of the result returned here

-   */

-  void arm_cmplx_dot_prod_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  uint32_t numSamples,

-  q31_t * realResult,

-  q31_t * imagResult);

-

-

-  /**

-   * @brief  Q31 complex dot product

-   * @param[in]  pSrcA       points to the first input vector

-   * @param[in]  pSrcB       points to the second input vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   * @param[out] realResult  real part of the result returned here

-   * @param[out] imagResult  imaginary part of the result returned here

-   */

-  void arm_cmplx_dot_prod_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  uint32_t numSamples,

-  q63_t * realResult,

-  q63_t * imagResult);

-

-

-  /**

-   * @brief  Floating-point complex dot product

-   * @param[in]  pSrcA       points to the first input vector

-   * @param[in]  pSrcB       points to the second input vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   * @param[out] realResult  real part of the result returned here

-   * @param[out] imagResult  imaginary part of the result returned here

-   */

-  void arm_cmplx_dot_prod_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  uint32_t numSamples,

-  float32_t * realResult,

-  float32_t * imagResult);

-

-

-  /**

-   * @brief  Q15 complex-by-real multiplication

-   * @param[in]  pSrcCmplx   points to the complex input vector

-   * @param[in]  pSrcReal    points to the real input vector

-   * @param[out] pCmplxDst   points to the complex output vector

-   * @param[in]  numSamples  number of samples in each vector

-   */

-  void arm_cmplx_mult_real_q15(

-  q15_t * pSrcCmplx,

-  q15_t * pSrcReal,

-  q15_t * pCmplxDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q31 complex-by-real multiplication

-   * @param[in]  pSrcCmplx   points to the complex input vector

-   * @param[in]  pSrcReal    points to the real input vector

-   * @param[out] pCmplxDst   points to the complex output vector

-   * @param[in]  numSamples  number of samples in each vector

-   */

-  void arm_cmplx_mult_real_q31(

-  q31_t * pSrcCmplx,

-  q31_t * pSrcReal,

-  q31_t * pCmplxDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Floating-point complex-by-real multiplication

-   * @param[in]  pSrcCmplx   points to the complex input vector

-   * @param[in]  pSrcReal    points to the real input vector

-   * @param[out] pCmplxDst   points to the complex output vector

-   * @param[in]  numSamples  number of samples in each vector

-   */

-  void arm_cmplx_mult_real_f32(

-  float32_t * pSrcCmplx,

-  float32_t * pSrcReal,

-  float32_t * pCmplxDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Minimum value of a Q7 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] result     is output pointer

-   * @param[in]  index      is the array index of the minimum value in the input buffer.

-   */

-  void arm_min_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q7_t * result,

-  uint32_t * index);

-

-

-  /**

-   * @brief  Minimum value of a Q15 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output pointer

-   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.

-   */

-  void arm_min_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult,

-  uint32_t * pIndex);

-

-

-  /**

-   * @brief  Minimum value of a Q31 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output pointer

-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.

-   */

-  void arm_min_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult,

-  uint32_t * pIndex);

-

-

-  /**

-   * @brief  Minimum value of a floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[in]  blockSize  is the number of samples to process

-   * @param[out] pResult    is output pointer

-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.

-   */

-  void arm_min_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult,

-  uint32_t * pIndex);

-

-

-/**

- * @brief Maximum value of a Q7 vector.

- * @param[in]  pSrc       points to the input buffer

- * @param[in]  blockSize  length of the input vector

- * @param[out] pResult    maximum value returned here

- * @param[out] pIndex     index of maximum value returned here

- */

-  void arm_max_q7(

-  q7_t * pSrc,

-  uint32_t blockSize,

-  q7_t * pResult,

-  uint32_t * pIndex);

-

-

-/**

- * @brief Maximum value of a Q15 vector.

- * @param[in]  pSrc       points to the input buffer

- * @param[in]  blockSize  length of the input vector

- * @param[out] pResult    maximum value returned here

- * @param[out] pIndex     index of maximum value returned here

- */

-  void arm_max_q15(

-  q15_t * pSrc,

-  uint32_t blockSize,

-  q15_t * pResult,

-  uint32_t * pIndex);

-

-

-/**

- * @brief Maximum value of a Q31 vector.

- * @param[in]  pSrc       points to the input buffer

- * @param[in]  blockSize  length of the input vector

- * @param[out] pResult    maximum value returned here

- * @param[out] pIndex     index of maximum value returned here

- */

-  void arm_max_q31(

-  q31_t * pSrc,

-  uint32_t blockSize,

-  q31_t * pResult,

-  uint32_t * pIndex);

-

-

-/**

- * @brief Maximum value of a floating-point vector.

- * @param[in]  pSrc       points to the input buffer

- * @param[in]  blockSize  length of the input vector

- * @param[out] pResult    maximum value returned here

- * @param[out] pIndex     index of maximum value returned here

- */

-  void arm_max_f32(

-  float32_t * pSrc,

-  uint32_t blockSize,

-  float32_t * pResult,

-  uint32_t * pIndex);

-

-

-  /**

-   * @brief  Q15 complex-by-complex multiplication

-   * @param[in]  pSrcA       points to the first input vector

-   * @param[in]  pSrcB       points to the second input vector

-   * @param[out] pDst        points to the output vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   */

-  void arm_cmplx_mult_cmplx_q15(

-  q15_t * pSrcA,

-  q15_t * pSrcB,

-  q15_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Q31 complex-by-complex multiplication

-   * @param[in]  pSrcA       points to the first input vector

-   * @param[in]  pSrcB       points to the second input vector

-   * @param[out] pDst        points to the output vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   */

-  void arm_cmplx_mult_cmplx_q31(

-  q31_t * pSrcA,

-  q31_t * pSrcB,

-  q31_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief  Floating-point complex-by-complex multiplication

-   * @param[in]  pSrcA       points to the first input vector

-   * @param[in]  pSrcB       points to the second input vector

-   * @param[out] pDst        points to the output vector

-   * @param[in]  numSamples  number of complex samples in each vector

-   */

-  void arm_cmplx_mult_cmplx_f32(

-  float32_t * pSrcA,

-  float32_t * pSrcB,

-  float32_t * pDst,

-  uint32_t numSamples);

-

-

-  /**

-   * @brief Converts the elements of the floating-point vector to Q31 vector.

-   * @param[in]  pSrc       points to the floating-point input vector

-   * @param[out] pDst       points to the Q31 output vector

-   * @param[in]  blockSize  length of the input vector

-   */

-  void arm_float_to_q31(

-  float32_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Converts the elements of the floating-point vector to Q15 vector.

-   * @param[in]  pSrc       points to the floating-point input vector

-   * @param[out] pDst       points to the Q15 output vector

-   * @param[in]  blockSize  length of the input vector

-   */

-  void arm_float_to_q15(

-  float32_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief Converts the elements of the floating-point vector to Q7 vector.

-   * @param[in]  pSrc       points to the floating-point input vector

-   * @param[out] pDst       points to the Q7 output vector

-   * @param[in]  blockSize  length of the input vector

-   */

-  void arm_float_to_q7(

-  float32_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q31 vector to Q15 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[out] pDst       is output pointer

-   * @param[in]  blockSize  is the number of samples to process

-   */

-  void arm_q31_to_q15(

-  q31_t * pSrc,

-  q15_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q31 vector to Q7 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[out] pDst       is output pointer

-   * @param[in]  blockSize  is the number of samples to process

-   */

-  void arm_q31_to_q7(

-  q31_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q15 vector to floating-point vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[out] pDst       is output pointer

-   * @param[in]  blockSize  is the number of samples to process

-   */

-  void arm_q15_to_float(

-  q15_t * pSrc,

-  float32_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q15 vector to Q31 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[out] pDst       is output pointer

-   * @param[in]  blockSize  is the number of samples to process

-   */

-  void arm_q15_to_q31(

-  q15_t * pSrc,

-  q31_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @brief  Converts the elements of the Q15 vector to Q7 vector.

-   * @param[in]  pSrc       is input pointer

-   * @param[out] pDst       is output pointer

-   * @param[in]  blockSize  is the number of samples to process

-   */

-  void arm_q15_to_q7(

-  q15_t * pSrc,

-  q7_t * pDst,

-  uint32_t blockSize);

-

-

-  /**

-   * @ingroup groupInterpolation

-   */

-

-  /**

-   * @defgroup BilinearInterpolate Bilinear Interpolation

-   *

-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.

-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process

-   * determines values between the grid points.

-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.

-   * Bilinear interpolation is often used in image processing to rescale images.

-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.

-   *

-   * <b>Algorithm</b>

-   * \par

-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.

-   * For floating-point, the instance structure is defined as:

-   * <pre>

-   *   typedef struct

-   *   {

-   *     uint16_t numRows;

-   *     uint16_t numCols;

-   *     float32_t *pData;

-   * } arm_bilinear_interp_instance_f32;

-   * </pre>

-   *

-   * \par

-   * where <code>numRows</code> specifies the number of rows in the table;

-   * <code>numCols</code> specifies the number of columns in the table;

-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.

-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.

-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.

-   *

-   * \par

-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:

-   * <pre>

-   *     XF = floor(x)

-   *     YF = floor(y)

-   * </pre>

-   * \par

-   * The interpolated output point is computed as:

-   * <pre>

-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))

-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))

-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)

-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)

-   * </pre>

-   * Note that the coordinates (x, y) contain integer and fractional components.

-   * The integer components specify which portion of the table to use while the

-   * fractional components control the interpolation processor.

-   *

-   * \par

-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.

-   */

-

-  /**

-   * @addtogroup BilinearInterpolate

-   * @{

-   */

-

-

-  /**

-  *

-  * @brief  Floating-point bilinear interpolation.

-  * @param[in,out] S  points to an instance of the interpolation structure.

-  * @param[in]     X  interpolation coordinate.

-  * @param[in]     Y  interpolation coordinate.

-  * @return out interpolated value.

-  */

-  static __INLINE float32_t arm_bilinear_interp_f32(

-  const arm_bilinear_interp_instance_f32 * S,

-  float32_t X,

-  float32_t Y)

-  {

-    float32_t out;

-    float32_t f00, f01, f10, f11;

-    float32_t *pData = S->pData;

-    int32_t xIndex, yIndex, index;

-    float32_t xdiff, ydiff;

-    float32_t b1, b2, b3, b4;

-

-    xIndex = (int32_t) X;

-    yIndex = (int32_t) Y;

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* Calculation of index for two nearest points in X-direction */

-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;

-

-

-    /* Read two nearest points in X-direction */

-    f00 = pData[index];

-    f01 = pData[index + 1];

-

-    /* Calculation of index for two nearest points in Y-direction */

-    index = (xIndex - 1) + (yIndex) * S->numCols;

-

-

-    /* Read two nearest points in Y-direction */

-    f10 = pData[index];

-    f11 = pData[index + 1];

-

-    /* Calculation of intermediate values */

-    b1 = f00;

-    b2 = f01 - f00;

-    b3 = f10 - f00;

-    b4 = f00 - f01 - f10 + f11;

-

-    /* Calculation of fractional part in X */

-    xdiff = X - xIndex;

-

-    /* Calculation of fractional part in Y */

-    ydiff = Y - yIndex;

-

-    /* Calculation of bi-linear interpolated output */

-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;

-

-    /* return to application */

-    return (out);

-  }

-

-

-  /**

-  *

-  * @brief  Q31 bilinear interpolation.

-  * @param[in,out] S  points to an instance of the interpolation structure.

-  * @param[in]     X  interpolation coordinate in 12.20 format.

-  * @param[in]     Y  interpolation coordinate in 12.20 format.

-  * @return out interpolated value.

-  */

-  static __INLINE q31_t arm_bilinear_interp_q31(

-  arm_bilinear_interp_instance_q31 * S,

-  q31_t X,

-  q31_t Y)

-  {

-    q31_t out;                                   /* Temporary output */

-    q31_t acc = 0;                               /* output */

-    q31_t xfract, yfract;                        /* X, Y fractional parts */

-    q31_t x1, x2, y1, y2;                        /* Nearest output values */

-    int32_t rI, cI;                              /* Row and column indices */

-    q31_t *pYData = S->pData;                    /* pointer to output table values */

-    uint32_t nCols = S->numCols;                 /* num of rows */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    rI = ((X & (q31_t)0xFFF00000) >> 20);

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    cI = ((Y & (q31_t)0xFFF00000) >> 20);

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* 20 bits for the fractional part */

-    /* shift left xfract by 11 to keep 1.31 format */

-    xfract = (X & 0x000FFFFF) << 11u;

-

-    /* Read two nearest output values from the index */

-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];

-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];

-

-    /* 20 bits for the fractional part */

-    /* shift left yfract by 11 to keep 1.31 format */

-    yfract = (Y & 0x000FFFFF) << 11u;

-

-    /* Read two nearest output values from the index */

-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];

-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];

-

-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */

-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));

-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));

-

-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */

-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));

-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));

-

-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */

-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));

-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));

-

-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */

-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));

-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));

-

-    /* Convert acc to 1.31(q31) format */

-    return ((q31_t)(acc << 2));

-  }

-

-

-  /**

-  * @brief  Q15 bilinear interpolation.

-  * @param[in,out] S  points to an instance of the interpolation structure.

-  * @param[in]     X  interpolation coordinate in 12.20 format.

-  * @param[in]     Y  interpolation coordinate in 12.20 format.

-  * @return out interpolated value.

-  */

-  static __INLINE q15_t arm_bilinear_interp_q15(

-  arm_bilinear_interp_instance_q15 * S,

-  q31_t X,

-  q31_t Y)

-  {

-    q63_t acc = 0;                               /* output */

-    q31_t out;                                   /* Temporary output */

-    q15_t x1, x2, y1, y2;                        /* Nearest output values */

-    q31_t xfract, yfract;                        /* X, Y fractional parts */

-    int32_t rI, cI;                              /* Row and column indices */

-    q15_t *pYData = S->pData;                    /* pointer to output table values */

-    uint32_t nCols = S->numCols;                 /* num of rows */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    rI = ((X & (q31_t)0xFFF00000) >> 20);

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    cI = ((Y & (q31_t)0xFFF00000) >> 20);

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* 20 bits for the fractional part */

-    /* xfract should be in 12.20 format */

-    xfract = (X & 0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];

-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];

-

-    /* 20 bits for the fractional part */

-    /* yfract should be in 12.20 format */

-    yfract = (Y & 0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];

-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];

-

-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */

-

-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */

-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */

-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);

-    acc = ((q63_t) out * (0xFFFFF - yfract));

-

-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */

-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);

-    acc += ((q63_t) out * (xfract));

-

-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */

-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);

-    acc += ((q63_t) out * (yfract));

-

-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */

-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);

-    acc += ((q63_t) out * (yfract));

-

-    /* acc is in 13.51 format and down shift acc by 36 times */

-    /* Convert out to 1.15 format */

-    return ((q15_t)(acc >> 36));

-  }

-

-

-  /**

-  * @brief  Q7 bilinear interpolation.

-  * @param[in,out] S  points to an instance of the interpolation structure.

-  * @param[in]     X  interpolation coordinate in 12.20 format.

-  * @param[in]     Y  interpolation coordinate in 12.20 format.

-  * @return out interpolated value.

-  */

-  static __INLINE q7_t arm_bilinear_interp_q7(

-  arm_bilinear_interp_instance_q7 * S,

-  q31_t X,

-  q31_t Y)

-  {

-    q63_t acc = 0;                               /* output */

-    q31_t out;                                   /* Temporary output */

-    q31_t xfract, yfract;                        /* X, Y fractional parts */

-    q7_t x1, x2, y1, y2;                         /* Nearest output values */

-    int32_t rI, cI;                              /* Row and column indices */

-    q7_t *pYData = S->pData;                     /* pointer to output table values */

-    uint32_t nCols = S->numCols;                 /* num of rows */

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    rI = ((X & (q31_t)0xFFF00000) >> 20);

-

-    /* Input is in 12.20 format */

-    /* 12 bits for the table index */

-    /* Index value calculation */

-    cI = ((Y & (q31_t)0xFFF00000) >> 20);

-

-    /* Care taken for table outside boundary */

-    /* Returns zero output when values are outside table boundary */

-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))

-    {

-      return (0);

-    }

-

-    /* 20 bits for the fractional part */

-    /* xfract should be in 12.20 format */

-    xfract = (X & (q31_t)0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];

-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];

-

-    /* 20 bits for the fractional part */

-    /* yfract should be in 12.20 format */

-    yfract = (Y & (q31_t)0x000FFFFF);

-

-    /* Read two nearest output values from the index */

-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];

-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];

-

-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */

-    out = ((x1 * (0xFFFFF - xfract)));

-    acc = (((q63_t) out * (0xFFFFF - yfract)));

-

-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */

-    out = ((x2 * (0xFFFFF - yfract)));

-    acc += (((q63_t) out * (xfract)));

-

-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */

-    out = ((y1 * (0xFFFFF - xfract)));

-    acc += (((q63_t) out * (yfract)));

-

-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */

-    out = ((y2 * (yfract)));

-    acc += (((q63_t) out * (xfract)));

-

-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */

-    return ((q7_t)(acc >> 40));

-  }

-

-  /**

-   * @} end of BilinearInterpolate group

-   */

-

-

-/* SMMLAR */

-#define multAcc_32x32_keep32_R(a, x, y) \

-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)

-

-/* SMMLSR */

-#define multSub_32x32_keep32_R(a, x, y) \

-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)

-

-/* SMMULR */

-#define mult_32x32_keep32_R(a, x, y) \

-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)

-

-/* SMMLA */

-#define multAcc_32x32_keep32(a, x, y) \

-    a += (q31_t) (((q63_t) x * y) >> 32)

-

-/* SMMLS */

-#define multSub_32x32_keep32(a, x, y) \

-    a -= (q31_t) (((q63_t) x * y) >> 32)

-

-/* SMMUL */

-#define mult_32x32_keep32(a, x, y) \

-    a = (q31_t) (((q63_t) x * y ) >> 32)

-

-

-#if defined ( __CC_ARM )

-  /* Enter low optimization region - place directly above function definition */

-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)

-    #define LOW_OPTIMIZATION_ENTER \

-       _Pragma ("push")         \

-       _Pragma ("O1")

-  #else

-    #define LOW_OPTIMIZATION_ENTER

-  #endif

-

-  /* Exit low optimization region - place directly after end of function definition */

-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)

-    #define LOW_OPTIMIZATION_EXIT \

-       _Pragma ("pop")

-  #else

-    #define LOW_OPTIMIZATION_EXIT

-  #endif

-

-  /* Enter low optimization region - place directly above function definition */

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-

-  /* Exit low optimization region - place directly after end of function definition */

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #define LOW_OPTIMIZATION_ENTER

-  #define LOW_OPTIMIZATION_EXIT

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__GNUC__)

-  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))

-  #define LOW_OPTIMIZATION_EXIT

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__ICCARM__)

-  /* Enter low optimization region - place directly above function definition */

-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)

-    #define LOW_OPTIMIZATION_ENTER \

-       _Pragma ("optimize=low")

-  #else

-    #define LOW_OPTIMIZATION_ENTER

-  #endif

-

-  /* Exit low optimization region - place directly after end of function definition */

-  #define LOW_OPTIMIZATION_EXIT

-

-  /* Enter low optimization region - place directly above function definition */

-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)

-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \

-       _Pragma ("optimize=low")

-  #else

-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-  #endif

-

-  /* Exit low optimization region - place directly after end of function definition */

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__CSMC__)

-  #define LOW_OPTIMIZATION_ENTER

-  #define LOW_OPTIMIZATION_EXIT

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#elif defined(__TASKING__)

-  #define LOW_OPTIMIZATION_ENTER

-  #define LOW_OPTIMIZATION_EXIT

-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER

-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT

-

-#endif

-

-

-#ifdef   __cplusplus

-}

-#endif

-

-

-#if defined ( __GNUC__ )

-#pragma GCC diagnostic pop

-#endif

-

-#endif /* _ARM_MATH_H */

-

-/**

- *

- * End of file.

- */

diff --git a/os/common/ext/CMSIS/include/cmsis_gcc.h b/os/common/ext/CMSIS/include/cmsis_gcc.h
deleted file mode 100644
index d868f2e64..000000000
--- a/os/common/ext/CMSIS/include/cmsis_gcc.h
+++ /dev/null
@@ -1,1373 +0,0 @@
-/**************************************************************************//**

- * @file     cmsis_gcc.h

- * @brief    CMSIS Cortex-M Core Function/Instruction Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#ifndef __CMSIS_GCC_H

-#define __CMSIS_GCC_H

-

-/* ignore some GCC warnings */

-#if defined ( __GNUC__ )

-#pragma GCC diagnostic push

-#pragma GCC diagnostic ignored "-Wsign-conversion"

-#pragma GCC diagnostic ignored "-Wconversion"

-#pragma GCC diagnostic ignored "-Wunused-parameter"

-#endif

-

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

- */

-

-/**

-  \brief   Enable IRQ Interrupts

-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)

-{

-  __ASM volatile ("cpsie i" : : : "memory");

-}

-

-

-/**

-  \brief   Disable IRQ Interrupts

-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

-  Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)

-{

-  __ASM volatile ("cpsid i" : : : "memory");

-}

-

-

-/**

-  \brief   Get Control Register

-  \details Returns the content of the Control Register.

-  \return               Control Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, control" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Control Register

-  \details Writes the given value to the Control Register.

-  \param [in]    control  Control Register value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)

-{

-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

-}

-

-

-/**

-  \brief   Get IPSR Register

-  \details Returns the content of the IPSR Register.

-  \return               IPSR Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get APSR Register

-  \details Returns the content of the APSR Register.

-  \return               APSR Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get xPSR Register

-  \details Returns the content of the xPSR Register.

-

-    \return               xPSR Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Get Process Stack Pointer

-  \details Returns the current value of the Process Stack Pointer (PSP).

-  \return               PSP Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Process Stack Pointer

-  \details Assigns the given value to the Process Stack Pointer (PSP).

-  \param [in]    topOfProcStack  Process Stack Pointer value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

-{

-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");

-}

-

-

-/**

-  \brief   Get Main Stack Pointer

-  \details Returns the current value of the Main Stack Pointer (MSP).

-  \return               MSP Register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)

-{

-  register uint32_t result;

-

-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Main Stack Pointer

-  \details Assigns the given value to the Main Stack Pointer (MSP).

-

-    \param [in]    topOfMainStack  Main Stack Pointer value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

-{

-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");

-}

-

-

-/**

-  \brief   Get Priority Mask

-  \details Returns the current state of the priority mask bit from the Priority Mask Register.

-  \return               Priority Mask value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, primask" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Priority Mask

-  \details Assigns the given value to the Priority Mask Register.

-  \param [in]    priMask  Priority Mask

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

-{

-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

-}

-

-

-#if       (__CORTEX_M >= 0x03U)

-

-/**

-  \brief   Enable FIQ

-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)

-{

-  __ASM volatile ("cpsie f" : : : "memory");

-}

-

-

-/**

-  \brief   Disable FIQ

-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

-           Can only be executed in Privileged modes.

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)

-{

-  __ASM volatile ("cpsid f" : : : "memory");

-}

-

-

-/**

-  \brief   Get Base Priority

-  \details Returns the current value of the Base Priority register.

-  \return               Base Priority register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Base Priority

-  \details Assigns the given value to the Base Priority register.

-  \param [in]    basePri  Base Priority value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)

-{

-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");

-}

-

-

-/**

-  \brief   Set Base Priority with condition

-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,

-           or the new value increases the BASEPRI priority level.

-  \param [in]    basePri  Base Priority value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)

-{

-  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");

-}

-

-

-/**

-  \brief   Get Fault Mask

-  \details Returns the current value of the Fault Mask register.

-  \return               Fault Mask register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)

-{

-  uint32_t result;

-

-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

-  return(result);

-}

-

-

-/**

-  \brief   Set Fault Mask

-  \details Assigns the given value to the Fault Mask register.

-  \param [in]    faultMask  Fault Mask value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

-{

-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

-}

-

-#endif /* (__CORTEX_M >= 0x03U) */

-

-

-#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)

-

-/**

-  \brief   Get FPSCR

-  \details Returns the current value of the Floating Point Status/Control register.

-  \return               Floating Point Status/Control register value

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  uint32_t result;

-

-  /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("");

-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

-  __ASM volatile ("");

-  return(result);

-#else

-   return(0);

-#endif

-}

-

-

-/**

-  \brief   Set FPSCR

-  \details Assigns the given value to the Floating Point Status/Control register.

-  \param [in]    fpscr  Floating Point Status/Control value to set

- */

-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

-{

-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)

-  /* Empty asm statement works as a scheduling barrier */

-  __ASM volatile ("");

-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");

-  __ASM volatile ("");

-#endif

-}

-

-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */

-

-

-

-/*@} end of CMSIS_Core_RegAccFunctions */

-

-

-/* ##########################  Core Instruction Access  ######################### */

-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

-  Access to dedicated instructions

-  @{

-*/

-

-/* Define macros for porting to both thumb1 and thumb2.

- * For thumb1, use low register (r0-r7), specified by constraint "l"

- * Otherwise, use general registers, specified by constraint "r" */

-#if defined (__thumb__) && !defined (__thumb2__)

-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)

-#define __CMSIS_GCC_USE_REG(r) "l" (r)

-#else

-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)

-#define __CMSIS_GCC_USE_REG(r) "r" (r)

-#endif

-

-/**

-  \brief   No Operation

-  \details No Operation does nothing. This instruction can be used for code alignment purposes.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)

-{

-  __ASM volatile ("nop");

-}

-

-

-/**

-  \brief   Wait For Interrupt

-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)

-{

-  __ASM volatile ("wfi");

-}

-

-

-/**

-  \brief   Wait For Event

-  \details Wait For Event is a hint instruction that permits the processor to enter

-    a low-power state until one of a number of events occurs.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)

-{

-  __ASM volatile ("wfe");

-}

-

-

-/**

-  \brief   Send Event

-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)

-{

-  __ASM volatile ("sev");

-}

-

-

-/**

-  \brief   Instruction Synchronization Barrier

-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,

-           so that all instructions following the ISB are fetched from cache or memory,

-           after the instruction has been completed.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)

-{

-  __ASM volatile ("isb 0xF":::"memory");

-}

-

-

-/**

-  \brief   Data Synchronization Barrier

-  \details Acts as a special kind of Data Memory Barrier.

-           It completes when all explicit memory accesses before this instruction complete.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)

-{

-  __ASM volatile ("dsb 0xF":::"memory");

-}

-

-

-/**

-  \brief   Data Memory Barrier

-  \details Ensures the apparent order of the explicit memory operations before

-           and after the instruction, without ensuring their completion.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)

-{

-  __ASM volatile ("dmb 0xF":::"memory");

-}

-

-

-/**

-  \brief   Reverse byte order (32 bit)

-  \details Reverses the byte order in integer value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)

-{

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)

-  return __builtin_bswap32(value);

-#else

-  uint32_t result;

-

-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-#endif

-}

-

-

-/**

-  \brief   Reverse byte order (16 bit)

-  \details Reverses the byte order in two unsigned short values.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-

-

-/**

-  \brief   Reverse byte order in signed short value

-  \details Reverses the byte order in a signed short value with sign extension to integer.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)

-{

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-  return (short)__builtin_bswap16(value);

-#else

-  int32_t result;

-

-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-#endif

-}

-

-

-/**

-  \brief   Rotate Right in unsigned value (32 bit)

-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

-  \param [in]    value  Value to rotate

-  \param [in]    value  Number of Bits to rotate

-  \return               Rotated value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

-{

-  return (op1 >> op2) | (op1 << (32U - op2));

-}

-

-

-/**

-  \brief   Breakpoint

-  \details Causes the processor to enter Debug state.

-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.

-  \param [in]    value  is ignored by the processor.

-                 If required, a debugger can use it to store additional information about the breakpoint.

- */

-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)

-

-

-/**

-  \brief   Reverse bit order of value

-  \details Reverses the bit order of the given value.

-  \param [in]    value  Value to reverse

-  \return               Reversed value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

-{

-  uint32_t result;

-

-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

-#else

-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */

-

-  result = value;                      /* r will be reversed bits of v; first get LSB of v */

-  for (value >>= 1U; value; value >>= 1U)

-  {

-    result <<= 1U;

-    result |= value & 1U;

-    s--;

-  }

-  result <<= s;                        /* shift when v's highest bits are zero */

-#endif

-  return(result);

-}

-

-

-/**

-  \brief   Count leading zeros

-  \details Counts the number of leading zeros of a data value.

-  \param [in]  value  Value to count the leading zeros

-  \return             number of leading zeros in value

- */

-#define __CLZ             __builtin_clz

-

-

-#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

-

-/**

-  \brief   LDR Exclusive (8 bit)

-  \details Executes a exclusive LDR instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint8_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDR Exclusive (16 bit)

-  \details Executes a exclusive LDR instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint16_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDR Exclusive (32 bit)

-  \details Executes a exclusive LDR instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );

-   return(result);

-}

-

-

-/**

-  \brief   STR Exclusive (8 bit)

-  \details Executes a exclusive STR instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

-{

-   uint32_t result;

-

-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

-   return(result);

-}

-

-

-/**

-  \brief   STR Exclusive (16 bit)

-  \details Executes a exclusive STR instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

-{

-   uint32_t result;

-

-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

-   return(result);

-}

-

-

-/**

-  \brief   STR Exclusive (32 bit)

-  \details Executes a exclusive STR instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

-  \return          0  Function succeeded

-  \return          1  Function failed

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

-{

-   uint32_t result;

-

-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

-   return(result);

-}

-

-

-/**

-  \brief   Remove the exclusive lock

-  \details Removes the exclusive lock which is created by LDREX.

- */

-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)

-{

-  __ASM volatile ("clrex" ::: "memory");

-}

-

-

-/**

-  \brief   Signed Saturate

-  \details Saturates a signed value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (1..32)

-  \return             Saturated value

- */

-#define __SSAT(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-

-/**

-  \brief   Unsigned Saturate

-  \details Saturates an unsigned value.

-  \param [in]  value  Value to be saturated

-  \param [in]    sat  Bit position to saturate to (0..31)

-  \return             Saturated value

- */

-#define __USAT(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-

-/**

-  \brief   Rotate Right with Extend (32 bit)

-  \details Moves each bit of a bitstring right by one bit.

-           The carry input is shifted in at the left end of the bitstring.

-  \param [in]    value  Value to rotate

-  \return               Rotated value

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)

-{

-  uint32_t result;

-

-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

-  return(result);

-}

-

-

-/**

-  \brief   LDRT Unprivileged (8 bit)

-  \details Executes a Unprivileged LDRT instruction for 8 bit value.

-  \param [in]    ptr  Pointer to data

-  \return             value of type uint8_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint8_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDRT Unprivileged (16 bit)

-  \details Executes a Unprivileged LDRT instruction for 16 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint16_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)

-{

-    uint32_t result;

-

-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );

-#else

-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

-       accepted by assembler. So has to use following less efficient pattern.

-    */

-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

-#endif

-   return ((uint16_t) result);    /* Add explicit type cast here */

-}

-

-

-/**

-  \brief   LDRT Unprivileged (32 bit)

-  \details Executes a Unprivileged LDRT instruction for 32 bit values.

-  \param [in]    ptr  Pointer to data

-  \return        value of type uint32_t at (*ptr)

- */

-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)

-{

-    uint32_t result;

-

-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );

-   return(result);

-}

-

-

-/**

-  \brief   STRT Unprivileged (8 bit)

-  \details Executes a Unprivileged STRT instruction for 8 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)

-{

-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   STRT Unprivileged (16 bit)

-  \details Executes a Unprivileged STRT instruction for 16 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)

-{

-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

-}

-

-

-/**

-  \brief   STRT Unprivileged (32 bit)

-  \details Executes a Unprivileged STRT instruction for 32 bit values.

-  \param [in]  value  Value to store

-  \param [in]    ptr  Pointer to location

- */

-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)

-{

-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );

-}

-

-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */

-

-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

-

-

-/* ###################  Compiler specific Intrinsics  ########################### */

-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

-  Access to dedicated SIMD instructions

-  @{

-*/

-

-#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-#define __SSAT16(ARG1,ARG2) \

-({                          \

-  int32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-#define __USAT16(ARG1,ARG2) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1); \

-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

-  __RES; \

- })

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)

-{

-  uint32_t result;

-

-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)

-{

-  uint32_t result;

-

-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

-{

-  uint32_t result;

-

-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)

-{

-  union llreg_u{

-    uint32_t w32[2];

-    uint64_t w64;

-  } llr;

-  llr.w64 = acc;

-

-#ifndef __ARMEB__   /* Little endian */

-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

-#else               /* Big endian */

-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

-#endif

-

-  return(llr.w64);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

-{

-  uint32_t result;

-

-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)

-{

-  int32_t result;

-

-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)

-{

-  int32_t result;

-

-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

-  return(result);

-}

-

-#define __PKHBT(ARG1,ARG2,ARG3) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

-  __RES; \

- })

-

-#define __PKHTB(ARG1,ARG2,ARG3) \

-({                          \

-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

-  if (ARG3 == 0) \

-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

-  else \

-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

-  __RES; \

- })

-

-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

-{

- int32_t result;

-

- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

- return(result);

-}

-

-#endif /* (__CORTEX_M >= 0x04) */

-/*@} end of group CMSIS_SIMD_intrinsics */

-

-

-#if defined ( __GNUC__ )

-#pragma GCC diagnostic pop

-#endif

-

-#endif /* __CMSIS_GCC_H */

diff --git a/os/common/ext/CMSIS/include/core_cmFunc.h b/os/common/ext/CMSIS/include/core_cmFunc.h
deleted file mode 100644
index ca319a55c..000000000
--- a/os/common/ext/CMSIS/include/core_cmFunc.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**************************************************************************//**

- * @file     core_cmFunc.h

- * @brief    CMSIS Cortex-M Core Function Access Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CMFUNC_H

-#define __CORE_CMFUNC_H

-

-

-/* ###########################  Core Function Access  ########################### */

-/** \ingroup  CMSIS_Core_FunctionInterface

-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

-  @{

-*/

-

-/*------------------ RealView Compiler -----------------*/

-#if   defined ( __CC_ARM )

-  #include "cmsis_armcc.h"

-

-/*------------------ ARM Compiler V6 -------------------*/

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #include "cmsis_armcc_V6.h"

-

-/*------------------ GNU Compiler ----------------------*/

-#elif defined ( __GNUC__ )

-  #include "cmsis_gcc.h"

-

-/*------------------ ICC Compiler ----------------------*/

-#elif defined ( __ICCARM__ )

-  #include <cmsis_iar.h>

-

-/*------------------ TI CCS Compiler -------------------*/

-#elif defined ( __TMS470__ )

-  #include <cmsis_ccs.h>

-

-/*------------------ TASKING Compiler ------------------*/

-#elif defined ( __TASKING__ )

-  /*

-   * The CMSIS functions have been implemented as intrinsics in the compiler.

-   * Please use "carm -?i" to get an up to date list of all intrinsics,

-   * Including the CMSIS ones.

-   */

-

-/*------------------ COSMIC Compiler -------------------*/

-#elif defined ( __CSMC__ )

-  #include <cmsis_csm.h>

-

-#endif

-

-/*@} end of CMSIS_Core_RegAccFunctions */

-

-#endif /* __CORE_CMFUNC_H */

diff --git a/os/common/ext/CMSIS/include/core_cmInstr.h b/os/common/ext/CMSIS/include/core_cmInstr.h
deleted file mode 100644
index 389084a31..000000000
--- a/os/common/ext/CMSIS/include/core_cmInstr.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/**************************************************************************//**

- * @file     core_cmInstr.h

- * @brief    CMSIS Cortex-M Core Instruction Access Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CMINSTR_H

-#define __CORE_CMINSTR_H

-

-

-/* ##########################  Core Instruction Access  ######################### */

-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

-  Access to dedicated instructions

-  @{

-*/

-

-/* CHIBIOS FIX */

-#if !defined(__CORTEX_SC)

-#define __CORTEX_SC 0

-#endif

-

-/*------------------ RealView Compiler -----------------*/

-#if   defined ( __CC_ARM )

-  #include "cmsis_armcc.h"

-

-/*------------------ ARM Compiler V6 -------------------*/

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #include "cmsis_armcc_V6.h"

-

-/*------------------ GNU Compiler ----------------------*/

-#elif defined ( __GNUC__ )

-  #include "cmsis_gcc.h"

-

-/*------------------ ICC Compiler ----------------------*/

-#elif defined ( __ICCARM__ )

-  #include <cmsis_iar.h>

-

-/*------------------ TI CCS Compiler -------------------*/

-#elif defined ( __TMS470__ )

-  #include <cmsis_ccs.h>

-

-/*------------------ TASKING Compiler ------------------*/

-#elif defined ( __TASKING__ )

-  /*

-   * The CMSIS functions have been implemented as intrinsics in the compiler.

-   * Please use "carm -?i" to get an up to date list of all intrinsics,

-   * Including the CMSIS ones.

-   */

-

-/*------------------ COSMIC Compiler -------------------*/

-#elif defined ( __CSMC__ )

-  #include <cmsis_csm.h>

-

-#endif

-

-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

-

-#endif /* __CORE_CMINSTR_H */

diff --git a/os/common/ext/CMSIS/include/core_cmSimd.h b/os/common/ext/CMSIS/include/core_cmSimd.h
deleted file mode 100644
index 4d76bf901..000000000
--- a/os/common/ext/CMSIS/include/core_cmSimd.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/**************************************************************************//**

- * @file     core_cmSimd.h

- * @brief    CMSIS Cortex-M SIMD Header File

- * @version  V4.30

- * @date     20. October 2015

- ******************************************************************************/

-/* Copyright (c) 2009 - 2015 ARM LIMITED

-

-   All rights reserved.

-   Redistribution and use in source and binary forms, with or without

-   modification, are permitted provided that the following conditions are met:

-   - Redistributions of source code must retain the above copyright

-     notice, this list of conditions and the following disclaimer.

-   - Redistributions in binary form must reproduce the above copyright

-     notice, this list of conditions and the following disclaimer in the

-     documentation and/or other materials provided with the distribution.

-   - Neither the name of ARM nor the names of its contributors may be used

-     to endorse or promote products derived from this software without

-     specific prior written permission.

-   *

-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-   POSSIBILITY OF SUCH DAMAGE.

-   ---------------------------------------------------------------------------*/

-

-

-#if   defined ( __ICCARM__ )

- #pragma system_include         /* treat file as system include file for MISRA check */

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #pragma clang system_header   /* treat file as system include file */

-#endif

-

-#ifndef __CORE_CMSIMD_H

-#define __CORE_CMSIMD_H

-

-#ifdef __cplusplus

- extern "C" {

-#endif

-

-

-/* ###################  Compiler specific Intrinsics  ########################### */

-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

-  Access to dedicated SIMD instructions

-  @{

-*/

-

-/*------------------ RealView Compiler -----------------*/

-#if   defined ( __CC_ARM )

-  #include "cmsis_armcc.h"

-

-/*------------------ ARM Compiler V6 -------------------*/

-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)

-  #include "cmsis_armcc_V6.h"

-

-/*------------------ GNU Compiler ----------------------*/

-#elif defined ( __GNUC__ )

-  #include "cmsis_gcc.h"

-

-/*------------------ ICC Compiler ----------------------*/

-#elif defined ( __ICCARM__ )

-  #include <cmsis_iar.h>

-

-/*------------------ TI CCS Compiler -------------------*/

-#elif defined ( __TMS470__ )

-  #include <cmsis_ccs.h>

-

-/*------------------ TASKING Compiler ------------------*/

-#elif defined ( __TASKING__ )

-  /*

-   * The CMSIS functions have been implemented as intrinsics in the compiler.

-   * Please use "carm -?i" to get an up to date list of all intrinsics,

-   * Including the CMSIS ones.

-   */

-

-/*------------------ COSMIC Compiler -------------------*/

-#elif defined ( __CSMC__ )

-  #include <cmsis_csm.h>

-

-#endif

-

-/*@} end of group CMSIS_SIMD_intrinsics */

-

-

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* __CORE_CMSIMD_H */

diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f030x6.h b/os/common/ext/ST/STM32F0xx/stm32f030x6.h
index 369506e3a..369506e3a 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f030x6.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f030x6.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f030x8.h b/os/common/ext/ST/STM32F0xx/stm32f030x8.h
index 6ab2fb481..6ab2fb481 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f030x8.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f030x8.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f030xc.h b/os/common/ext/ST/STM32F0xx/stm32f030xc.h
index 44e1c7e46..44e1c7e46 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f030xc.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f030xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f031x6.h b/os/common/ext/ST/STM32F0xx/stm32f031x6.h
index e3eaa173d..e3eaa173d 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f031x6.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f031x6.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f038xx.h b/os/common/ext/ST/STM32F0xx/stm32f038xx.h
index 14bc9df74..14bc9df74 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f038xx.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f038xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f042x6.h b/os/common/ext/ST/STM32F0xx/stm32f042x6.h
index c8d2c79e1..c8d2c79e1 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f042x6.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f042x6.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f048xx.h b/os/common/ext/ST/STM32F0xx/stm32f048xx.h
index c90656e0b..c90656e0b 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f048xx.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f048xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f051x8.h b/os/common/ext/ST/STM32F0xx/stm32f051x8.h
index fae1731cc..fae1731cc 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f051x8.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f051x8.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f058xx.h b/os/common/ext/ST/STM32F0xx/stm32f058xx.h
index 2101afbe2..2101afbe2 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f058xx.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f058xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f070x6.h b/os/common/ext/ST/STM32F0xx/stm32f070x6.h
index 7692d2526..7692d2526 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f070x6.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f070x6.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f070xb.h b/os/common/ext/ST/STM32F0xx/stm32f070xb.h
index 96dcef47e..96dcef47e 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f070xb.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f070xb.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h b/os/common/ext/ST/STM32F0xx/stm32f071xb.h
index cc3af34ef..cc3af34ef 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f071xb.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f071xb.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f072xb.h b/os/common/ext/ST/STM32F0xx/stm32f072xb.h
index 4be4926de..4be4926de 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f072xb.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f072xb.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f078xx.h b/os/common/ext/ST/STM32F0xx/stm32f078xx.h
index af79cfc04..af79cfc04 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f078xx.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f078xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f091xc.h b/os/common/ext/ST/STM32F0xx/stm32f091xc.h
index 4f2ae78b1..4f2ae78b1 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f091xc.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f091xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f098xx.h b/os/common/ext/ST/STM32F0xx/stm32f098xx.h
index 247ad3154..247ad3154 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f098xx.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f098xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f0xx.h b/os/common/ext/ST/STM32F0xx/stm32f0xx.h
index e432a4bc8..e432a4bc8 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/stm32f0xx.h
+++ b/os/common/ext/ST/STM32F0xx/stm32f0xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F0xx/system_stm32f0xx.h b/os/common/ext/ST/STM32F0xx/system_stm32f0xx.h
index 4daf83e49..4daf83e49 100644
--- a/os/common/ext/CMSIS/ST/STM32F0xx/system_stm32f0xx.h
+++ b/os/common/ext/ST/STM32F0xx/system_stm32f0xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f100xb.h b/os/common/ext/ST/STM32F1xx/stm32f100xb.h
index dd0027bd1..495a1644a 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f100xb.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f100xb.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f100xb.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -141,7 +141,6 @@ typedef enum
   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -555,73 +554,73 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0801FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)

-#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)

-#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-

-

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define CEC_BASE              (APB1PERIPH_BASE + 0x00007800U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+#define TIM15_BASE            (APB2PERIPH_BASE + 0x00004000U)

+#define TIM16_BASE            (APB2PERIPH_BASE + 0x00004400U)

+#define TIM17_BASE            (APB2PERIPH_BASE + 0x00004800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+

+

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 

@@ -633,52 +632,53 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define CEC                 ((CEC_TypeDef *) CEC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define CEC                 ((CEC_TypeDef *)CEC_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define TIM15               ((TIM_TypeDef *)TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *)TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *)TIM17_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -749,14 +749,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -921,9 +931,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -932,9 +942,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -945,15 +955,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -963,11 +973,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -977,11 +987,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -990,10 +1000,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1012,10 +1022,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_PREDIV1            ((uint32_t)0x00000000)            /*!< PREDIV1 clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       ((uint32_t)0x00020000)            /*!< PREDIV1 clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1            0x00000000U                       /*!< PREDIV1 clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       0x00020000U                       /*!< PREDIV1 clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1067,22 +1077,22 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                       /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                       /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                       /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                       /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                       /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

- #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

- #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0

- #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1

- #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2

- #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK

- #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK

- #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI

- #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE

- #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLLCLK_DIV2

+ #define RCC_CFGR_MCOSEL                     RCC_CFGR_MCO

+ #define RCC_CFGR_MCOSEL_0                   RCC_CFGR_MCO_0

+ #define RCC_CFGR_MCOSEL_1                   RCC_CFGR_MCO_1

+ #define RCC_CFGR_MCOSEL_2                   RCC_CFGR_MCO_2

+ #define RCC_CFGR_MCOSEL_NOCLOCK             RCC_CFGR_MCO_NOCLOCK

+ #define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCO_SYSCLK

+ #define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCO_HSI

+ #define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCO_HSE

+ #define RCC_CFGR_MCOSEL_PLL_DIV2            RCC_CFGR_MCO_PLLCLK_DIV2

 

 /*!<******************  Bit definition for RCC_CIR register  ********************/

 #define RCC_CIR_LSIRDYF_Pos                  (0U)                              

@@ -1381,10 +1391,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1433,7 +1443,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV1_2                  (0x4U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000004 */

 #define RCC_CFGR2_PREDIV1_3                  (0x8U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000008 */

 

-#define RCC_CFGR2_PREDIV1_DIV1               ((uint32_t)0x00000000)            /*!< PREDIV1 input clock not divided */

+#define RCC_CFGR2_PREDIV1_DIV1               0x00000000U                       /*!< PREDIV1 input clock not divided */

 #define RCC_CFGR2_PREDIV1_DIV2_Pos           (0U)                              

 #define RCC_CFGR2_PREDIV1_DIV2_Msk           (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */

 #define RCC_CFGR2_PREDIV1_DIV2               RCC_CFGR2_PREDIV1_DIV2_Msk        /*!< PREDIV1 input clock divided by 2 */

@@ -2010,7 +2020,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2065,7 +2075,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2104,7 +2114,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2119,7 +2129,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2134,7 +2144,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2152,7 +2162,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2177,7 +2187,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2204,7 +2214,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2225,7 +2235,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2246,7 +2256,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2267,7 +2277,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2302,7 +2312,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2323,7 +2333,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2344,7 +2354,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2365,7 +2375,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2400,7 +2410,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2421,7 +2431,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2442,7 +2452,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2463,7 +2473,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2498,7 +2508,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2519,7 +2529,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2540,7 +2550,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2561,7 +2571,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2605,440 +2615,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3098,12 +2674,6 @@ typedef struct
 #define EXTI_IMR_MR17_Pos                   (17U)                              

 #define EXTI_IMR_MR17_Msk                   (0x1U << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */

 #define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */

-#define EXTI_IMR_MR18_Pos                   (18U)                              

-#define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3124,9 +2694,8 @@ typedef struct
 #define  EXTI_IMR_IM15 EXTI_IMR_MR15

 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

-#define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0003FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3182,12 +2751,6 @@ typedef struct
 #define EXTI_EMR_MR17_Pos                   (17U)                              

 #define EXTI_EMR_MR17_Msk                   (0x1U << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */

 #define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */

-#define EXTI_EMR_MR18_Pos                   (18U)                              

-#define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3208,8 +2771,6 @@ typedef struct
 #define  EXTI_EMR_EM15 EXTI_EMR_MR15

 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

-#define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3266,12 +2827,6 @@ typedef struct
 #define EXTI_RTSR_TR17_Pos                  (17U)                              

 #define EXTI_RTSR_TR17_Msk                  (0x1U << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */

 #define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */

-#define EXTI_RTSR_TR18_Pos                  (18U)                              

-#define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3292,8 +2847,6 @@ typedef struct
 #define  EXTI_RTSR_RT15 EXTI_RTSR_TR15

 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3350,12 +2903,6 @@ typedef struct
 #define EXTI_FTSR_TR17_Pos                  (17U)                              

 #define EXTI_FTSR_TR17_Msk                  (0x1U << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */

 #define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */

-#define EXTI_FTSR_TR18_Pos                  (18U)                              

-#define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3376,8 +2923,6 @@ typedef struct
 #define  EXTI_FTSR_FT15 EXTI_FTSR_TR15

 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3434,12 +2979,6 @@ typedef struct
 #define EXTI_SWIER_SWIER17_Pos              (17U)                              

 #define EXTI_SWIER_SWIER17_Msk              (0x1U << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */

 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */

-#define EXTI_SWIER_SWIER18_Pos              (18U)                              

-#define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3460,8 +2999,6 @@ typedef struct
 #define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15

 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3518,12 +3055,6 @@ typedef struct
 #define EXTI_PR_PR17_Pos                    (17U)                              

 #define EXTI_PR_PR17_Msk                    (0x1U << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */

 #define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */

-#define EXTI_PR_PR18_Pos                    (18U)                              

-#define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3544,8 +3075,6 @@ typedef struct
 #define  EXTI_PR_PIF15 EXTI_PR_PR15

 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

-#define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4648,10 +4177,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -4996,9 +4521,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5102,8 +4624,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5845,8 +5365,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -5891,6 +5411,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -6071,6 +5596,9 @@ typedef struct
 #define USART_CR1_UE_Pos                    (13U)                              

 #define USART_CR1_UE_Msk                    (0x1U << USART_CR1_UE_Pos)         /*!< 0x00002000 */

 #define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */

+#define USART_CR1_OVER8_Pos                 (15U)                              

+#define USART_CR1_OVER8_Msk                 (0x1U << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */

+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< USART Oversmapling 8-bits */

 

 /******************  Bit definition for USART_CR2 register  *******************/

 #define USART_CR2_ADD_Pos                   (0U)                               

@@ -6139,6 +5667,9 @@ typedef struct
 #define USART_CR3_CTSIE_Pos                 (10U)                              

 #define USART_CR3_CTSIE_Msk                 (0x1U << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */

 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos                (11U)                              

+#define USART_CR3_ONEBIT_Msk                (0x1U << USART_CR3_ONEBIT_Pos)      /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                /*!< One Bit method */

 

 /******************  Bit definition for USART_GTPR register  ******************/

 #define USART_GTPR_PSC_Pos                  (0U)                               

@@ -6452,7 +5983,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -6480,6 +6011,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -6500,6 +6034,8 @@ typedef struct
    ((INSTANCE) == TIM16)   || \

    ((INSTANCE) == TIM17))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM2)    || \

@@ -6700,6 +6236,18 @@ typedef struct
    ((INSTANCE) == TIM16)   || \

    ((INSTANCE) == TIM17))

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -6757,10 +6305,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        26000000U

+

+#define RCC_MAX_FREQUENCY  24000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -6771,33 +6323,33 @@ typedef struct
 

 /* Aliases for __IRQn */

 #define ADC1_2_IRQn             ADC1_IRQn

-#define USBWakeUp_IRQn          CEC_IRQn

 #define OTG_FS_WKUP_IRQn        CEC_IRQn

-#define TIM1_BRK_IRQn           TIM1_BRK_TIM15_IRQn

-#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_TIM15_IRQn

+#define USBWakeUp_IRQn          CEC_IRQn

 #define TIM9_IRQn               TIM1_BRK_TIM15_IRQn

-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn

+#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_TIM15_IRQn

+#define TIM1_BRK_IRQn           TIM1_BRK_TIM15_IRQn

 #define TIM1_TRG_COM_IRQn       TIM1_TRG_COM_TIM17_IRQn

+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn

 #define TIM11_IRQn              TIM1_TRG_COM_TIM17_IRQn

-#define TIM1_UP_IRQn            TIM1_UP_TIM16_IRQn

-#define TIM10_IRQn              TIM1_UP_TIM16_IRQn

 #define TIM1_UP_TIM10_IRQn      TIM1_UP_TIM16_IRQn

+#define TIM10_IRQn              TIM1_UP_TIM16_IRQn

+#define TIM1_UP_IRQn            TIM1_UP_TIM16_IRQn

 #define TIM6_IRQn               TIM6_DAC_IRQn

 

 

 /* Aliases for __IRQHandler */

 #define ADC1_2_IRQHandler             ADC1_IRQHandler

-#define USBWakeUp_IRQHandler          CEC_IRQHandler

 #define OTG_FS_WKUP_IRQHandler        CEC_IRQHandler

-#define TIM1_BRK_IRQHandler           TIM1_BRK_TIM15_IRQHandler

-#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_TIM15_IRQHandler

+#define USBWakeUp_IRQHandler          CEC_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_TIM15_IRQHandler

-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_TIM15_IRQHandler

+#define TIM1_BRK_IRQHandler           TIM1_BRK_TIM15_IRQHandler

 #define TIM1_TRG_COM_IRQHandler       TIM1_TRG_COM_TIM17_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler

 #define TIM11_IRQHandler              TIM1_TRG_COM_TIM17_IRQHandler

-#define TIM1_UP_IRQHandler            TIM1_UP_TIM16_IRQHandler

-#define TIM10_IRQHandler              TIM1_UP_TIM16_IRQHandler

 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_TIM16_IRQHandler

+#define TIM10_IRQHandler              TIM1_UP_TIM16_IRQHandler

+#define TIM1_UP_IRQHandler            TIM1_UP_TIM16_IRQHandler

 #define TIM6_IRQHandler               TIM6_DAC_IRQHandler

 

 

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f100xe.h b/os/common/ext/ST/STM32F1xx/stm32f100xe.h
index 68012d3fe..3b87d3a0d 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f100xe.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f100xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f100xe.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -156,7 +156,6 @@ typedef enum
                                              the AFIO_MAPR2 register is set)                      */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -621,99 +620,99 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0807FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

-#define FSMC_BASE             ((uint32_t)0x60000000) /*!< FSMC base address */

-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */

+#define FSMC_BASE             0x60000000U /*!< FSMC base address */

+#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address */

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)

-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)

-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define TIM12_BASE            (APB1PERIPH_BASE + 0x00001800U)

+#define TIM13_BASE            (APB1PERIPH_BASE + 0x00001C00U)

+#define TIM14_BASE            (APB1PERIPH_BASE + 0x00002000U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)

+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)

-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)

-#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)

-#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define CEC_BASE              (APB1PERIPH_BASE + 0x00007800U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x00001C00U)

+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x00002000U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+#define TIM15_BASE            (APB2PERIPH_BASE + 0x00004000U)

+#define TIM16_BASE            (APB2PERIPH_BASE + 0x00004400U)

+#define TIM17_BASE            (APB2PERIPH_BASE + 0x00004800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400U)

+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408U)

+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CU)

+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430U)

+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444U)

+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

 

 

 #define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */

 #define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */

-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */

-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */

-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */

+#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */

+#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */

+#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */

 

 

-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000)    /*!< FSMC Bank1 registers base address */

-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104)    /*!< FSMC Bank1E registers base address */

+#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x00000000U)    /*!< FSMC Bank1 registers base address */

+#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x00000104U)    /*!< FSMC Bank1E registers base address */

 

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 

@@ -725,69 +724,70 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define UART4               ((USART_TypeDef *) UART4_BASE)

-#define UART5               ((USART_TypeDef *) UART5_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define CEC                 ((CEC_TypeDef *) CEC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)

-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *)TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define TIM12               ((TIM_TypeDef *)TIM12_BASE)

+#define TIM13               ((TIM_TypeDef *)TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *)TIM14_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define UART4               ((USART_TypeDef *)UART4_BASE)

+#define UART5               ((USART_TypeDef *)UART5_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define CEC                 ((CEC_TypeDef *)CEC_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *)GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *)GPIOG_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define TIM15               ((TIM_TypeDef *)TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *)TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *)TIM17_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA2                ((DMA_TypeDef *)DMA2_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

+#define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

+#define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

+#define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

+#define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)

+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -858,14 +858,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -1190,9 +1200,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -1201,9 +1211,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1214,15 +1224,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1232,11 +1242,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1246,11 +1256,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1259,10 +1269,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1281,10 +1291,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_PREDIV1            ((uint32_t)0x00000000)            /*!< PREDIV1 clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       ((uint32_t)0x00020000)            /*!< PREDIV1 clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1            0x00000000U                       /*!< PREDIV1 clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       0x00020000U                       /*!< PREDIV1 clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1336,22 +1346,22 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                       /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                       /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                       /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                       /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                       /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

- #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

- #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0

- #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1

- #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2

- #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK

- #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK

- #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI

- #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE

- #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLLCLK_DIV2

+ #define RCC_CFGR_MCOSEL                     RCC_CFGR_MCO

+ #define RCC_CFGR_MCOSEL_0                   RCC_CFGR_MCO_0

+ #define RCC_CFGR_MCOSEL_1                   RCC_CFGR_MCO_1

+ #define RCC_CFGR_MCOSEL_2                   RCC_CFGR_MCO_2

+ #define RCC_CFGR_MCOSEL_NOCLOCK             RCC_CFGR_MCO_NOCLOCK

+ #define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCO_SYSCLK

+ #define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCO_HSI

+ #define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCO_HSE

+ #define RCC_CFGR_MCOSEL_PLL_DIV2            RCC_CFGR_MCO_PLLCLK_DIV2

 

 /*!<******************  Bit definition for RCC_CIR register  ********************/

 #define RCC_CIR_LSIRDYF_Pos                  (0U)                              

@@ -1710,10 +1720,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1762,7 +1772,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV1_2                  (0x4U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000004 */

 #define RCC_CFGR2_PREDIV1_3                  (0x8U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000008 */

 

-#define RCC_CFGR2_PREDIV1_DIV1               ((uint32_t)0x00000000)            /*!< PREDIV1 input clock not divided */

+#define RCC_CFGR2_PREDIV1_DIV1               0x00000000U                       /*!< PREDIV1 input clock not divided */

 #define RCC_CFGR2_PREDIV1_DIV2_Pos           (0U)                              

 #define RCC_CFGR2_PREDIV1_DIV2_Msk           (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */

 #define RCC_CFGR2_PREDIV1_DIV2               RCC_CFGR2_PREDIV1_DIV2_Msk        /*!< PREDIV1 input clock divided by 2 */

@@ -2339,7 +2349,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2394,7 +2404,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2433,7 +2443,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2448,7 +2458,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2463,7 +2473,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2481,7 +2491,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2509,7 +2519,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2536,7 +2546,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2557,7 +2567,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2578,7 +2588,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2599,7 +2609,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2634,7 +2644,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2655,7 +2665,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2676,7 +2686,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2697,7 +2707,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2732,7 +2742,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2753,7 +2763,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2774,7 +2784,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2795,7 +2805,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2830,7 +2840,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2851,7 +2861,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2872,7 +2882,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2893,7 +2903,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2952,440 +2962,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3445,12 +3021,6 @@ typedef struct
 #define EXTI_IMR_MR17_Pos                   (17U)                              

 #define EXTI_IMR_MR17_Msk                   (0x1U << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */

 #define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */

-#define EXTI_IMR_MR18_Pos                   (18U)                              

-#define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

-#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3471,9 +3041,8 @@ typedef struct
 #define  EXTI_IMR_IM15 EXTI_IMR_MR15

 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

-#define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0003FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3529,12 +3098,6 @@ typedef struct
 #define EXTI_EMR_MR17_Pos                   (17U)                              

 #define EXTI_EMR_MR17_Msk                   (0x1U << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */

 #define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */

-#define EXTI_EMR_MR18_Pos                   (18U)                              

-#define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

-#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3555,8 +3118,6 @@ typedef struct
 #define  EXTI_EMR_EM15 EXTI_EMR_MR15

 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

-#define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3613,12 +3174,6 @@ typedef struct
 #define EXTI_RTSR_TR17_Pos                  (17U)                              

 #define EXTI_RTSR_TR17_Msk                  (0x1U << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */

 #define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */

-#define EXTI_RTSR_TR18_Pos                  (18U)                              

-#define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

-#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3639,8 +3194,6 @@ typedef struct
 #define  EXTI_RTSR_RT15 EXTI_RTSR_TR15

 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

-#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3697,12 +3250,6 @@ typedef struct
 #define EXTI_FTSR_TR17_Pos                  (17U)                              

 #define EXTI_FTSR_TR17_Msk                  (0x1U << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */

 #define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */

-#define EXTI_FTSR_TR18_Pos                  (18U)                              

-#define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

-#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3723,8 +3270,6 @@ typedef struct
 #define  EXTI_FTSR_FT15 EXTI_FTSR_TR15

 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

-#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3781,12 +3326,6 @@ typedef struct
 #define EXTI_SWIER_SWIER17_Pos              (17U)                              

 #define EXTI_SWIER_SWIER17_Msk              (0x1U << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */

 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */

-#define EXTI_SWIER_SWIER18_Pos              (18U)                              

-#define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

-#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3807,8 +3346,6 @@ typedef struct
 #define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15

 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

-#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3865,12 +3402,6 @@ typedef struct
 #define EXTI_PR_PR17_Pos                    (17U)                              

 #define EXTI_PR_PR17_Msk                    (0x1U << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */

 #define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */

-#define EXTI_PR_PR18_Pos                    (18U)                              

-#define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

-#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3891,8 +3422,6 @@ typedef struct
 #define  EXTI_PR_PIF15 EXTI_PR_PR15

 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

-#define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4995,10 +4524,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -5343,9 +4868,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5449,8 +4971,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -6359,8 +5879,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -6405,6 +5925,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -6585,6 +6110,9 @@ typedef struct
 #define USART_CR1_UE_Pos                    (13U)                              

 #define USART_CR1_UE_Msk                    (0x1U << USART_CR1_UE_Pos)         /*!< 0x00002000 */

 #define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */

+#define USART_CR1_OVER8_Pos                 (15U)                              

+#define USART_CR1_OVER8_Msk                 (0x1U << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */

+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< USART Oversmapling 8-bits */

 

 /******************  Bit definition for USART_CR2 register  *******************/

 #define USART_CR2_ADD_Pos                   (0U)                               

@@ -6653,6 +6181,9 @@ typedef struct
 #define USART_CR3_CTSIE_Pos                 (10U)                              

 #define USART_CR3_CTSIE_Msk                 (0x1U << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */

 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos                (11U)                              

+#define USART_CR3_ONEBIT_Msk                (0x1U << USART_CR3_ONEBIT_Pos)      /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                /*!< One Bit method */

 

 /******************  Bit definition for USART_GTPR register  ******************/

 #define USART_GTPR_PSC_Pos                  (0U)                               

@@ -6984,7 +6515,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -7019,6 +6550,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -7044,6 +6578,8 @@ typedef struct
    ((INSTANCE) == TIM16)   || \

    ((INSTANCE) == TIM17))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM2)    || \

@@ -7289,6 +6825,20 @@ typedef struct
    ((INSTANCE) == TIM16)   || \

    ((INSTANCE) == TIM17))

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4)    || \

+                                        ((INSTANCE) == TIM5))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4)    || \

+                                                         ((INSTANCE) == TIM5))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -7358,10 +6908,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        26000000U

+

+#define RCC_MAX_FREQUENCY  24000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -7372,45 +6926,45 @@ typedef struct
 

 /* Aliases for __IRQn */

 #define ADC1_2_IRQn             ADC1_IRQn

-#define USBWakeUp_IRQn          CEC_IRQn

 #define OTG_FS_WKUP_IRQn        CEC_IRQn

+#define USBWakeUp_IRQn          CEC_IRQn

 #define TIM8_BRK_TIM12_IRQn     TIM12_IRQn

 #define TIM8_BRK_IRQn           TIM12_IRQn

 #define TIM8_UP_IRQn            TIM13_IRQn

 #define TIM8_UP_TIM13_IRQn      TIM13_IRQn

 #define TIM8_TRG_COM_IRQn       TIM14_IRQn

 #define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn

-#define TIM1_BRK_IRQn           TIM1_BRK_TIM15_IRQn

 #define TIM9_IRQn               TIM1_BRK_TIM15_IRQn

+#define TIM1_BRK_IRQn           TIM1_BRK_TIM15_IRQn

 #define TIM1_BRK_TIM9_IRQn      TIM1_BRK_TIM15_IRQn

-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn

-#define TIM1_TRG_COM_IRQn       TIM1_TRG_COM_TIM17_IRQn

 #define TIM11_IRQn              TIM1_TRG_COM_TIM17_IRQn

-#define TIM10_IRQn              TIM1_UP_TIM16_IRQn

+#define TIM1_TRG_COM_IRQn       TIM1_TRG_COM_TIM17_IRQn

+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn

 #define TIM1_UP_IRQn            TIM1_UP_TIM16_IRQn

 #define TIM1_UP_TIM10_IRQn      TIM1_UP_TIM16_IRQn

+#define TIM10_IRQn              TIM1_UP_TIM16_IRQn

 #define TIM6_IRQn               TIM6_DAC_IRQn

 

 

 /* Aliases for __IRQHandler */

 #define ADC1_2_IRQHandler             ADC1_IRQHandler

-#define USBWakeUp_IRQHandler          CEC_IRQHandler

 #define OTG_FS_WKUP_IRQHandler        CEC_IRQHandler

+#define USBWakeUp_IRQHandler          CEC_IRQHandler

 #define TIM8_BRK_TIM12_IRQHandler     TIM12_IRQHandler

 #define TIM8_BRK_IRQHandler           TIM12_IRQHandler

 #define TIM8_UP_IRQHandler            TIM13_IRQHandler

 #define TIM8_UP_TIM13_IRQHandler      TIM13_IRQHandler

 #define TIM8_TRG_COM_IRQHandler       TIM14_IRQHandler

 #define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler

-#define TIM1_BRK_IRQHandler           TIM1_BRK_TIM15_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_TIM15_IRQHandler

+#define TIM1_BRK_IRQHandler           TIM1_BRK_TIM15_IRQHandler

 #define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_TIM15_IRQHandler

-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler

-#define TIM1_TRG_COM_IRQHandler       TIM1_TRG_COM_TIM17_IRQHandler

 #define TIM11_IRQHandler              TIM1_TRG_COM_TIM17_IRQHandler

-#define TIM10_IRQHandler              TIM1_UP_TIM16_IRQHandler

+#define TIM1_TRG_COM_IRQHandler       TIM1_TRG_COM_TIM17_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler

 #define TIM1_UP_IRQHandler            TIM1_UP_TIM16_IRQHandler

 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_TIM16_IRQHandler

+#define TIM10_IRQHandler              TIM1_UP_TIM16_IRQHandler

 #define TIM6_IRQHandler               TIM6_DAC_IRQHandler

 

 

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101x6.h b/os/common/ext/ST/STM32F1xx/stm32f101x6.h
index 92b413d12..9e279b130 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101x6.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f101x6.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f101x6.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -129,7 +129,6 @@ typedef enum
   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -507,60 +506,60 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x08007FFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-

-

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+

+

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 

@@ -572,39 +571,39 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -675,14 +674,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -847,9 +856,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -858,9 +867,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -871,15 +880,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -889,11 +898,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -903,11 +912,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -916,10 +925,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -938,10 +947,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -993,11 +1002,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1235,10 +1244,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1808,7 +1817,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -1863,7 +1872,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -1903,7 +1912,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -1918,7 +1927,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -1936,7 +1945,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -1958,7 +1967,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -1985,7 +1994,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2006,7 +2015,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2027,7 +2036,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2048,7 +2057,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2083,7 +2092,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2104,7 +2113,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2125,7 +2134,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2146,7 +2155,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2181,7 +2190,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2202,7 +2211,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2223,7 +2232,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2244,7 +2253,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2279,7 +2288,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2300,7 +2309,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2321,7 +2330,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2342,7 +2351,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2368,440 +2377,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -2864,9 +2439,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -2888,8 +2460,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -2948,9 +2520,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -2972,7 +2541,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3032,9 +2600,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3056,7 +2621,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3116,9 +2680,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3140,7 +2701,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3200,9 +2760,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3224,7 +2781,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3284,9 +2840,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3308,7 +2861,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4158,10 +3710,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -4506,9 +4054,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -4612,8 +4157,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5359,8 +4902,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -5405,6 +4948,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -5959,6 +5507,9 @@ typedef struct
 /******************************** I2C Instances *******************************/

 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -5971,6 +5522,8 @@ typedef struct
   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)              0U

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

@@ -6027,7 +5580,7 @@ typedef struct
   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

 

-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)                 0U

 

 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

    ((((INSTANCE) == TIM2) &&                   \

@@ -6042,13 +5595,13 @@ typedef struct
       ((CHANNEL) == TIM_CHANNEL_3) ||          \

       ((CHANNEL) == TIM_CHANNEL_4))))

 

-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)         0U

 

 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

 

-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)    0U

 

 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -6062,7 +5615,15 @@ typedef struct
   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

     

-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)     0U

+

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

 

 /****************************** END TIM Instances *****************************/

 

@@ -6101,7 +5662,7 @@ typedef struct
 

 /***************** UART Instances : DMA mode available **********************/

 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

-                                        ((INSTANCE) == USART2) )

+                                        ((INSTANCE) == USART2))

 

 /****************************** RTC Instances *********************************/

 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

@@ -6112,10 +5673,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101xb.h b/os/common/ext/ST/STM32F1xx/stm32f101xb.h
index 2909876c1..4e0ddf25d 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101xb.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f101xb.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f101xb.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -134,7 +134,6 @@ typedef enum
   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -512,65 +511,65 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0801FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

 

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

 

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

 

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

 

 

 

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 

@@ -582,44 +581,44 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -690,14 +689,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -862,9 +871,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -873,9 +882,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -886,15 +895,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -904,11 +913,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -918,11 +927,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -931,10 +940,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -953,10 +962,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1008,11 +1017,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1280,10 +1289,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1853,7 +1862,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -1908,7 +1917,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -1947,7 +1956,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -1962,7 +1971,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -1977,7 +1986,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -1995,7 +2004,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2020,7 +2029,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2047,7 +2056,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2068,7 +2077,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2089,7 +2098,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2110,7 +2119,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2145,7 +2154,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2166,7 +2175,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2187,7 +2196,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2208,7 +2217,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2243,7 +2252,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2264,7 +2273,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2285,7 +2294,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2306,7 +2315,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2341,7 +2350,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2362,7 +2371,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2383,7 +2392,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2404,7 +2413,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2430,440 +2439,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -2926,9 +2501,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -2950,8 +2522,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3010,9 +2582,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3034,7 +2603,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3094,9 +2662,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3118,7 +2683,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3178,9 +2742,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3202,7 +2763,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3262,9 +2822,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3286,7 +2843,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3346,9 +2902,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3370,7 +2923,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4220,10 +3772,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -4568,9 +4116,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -4674,8 +4219,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5421,8 +4964,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -5467,6 +5010,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -6053,6 +5601,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -6067,6 +5618,8 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)              0U

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3)    || \

@@ -6137,7 +5690,7 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)               0U

 

 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

    ((((INSTANCE) == TIM2) &&                   \

@@ -6158,14 +5711,14 @@ typedef struct
       ((CHANNEL) == TIM_CHANNEL_3) ||          \

       ((CHANNEL) == TIM_CHANNEL_4))))

 

-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)        0U

 

 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)   0U

 

 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -6182,7 +5735,17 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

     

-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)     0U

+

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

 

 /****************************** END TIM Instances *****************************/

 

@@ -6241,10 +5804,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101xe.h b/os/common/ext/ST/STM32F1xx/stm32f101xe.h
index bc0fdee2c..f12817435 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101xe.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f101xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f101xe.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -145,7 +145,6 @@ typedef enum
   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -629,96 +628,96 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0807FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

-#define FSMC_BASE             ((uint32_t)0x60000000) /*!< FSMC base address */

-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */

+#define FSMC_BASE             0x60000000U /*!< FSMC base address */

+#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address */

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)

+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)

-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x00001C00U)

+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x00002000U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400U)

+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408U)

+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CU)

+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430U)

+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444U)

+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

 

 

 #define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */

 #define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */

-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */

-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */

-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */

+#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */

+#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */

+#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */

 

-#define FSMC_BANK2            (FSMC_BASE + 0x10000000)  /*!< FSMC Bank2 base address */

-#define FSMC_BANK3            (FSMC_BASE + 0x20000000)  /*!< FSMC Bank3 base address */

-#define FSMC_BANK4            (FSMC_BASE + 0x30000000)  /*!< FSMC Bank4 base address */

+#define FSMC_BANK2            (FSMC_BASE + 0x10000000U)  /*!< FSMC Bank2 base address */

+#define FSMC_BANK3            (FSMC_BASE + 0x20000000U)  /*!< FSMC Bank3 base address */

+#define FSMC_BANK4            (FSMC_BASE + 0x30000000U)  /*!< FSMC Bank4 base address */

 

-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000)    /*!< FSMC Bank1 registers base address */

-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104)    /*!< FSMC Bank1E registers base address */

-#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x0060)    /*!< FSMC Bank2/Bank3 registers base address */

-#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x00A0)    /*!< FSMC Bank4 registers base address */

+#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x00000000U)    /*!< FSMC Bank1 registers base address */

+#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x00000104U)    /*!< FSMC Bank1E registers base address */

+#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x00000060U)    /*!< FSMC Bank2/Bank3 registers base address */

+#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x000000A0U)    /*!< FSMC Bank4 registers base address */

 

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 

@@ -730,63 +729,64 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define UART4               ((USART_TypeDef *) UART4_BASE)

-#define UART5               ((USART_TypeDef *) UART5_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)

-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)

-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)

-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *)TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define UART4               ((USART_TypeDef *)UART4_BASE)

+#define UART5               ((USART_TypeDef *)UART5_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *)GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *)GPIOG_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA2                ((DMA_TypeDef *)DMA2_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

+#define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

+#define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

+#define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

+#define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)

+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)

+#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)

+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -857,14 +857,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -1189,9 +1199,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -1200,9 +1210,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1213,15 +1223,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1231,11 +1241,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1245,11 +1255,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1258,10 +1268,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1280,10 +1290,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1335,11 +1345,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1667,10 +1677,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -2240,7 +2250,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2295,7 +2305,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2334,7 +2344,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2349,7 +2359,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2364,7 +2374,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2382,7 +2392,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2410,7 +2420,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2437,7 +2447,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2458,7 +2468,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2479,7 +2489,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2500,7 +2510,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2535,7 +2545,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2556,7 +2566,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2577,7 +2587,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2598,7 +2608,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2633,7 +2643,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2654,7 +2664,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2675,7 +2685,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2696,7 +2706,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2731,7 +2741,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2752,7 +2762,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2773,7 +2783,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2794,7 +2804,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2823,440 +2833,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3319,9 +2895,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3343,8 +2916,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3403,9 +2976,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3427,7 +2997,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3487,9 +3056,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3511,7 +3077,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3571,9 +3136,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3595,7 +3157,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3655,9 +3216,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3679,7 +3237,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3739,9 +3296,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3763,7 +3317,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4762,10 +4315,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -5110,9 +4659,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5216,8 +4762,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5640,14 +5184,14 @@ typedef struct
 #define FSMC_PMEMx_MEMWAITx_Pos             (8U)                               

 #define FSMC_PMEMx_MEMWAITx_Msk             (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */

 #define FSMC_PMEMx_MEMWAITx                 FSMC_PMEMx_MEMWAITx_Msk            /*!< MEMWAITx[7:0] bits (Common memory x wait time) */

-#define FSMC_PMEMx_MEMWAIT2_0               ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define FSMC_PMEMx_MEMWAITx_1               ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define FSMC_PMEMx_MEMWAITx_2               ((uint32_t)0x00000400)             /*!< Bit 2 */

-#define FSMC_PMEMx_MEMWAITx_3               ((uint32_t)0x00000800)             /*!< Bit 3 */

-#define FSMC_PMEMx_MEMWAITx_4               ((uint32_t)0x00001000)             /*!< Bit 4 */

-#define FSMC_PMEMx_MEMWAITx_5               ((uint32_t)0x00002000)             /*!< Bit 5 */

-#define FSMC_PMEMx_MEMWAITx_6               ((uint32_t)0x00004000)             /*!< Bit 6 */

-#define FSMC_PMEMx_MEMWAITx_7               ((uint32_t)0x00008000)             /*!< Bit 7 */

+#define FSMC_PMEMx_MEMWAIT2_0               0x00000100U                        /*!< Bit 0 */

+#define FSMC_PMEMx_MEMWAITx_1               0x00000200U                        /*!< Bit 1 */

+#define FSMC_PMEMx_MEMWAITx_2               0x00000400U                        /*!< Bit 2 */

+#define FSMC_PMEMx_MEMWAITx_3               0x00000800U                        /*!< Bit 3 */

+#define FSMC_PMEMx_MEMWAITx_4               0x00001000U                        /*!< Bit 4 */

+#define FSMC_PMEMx_MEMWAITx_5               0x00002000U                        /*!< Bit 5 */

+#define FSMC_PMEMx_MEMWAITx_6               0x00004000U                        /*!< Bit 6 */

+#define FSMC_PMEMx_MEMWAITx_7               0x00008000U                        /*!< Bit 7 */

 

 #define FSMC_PMEMx_MEMHOLDx_Pos             (16U)                              

 #define FSMC_PMEMx_MEMHOLDx_Msk             (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */

@@ -6345,8 +5889,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -6391,6 +5935,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -6971,7 +6520,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -7006,6 +6555,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -7024,6 +6576,8 @@ typedef struct
    ((INSTANCE) == TIM6)    || \

    ((INSTANCE) == TIM7))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)              0U

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3)    || \

@@ -7110,7 +6664,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \

    ((INSTANCE) == TIM5))

 

-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)               0U

 

 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

    ((((INSTANCE) == TIM2) &&                   \

@@ -7137,7 +6691,7 @@ typedef struct
       ((CHANNEL) == TIM_CHANNEL_3) ||          \

       ((CHANNEL) == TIM_CHANNEL_4))))

 

-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)       0U

  

 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -7145,7 +6699,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \

    ((INSTANCE) == TIM5))

 

-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)    0U

 

 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -7167,7 +6721,19 @@ typedef struct
    ((INSTANCE) == TIM4)    || \

    ((INSTANCE) == TIM5))

     

-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)     0U

+

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4)    || \

+                                        ((INSTANCE) == TIM5))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4)    || \

+                                                         ((INSTANCE) == TIM5))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

 

 /****************************** END TIM Instances *****************************/

 

@@ -7237,10 +6803,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101xg.h b/os/common/ext/ST/STM32F1xx/stm32f101xg.h
index 768a00256..d434eb0da 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f101xg.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f101xg.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f101xg.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             1      /*!< STM32 XL-density devices provide an MPU      */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             1U       /*!< STM32 XL-density devices provide an MPU      */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -116,7 +116,7 @@ typedef enum
   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */

   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */

   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */

-  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */

+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */

   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */

   TIM9_IRQn                   = 24,     /*!< TIM9 global Interrupt                                */

   TIM10_IRQn                  = 25,     /*!< TIM10 global Interrupt                               */

@@ -151,7 +151,6 @@ typedef enum
   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -641,104 +640,103 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */

-#define FLASH_BANK2_END       ((uint32_t)0x080FFFFF) /*!< FLASH END address of bank2 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0807FFFFU /*!< FLASH END address of bank1 */

+#define FLASH_BANK2_END       0x080FFFFFU /*!< FLASH END address of bank2 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

-#define FSMC_BASE             ((uint32_t)0x60000000) /*!< FSMC base address */

-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */

+#define FSMC_BASE             0x60000000U /*!< FSMC base address */

+#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address */

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)

-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)

-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define TIM12_BASE            (APB1PERIPH_BASE + 0x00001800U)

+#define TIM13_BASE            (APB1PERIPH_BASE + 0x00001C00U)

+#define TIM14_BASE            (APB1PERIPH_BASE + 0x00002000U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)

+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)

-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)

-#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)

-#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x00001C00U)

+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x00002000U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+#define TIM9_BASE             (APB2PERIPH_BASE + 0x00004C00U)

+#define TIM10_BASE            (APB2PERIPH_BASE + 0x00005000U)

+#define TIM11_BASE            (APB2PERIPH_BASE + 0x00005400U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400U)

+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408U)

+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CU)

+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430U)

+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444U)

+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

 

 

 #define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */

 #define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */

-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */

-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */

-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */

+#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */

+#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */

+#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */

 

-#define FSMC_BANK2            (FSMC_BASE + 0x10000000)  /*!< FSMC Bank2 base address */

-#define FSMC_BANK3            (FSMC_BASE + 0x20000000)  /*!< FSMC Bank3 base address */

-#define FSMC_BANK4            (FSMC_BASE + 0x30000000)  /*!< FSMC Bank4 base address */

+#define FSMC_BANK2            (FSMC_BASE + 0x10000000U)  /*!< FSMC Bank2 base address */

+#define FSMC_BANK3            (FSMC_BASE + 0x20000000U)  /*!< FSMC Bank3 base address */

+#define FSMC_BANK4            (FSMC_BASE + 0x30000000U)  /*!< FSMC Bank4 base address */

 

-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000)    /*!< FSMC Bank1 registers base address */

-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104)    /*!< FSMC Bank1E registers base address */

-#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x0060)    /*!< FSMC Bank2/Bank3 registers base address */

-#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x00A0)    /*!< FSMC Bank4 registers base address */

+#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x00000000U)    /*!< FSMC Bank1 registers base address */

+#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x00000104U)    /*!< FSMC Bank1E registers base address */

+#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x00000060U)    /*!< FSMC Bank2/Bank3 registers base address */

+#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x000000A0U)    /*!< FSMC Bank4 registers base address */

 

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 

@@ -750,70 +748,70 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define UART4               ((USART_TypeDef *) UART4_BASE)

-#define UART5               ((USART_TypeDef *) UART5_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)

-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)

-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)

-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)

-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)

-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *)TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define TIM12               ((TIM_TypeDef *)TIM12_BASE)

+#define TIM13               ((TIM_TypeDef *)TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *)TIM14_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define UART4               ((USART_TypeDef *)UART4_BASE)

+#define UART5               ((USART_TypeDef *)UART5_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *)GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *)GPIOG_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define TIM9                ((TIM_TypeDef *)TIM9_BASE)

+#define TIM10               ((TIM_TypeDef *)TIM10_BASE)

+#define TIM11               ((TIM_TypeDef *)TIM11_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA2                ((DMA_TypeDef *)DMA2_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

+#define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

+#define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

+#define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

+#define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)

+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)

+#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)

+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -884,14 +882,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -1216,9 +1224,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -1227,9 +1235,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1240,15 +1248,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1258,11 +1266,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1272,11 +1280,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1285,10 +1293,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1307,10 +1315,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1362,11 +1370,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1453,9 +1461,6 @@ typedef struct
 #define RCC_APB2RSTR_ADC1RST_Msk             (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */

 #define RCC_APB2RSTR_ADC1RST                 RCC_APB2RSTR_ADC1RST_Msk          /*!< ADC 1 interface reset */

 

-#define RCC_APB2RSTR_ADC2RST_Pos             (10U)                             

-#define RCC_APB2RSTR_ADC2RST_Msk             (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */

-#define RCC_APB2RSTR_ADC2RST                 RCC_APB2RSTR_ADC2RST_Msk          /*!< ADC 2 interface reset */

 

 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             

 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */

@@ -1607,9 +1612,6 @@ typedef struct
 #define RCC_APB2ENR_ADC1EN_Msk               (0x1U << RCC_APB2ENR_ADC1EN_Pos)  /*!< 0x00000200 */

 #define RCC_APB2ENR_ADC1EN                   RCC_APB2ENR_ADC1EN_Msk            /*!< ADC 1 interface clock enable */

 

-#define RCC_APB2ENR_ADC2EN_Pos               (10U)                             

-#define RCC_APB2ENR_ADC2EN_Msk               (0x1U << RCC_APB2ENR_ADC2EN_Pos)  /*!< 0x00000400 */

-#define RCC_APB2ENR_ADC2EN                   RCC_APB2ENR_ADC2EN_Msk            /*!< ADC 2 interface clock enable */

 

 #define RCC_APB2ENR_TIM1EN_Pos               (11U)                             

 #define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */

@@ -1736,10 +1738,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -2309,7 +2311,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2364,7 +2366,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2403,7 +2405,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2418,7 +2420,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2433,7 +2435,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2451,7 +2453,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2479,7 +2481,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2506,7 +2508,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2527,7 +2529,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2548,7 +2550,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2569,7 +2571,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2604,7 +2606,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2625,7 +2627,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2646,7 +2648,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2667,7 +2669,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2702,7 +2704,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2723,7 +2725,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2744,7 +2746,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2765,7 +2767,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2800,7 +2802,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2821,7 +2823,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2842,7 +2844,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2863,7 +2865,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2907,440 +2909,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3403,9 +2971,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3427,8 +2992,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3487,9 +3052,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3511,7 +3073,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3571,9 +3132,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3595,7 +3153,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3655,9 +3212,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3679,7 +3233,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3739,9 +3292,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3763,7 +3313,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3823,9 +3372,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3847,7 +3393,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4099,7 +3644,6 @@ typedef struct
 /*

  * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)

  */

-#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */

 

 /********************  Bit definition for ADC_SR register  ********************/

 #define ADC_SR_AWD_Pos                      (0U)                               

@@ -4164,14 +3708,6 @@ typedef struct
 #define ADC_CR1_DISCNUM_1                   (0x2U << ADC_CR1_DISCNUM_Pos)      /*!< 0x00004000 */

 #define ADC_CR1_DISCNUM_2                   (0x4U << ADC_CR1_DISCNUM_Pos)      /*!< 0x00008000 */

 

-#define ADC_CR1_DUALMOD_Pos                 (16U)                              

-#define ADC_CR1_DUALMOD_Msk                 (0xFU << ADC_CR1_DUALMOD_Pos)      /*!< 0x000F0000 */

-#define ADC_CR1_DUALMOD                     ADC_CR1_DUALMOD_Msk                /*!< ADC multimode mode selection */

-#define ADC_CR1_DUALMOD_0                   (0x1U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00010000 */

-#define ADC_CR1_DUALMOD_1                   (0x2U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00020000 */

-#define ADC_CR1_DUALMOD_2                   (0x4U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00040000 */

-#define ADC_CR1_DUALMOD_3                   (0x8U << ADC_CR1_DUALMOD_Pos)      /*!< 0x00080000 */

-

 #define ADC_CR1_JAWDEN_Pos                  (22U)                              

 #define ADC_CR1_JAWDEN_Msk                  (0x1U << ADC_CR1_JAWDEN_Pos)       /*!< 0x00400000 */

 #define ADC_CR1_JAWDEN                      ADC_CR1_JAWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group injected */

@@ -4614,9 +4150,6 @@ typedef struct
 #define ADC_DR_DATA_Pos                     (0U)                               

 #define ADC_DR_DATA_Msk                     (0xFFFFU << ADC_DR_DATA_Pos)       /*!< 0x0000FFFF */

 #define ADC_DR_DATA                         ADC_DR_DATA_Msk                    /*!< ADC group regular conversion data */

-#define ADC_DR_ADC2DATA_Pos                 (16U)                              

-#define ADC_DR_ADC2DATA_Msk                 (0xFFFFU << ADC_DR_ADC2DATA_Pos)   /*!< 0xFFFF0000 */

-#define ADC_DR_ADC2DATA                     ADC_DR_ADC2DATA_Msk                /*!< ADC group regular conversion data for ADC slave, in multimode */

 /******************************************************************************/

 /*                                                                            */

 /*                      Digital to Analog Converter                           */

@@ -4857,10 +4390,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -5205,9 +4734,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5311,8 +4837,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5735,14 +5259,14 @@ typedef struct
 #define FSMC_PMEMx_MEMWAITx_Pos             (8U)                               

 #define FSMC_PMEMx_MEMWAITx_Msk             (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */

 #define FSMC_PMEMx_MEMWAITx                 FSMC_PMEMx_MEMWAITx_Msk            /*!< MEMWAITx[7:0] bits (Common memory x wait time) */

-#define FSMC_PMEMx_MEMWAIT2_0               ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define FSMC_PMEMx_MEMWAITx_1               ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define FSMC_PMEMx_MEMWAITx_2               ((uint32_t)0x00000400)             /*!< Bit 2 */

-#define FSMC_PMEMx_MEMWAITx_3               ((uint32_t)0x00000800)             /*!< Bit 3 */

-#define FSMC_PMEMx_MEMWAITx_4               ((uint32_t)0x00001000)             /*!< Bit 4 */

-#define FSMC_PMEMx_MEMWAITx_5               ((uint32_t)0x00002000)             /*!< Bit 5 */

-#define FSMC_PMEMx_MEMWAITx_6               ((uint32_t)0x00004000)             /*!< Bit 6 */

-#define FSMC_PMEMx_MEMWAITx_7               ((uint32_t)0x00008000)             /*!< Bit 7 */

+#define FSMC_PMEMx_MEMWAIT2_0               0x00000100U                        /*!< Bit 0 */

+#define FSMC_PMEMx_MEMWAITx_1               0x00000200U                        /*!< Bit 1 */

+#define FSMC_PMEMx_MEMWAITx_2               0x00000400U                        /*!< Bit 2 */

+#define FSMC_PMEMx_MEMWAITx_3               0x00000800U                        /*!< Bit 3 */

+#define FSMC_PMEMx_MEMWAITx_4               0x00001000U                        /*!< Bit 4 */

+#define FSMC_PMEMx_MEMWAITx_5               0x00002000U                        /*!< Bit 5 */

+#define FSMC_PMEMx_MEMWAITx_6               0x00004000U                        /*!< Bit 6 */

+#define FSMC_PMEMx_MEMWAITx_7               0x00008000U                        /*!< Bit 7 */

 

 #define FSMC_PMEMx_MEMHOLDx_Pos             (16U)                              

 #define FSMC_PMEMx_MEMHOLDx_Msk             (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */

@@ -6440,8 +5964,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -6486,6 +6010,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -7115,12 +6644,9 @@ typedef struct
   */

 

 /****************************** ADC Instances *********************************/

-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

-                                       ((INSTANCE) == ADC2))

-

-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))

 

-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)

 

 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

 

@@ -7128,7 +6654,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -7163,6 +6689,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -7187,6 +6716,8 @@ typedef struct
    ((INSTANCE) == TIM13)   || \

    ((INSTANCE) == TIM14))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)             0U

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3)    || \

@@ -7287,7 +6818,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \

    ((INSTANCE) == TIM5))

 

-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)               0U

 

 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

    ((((INSTANCE) == TIM2) &&                   \

@@ -7334,7 +6865,7 @@ typedef struct
     (((INSTANCE) == TIM14) &&                  \

      (((CHANNEL) == TIM_CHANNEL_1))))

 

-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)         0U

 

 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -7342,7 +6873,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \

    ((INSTANCE) == TIM5))

 

-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)    0U

 

 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -7370,7 +6901,19 @@ typedef struct
    ((INSTANCE) == TIM4)    || \

    ((INSTANCE) == TIM5))

     

-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)     0U

+

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4)    || \

+                                        ((INSTANCE) == TIM5))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4)    || \

+                                                         ((INSTANCE) == TIM5))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

 

 /****************************** END TIM Instances *****************************/

 

@@ -7440,10 +6983,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -7453,20 +7000,20 @@ typedef struct
 /******************************************************************************/

 

 /* Aliases for __IRQn */

-#define ADC1_IRQn               ADC1_2_IRQn

+#define ADC1_2_IRQn             ADC1_IRQn

 #define DMA2_Channel4_IRQn      DMA2_Channel4_5_IRQn

+#define TIM1_UP_TIM10_IRQn      TIM10_IRQn

 #define TIM1_UP_TIM16_IRQn      TIM10_IRQn

 #define TIM1_UP_IRQn            TIM10_IRQn

-#define TIM1_UP_TIM10_IRQn      TIM10_IRQn

+#define TIM1_TRG_COM_IRQn       TIM11_IRQn

 #define TIM1_TRG_COM_TIM11_IRQn TIM11_IRQn

 #define TIM1_TRG_COM_TIM17_IRQn TIM11_IRQn

-#define TIM1_TRG_COM_IRQn       TIM11_IRQn

-#define TIM8_BRK_TIM12_IRQn     TIM12_IRQn

 #define TIM8_BRK_IRQn           TIM12_IRQn

-#define TIM8_UP_IRQn            TIM13_IRQn

+#define TIM8_BRK_TIM12_IRQn     TIM12_IRQn

 #define TIM8_UP_TIM13_IRQn      TIM13_IRQn

-#define TIM8_TRG_COM_IRQn       TIM14_IRQn

+#define TIM8_UP_IRQn            TIM13_IRQn

 #define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn

+#define TIM8_TRG_COM_IRQn       TIM14_IRQn

 #define TIM6_DAC_IRQn           TIM6_IRQn

 #define TIM1_BRK_TIM15_IRQn     TIM9_IRQn

 #define TIM1_BRK_IRQn           TIM9_IRQn

@@ -7474,20 +7021,20 @@ typedef struct
 

 

 /* Aliases for __IRQHandler */

-#define ADC1_IRQHandler               ADC1_2_IRQHandler

+#define ADC1_2_IRQHandler             ADC1_IRQHandler

 #define DMA2_Channel4_IRQHandler      DMA2_Channel4_5_IRQHandler

+#define TIM1_UP_TIM10_IRQHandler      TIM10_IRQHandler

 #define TIM1_UP_TIM16_IRQHandler      TIM10_IRQHandler

 #define TIM1_UP_IRQHandler            TIM10_IRQHandler

-#define TIM1_UP_TIM10_IRQHandler      TIM10_IRQHandler

+#define TIM1_TRG_COM_IRQHandler       TIM11_IRQHandler

 #define TIM1_TRG_COM_TIM11_IRQHandler TIM11_IRQHandler

 #define TIM1_TRG_COM_TIM17_IRQHandler TIM11_IRQHandler

-#define TIM1_TRG_COM_IRQHandler       TIM11_IRQHandler

-#define TIM8_BRK_TIM12_IRQHandler     TIM12_IRQHandler

 #define TIM8_BRK_IRQHandler           TIM12_IRQHandler

-#define TIM8_UP_IRQHandler            TIM13_IRQHandler

+#define TIM8_BRK_TIM12_IRQHandler     TIM12_IRQHandler

 #define TIM8_UP_TIM13_IRQHandler      TIM13_IRQHandler

-#define TIM8_TRG_COM_IRQHandler       TIM14_IRQHandler

+#define TIM8_UP_IRQHandler            TIM13_IRQHandler

 #define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler

+#define TIM8_TRG_COM_IRQHandler       TIM14_IRQHandler

 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler

 #define TIM1_BRK_TIM15_IRQHandler     TIM9_IRQHandler

 #define TIM1_BRK_IRQHandler           TIM9_IRQHandler

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f102x6.h b/os/common/ext/ST/STM32F1xx/stm32f102x6.h
index 4fb02af93..67202c706 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f102x6.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f102x6.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f102x6.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -132,7 +132,6 @@ typedef enum
   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -543,64 +542,64 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x08007FFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-

-

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+

+

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 /* USB device FS */

-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */

-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */

+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */

+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */

 

 

 /**

@@ -611,40 +610,40 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define USB                 ((USB_TypeDef *) USB_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define USB                 ((USB_TypeDef *)USB_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -715,14 +714,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -887,9 +896,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -898,9 +907,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -911,15 +920,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -929,11 +938,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -943,11 +952,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -956,10 +965,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -978,10 +987,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1036,11 +1045,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1284,10 +1293,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1857,7 +1866,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -1912,7 +1921,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -1952,7 +1961,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -1967,7 +1976,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -1985,7 +1994,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2007,7 +2016,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2034,7 +2043,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2055,7 +2064,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2076,7 +2085,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2097,7 +2106,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2132,7 +2141,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2153,7 +2162,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2174,7 +2183,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2195,7 +2204,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2230,7 +2239,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2251,7 +2260,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2272,7 +2281,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2293,7 +2302,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2328,7 +2337,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2349,7 +2358,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2370,7 +2379,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2391,7 +2400,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2417,440 +2426,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -2913,9 +2488,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -2937,8 +2509,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -2997,9 +2569,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3021,7 +2590,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3081,9 +2649,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3105,7 +2670,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3165,9 +2729,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3189,7 +2750,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3249,9 +2809,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3273,7 +2830,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3333,9 +2889,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3357,7 +2910,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4207,10 +3759,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -4555,9 +4103,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -4661,8 +4206,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5255,28 +4798,28 @@ typedef struct
 #define USB_EP_TYPE_MASK_Pos                    (9U)                           

 #define USB_EP_TYPE_MASK_Msk                    (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */

 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */

-#define USB_EP_BULK                             ((uint32_t)0x00000000)         /*!< EndPoint BULK */

-#define USB_EP_CONTROL                          ((uint32_t)0x00000200)         /*!< EndPoint CONTROL */

-#define USB_EP_ISOCHRONOUS                      ((uint32_t)0x00000400)         /*!< EndPoint ISOCHRONOUS */

-#define USB_EP_INTERRUPT                        ((uint32_t)0x00000600)         /*!< EndPoint INTERRUPT */

-#define  USB_EP_T_MASK                       (~USB_EP_T_FIELD & USB_EPREG_MASK)

-                                                                 

-#define  USB_EPKIND_MASK                     (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

-                                                                           /*!< STAT_TX[1:0] STATus for TX transfer */

-#define USB_EP_TX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint TX DISabled */

-#define USB_EP_TX_STALL                         ((uint32_t)0x00000010)         /*!< EndPoint TX STALLed */

-#define USB_EP_TX_NAK                           ((uint32_t)0x00000020)         /*!< EndPoint TX NAKed */

-#define USB_EP_TX_VALID                         ((uint32_t)0x00000030)         /*!< EndPoint TX VALID */

-#define USB_EPTX_DTOG1                          ((uint32_t)0x00000010)         /*!< EndPoint TX Data TOGgle bit1 */

-#define USB_EPTX_DTOG2                          ((uint32_t)0x00000020)         /*!< EndPoint TX Data TOGgle bit2 */

+#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */

+#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */

+#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */

+#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */

+#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)

+

+#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */

+#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */

+#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */

+#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */

+#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */

+#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */

+#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */

 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)

-                                                                           /*!< STAT_RX[1:0] STATus for RX transfer */

-#define USB_EP_RX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint RX DISabled */

-#define USB_EP_RX_STALL                         ((uint32_t)0x00001000)         /*!< EndPoint RX STALLed */

-#define USB_EP_RX_NAK                           ((uint32_t)0x00002000)         /*!< EndPoint RX NAKed */

-#define USB_EP_RX_VALID                         ((uint32_t)0x00003000)         /*!< EndPoint RX VALID */

-#define USB_EPRX_DTOG1                          ((uint32_t)0x00001000)         /*!< EndPoint RX Data TOGgle bit1 */

-#define USB_EPRX_DTOG2                          ((uint32_t)0x00002000)         /*!< EndPoint RX Data TOGgle bit1 */

+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */

+#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */

+#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */

+#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */

+#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */

+#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */

+#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */

 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)

 

 /*******************  Bit definition for USB_EP0R register  *******************/

@@ -5843,52 +5386,52 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/

-#define USB_COUNT0_TX_0_COUNT0_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 0 (low) */

+#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */

 

 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/

-#define USB_COUNT0_TX_1_COUNT0_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 0 (high) */

+#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */

 

 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/

-#define USB_COUNT1_TX_0_COUNT1_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 1 (low) */

+#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */

 

 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/

-#define USB_COUNT1_TX_1_COUNT1_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 1 (high) */

+#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */

 

 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/

-#define USB_COUNT2_TX_0_COUNT2_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 2 (low) */

+#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */

 

 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/

-#define USB_COUNT2_TX_1_COUNT2_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 2 (high) */

+#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */

 

 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/

-#define USB_COUNT3_TX_0_COUNT3_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 3 (low) */

+#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */

 

 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/

-#define USB_COUNT3_TX_1_COUNT3_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 3 (high) */

+#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */

 

 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/

-#define USB_COUNT4_TX_0_COUNT4_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 4 (low) */

+#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */

 

 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/

-#define USB_COUNT4_TX_1_COUNT4_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 4 (high) */

+#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */

 

 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/

-#define USB_COUNT5_TX_0_COUNT5_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 5 (low) */

+#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */

 

 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/

-#define USB_COUNT5_TX_1_COUNT5_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 5 (high) */

+#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */

 

 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/

-#define USB_COUNT6_TX_0_COUNT6_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 6 (low) */

+#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */

 

 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/

-#define USB_COUNT6_TX_1_COUNT6_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 6 (high) */

+#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */

 

 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/

-#define USB_COUNT7_TX_0_COUNT7_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 7 (low) */

+#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */

 

 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/

-#define USB_COUNT7_TX_1_COUNT7_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 7 (high) */

+#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */

 

 /*----------------------------------------------------------------------------*/

 

@@ -6081,196 +5624,196 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/

-#define USB_COUNT0_RX_0_COUNT0_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT0_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/

-#define USB_COUNT0_RX_1_COUNT0_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT0_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/

-#define USB_COUNT1_RX_0_COUNT1_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT1_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/

-#define USB_COUNT1_RX_1_COUNT1_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT1_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/

-#define USB_COUNT2_RX_0_COUNT2_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT2_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/

-#define USB_COUNT2_RX_1_COUNT2_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT2_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/

-#define USB_COUNT3_RX_0_COUNT3_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT3_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/

-#define USB_COUNT3_RX_1_COUNT3_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT3_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/

-#define USB_COUNT4_RX_0_COUNT4_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT4_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/

-#define USB_COUNT4_RX_1_COUNT4_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT4_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/

-#define USB_COUNT5_RX_0_COUNT5_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT5_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/

-#define USB_COUNT5_RX_1_COUNT5_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT5_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/

-#define USB_COUNT6_RX_0_COUNT6_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT6_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT6_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/

-#define USB_COUNT6_RX_1_COUNT6_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */

 

-#define USB_COUNT6_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */

 

-#define USB_COUNT6_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/

-#define USB_COUNT7_RX_0_COUNT7_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT7_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/

-#define USB_COUNT7_RX_1_COUNT7_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT7_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 

 /******************************************************************************/

@@ -6478,8 +6021,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -6524,6 +6067,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -7078,6 +6626,9 @@ typedef struct
 /******************************** I2C Instances *******************************/

 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -7090,6 +6641,8 @@ typedef struct
   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)              0U

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

@@ -7146,7 +6699,7 @@ typedef struct
   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

 

-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)                 0U

 

 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

    ((((INSTANCE) == TIM2) &&                   \

@@ -7161,13 +6714,13 @@ typedef struct
       ((CHANNEL) == TIM_CHANNEL_3) ||          \

       ((CHANNEL) == TIM_CHANNEL_4))))

 

-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)         0U

 

 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

 

-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)    0U

 

 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -7181,7 +6734,15 @@ typedef struct
   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

     

-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)     0U

+

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

 

 /****************************** END TIM Instances *****************************/

 

@@ -7220,7 +6781,7 @@ typedef struct
 

 /***************** UART Instances : DMA mode available **********************/

 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

-                                        ((INSTANCE) == USART2) )

+                                        ((INSTANCE) == USART2))

 

 /****************************** RTC Instances *********************************/

 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

@@ -7233,10 +6794,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -7247,22 +6812,22 @@ typedef struct
 

 /* Aliases for __IRQn */

 #define ADC1_2_IRQn          ADC1_IRQn

-#define CEC_IRQn             USBWakeUp_IRQn

 #define OTG_FS_WKUP_IRQn     USBWakeUp_IRQn

-#define USB_HP_CAN1_TX_IRQn  USB_HP_IRQn

+#define CEC_IRQn             USBWakeUp_IRQn

 #define CAN1_TX_IRQn         USB_HP_IRQn

-#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn

+#define USB_HP_CAN1_TX_IRQn  USB_HP_IRQn

 #define CAN1_RX0_IRQn        USB_LP_IRQn

+#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn

 

 

 /* Aliases for __IRQHandler */

 #define ADC1_2_IRQHandler          ADC1_IRQHandler

-#define CEC_IRQHandler             USBWakeUp_IRQHandler

 #define OTG_FS_WKUP_IRQHandler     USBWakeUp_IRQHandler

-#define USB_HP_CAN1_TX_IRQHandler  USB_HP_IRQHandler

+#define CEC_IRQHandler             USBWakeUp_IRQHandler

 #define CAN1_TX_IRQHandler         USB_HP_IRQHandler

-#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler

+#define USB_HP_CAN1_TX_IRQHandler  USB_HP_IRQHandler

 #define CAN1_RX0_IRQHandler        USB_LP_IRQHandler

+#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler

 

 

 /**

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f102xb.h b/os/common/ext/ST/STM32F1xx/stm32f102xb.h
index 63a394541..75ccf6c29 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f102xb.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f102xb.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f102xb.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -137,7 +137,6 @@ typedef enum
   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -548,68 +547,68 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0801FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-

-

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+

+

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 /* USB device FS */

-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */

-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */

+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */

+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */

 

 

 /**

@@ -620,44 +619,44 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define USB                 ((USB_TypeDef *) USB_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define USB                 ((USB_TypeDef *)USB_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC1_COMMON         ((ADC_Common_TypeDef *)ADC1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -728,14 +727,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -900,9 +909,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -911,9 +920,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -924,15 +933,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -942,11 +951,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -956,11 +965,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -969,10 +978,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -991,10 +1000,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1049,11 +1058,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1321,10 +1330,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1894,7 +1903,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -1949,7 +1958,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -1988,7 +1997,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2003,7 +2012,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2018,7 +2027,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2036,7 +2045,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2061,7 +2070,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2088,7 +2097,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2109,7 +2118,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2130,7 +2139,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2151,7 +2160,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2186,7 +2195,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2207,7 +2216,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2228,7 +2237,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2249,7 +2258,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2284,7 +2293,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2305,7 +2314,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2326,7 +2335,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2347,7 +2356,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2382,7 +2391,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2403,7 +2412,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2424,7 +2433,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2445,7 +2454,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2471,440 +2480,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -2967,9 +2542,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -2991,8 +2563,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3051,9 +2623,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3075,7 +2644,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3135,9 +2703,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3159,7 +2724,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3219,9 +2783,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3243,7 +2804,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3303,9 +2863,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3327,7 +2884,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3387,9 +2943,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3411,7 +2964,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4261,10 +3813,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -4609,9 +4157,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -4715,8 +4260,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5309,28 +4852,28 @@ typedef struct
 #define USB_EP_TYPE_MASK_Pos                    (9U)                           

 #define USB_EP_TYPE_MASK_Msk                    (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */

 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */

-#define USB_EP_BULK                             ((uint32_t)0x00000000)         /*!< EndPoint BULK */

-#define USB_EP_CONTROL                          ((uint32_t)0x00000200)         /*!< EndPoint CONTROL */

-#define USB_EP_ISOCHRONOUS                      ((uint32_t)0x00000400)         /*!< EndPoint ISOCHRONOUS */

-#define USB_EP_INTERRUPT                        ((uint32_t)0x00000600)         /*!< EndPoint INTERRUPT */

-#define  USB_EP_T_MASK                       (~USB_EP_T_FIELD & USB_EPREG_MASK)

-                                                                 

-#define  USB_EPKIND_MASK                     (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

-                                                                           /*!< STAT_TX[1:0] STATus for TX transfer */

-#define USB_EP_TX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint TX DISabled */

-#define USB_EP_TX_STALL                         ((uint32_t)0x00000010)         /*!< EndPoint TX STALLed */

-#define USB_EP_TX_NAK                           ((uint32_t)0x00000020)         /*!< EndPoint TX NAKed */

-#define USB_EP_TX_VALID                         ((uint32_t)0x00000030)         /*!< EndPoint TX VALID */

-#define USB_EPTX_DTOG1                          ((uint32_t)0x00000010)         /*!< EndPoint TX Data TOGgle bit1 */

-#define USB_EPTX_DTOG2                          ((uint32_t)0x00000020)         /*!< EndPoint TX Data TOGgle bit2 */

+#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */

+#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */

+#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */

+#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */

+#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)

+

+#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */

+#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */

+#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */

+#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */

+#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */

+#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */

+#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */

 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)

-                                                                           /*!< STAT_RX[1:0] STATus for RX transfer */

-#define USB_EP_RX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint RX DISabled */

-#define USB_EP_RX_STALL                         ((uint32_t)0x00001000)         /*!< EndPoint RX STALLed */

-#define USB_EP_RX_NAK                           ((uint32_t)0x00002000)         /*!< EndPoint RX NAKed */

-#define USB_EP_RX_VALID                         ((uint32_t)0x00003000)         /*!< EndPoint RX VALID */

-#define USB_EPRX_DTOG1                          ((uint32_t)0x00001000)         /*!< EndPoint RX Data TOGgle bit1 */

-#define USB_EPRX_DTOG2                          ((uint32_t)0x00002000)         /*!< EndPoint RX Data TOGgle bit1 */

+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */

+#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */

+#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */

+#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */

+#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */

+#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */

+#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */

 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)

 

 /*******************  Bit definition for USB_EP0R register  *******************/

@@ -5897,52 +5440,52 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/

-#define USB_COUNT0_TX_0_COUNT0_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 0 (low) */

+#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */

 

 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/

-#define USB_COUNT0_TX_1_COUNT0_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 0 (high) */

+#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */

 

 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/

-#define USB_COUNT1_TX_0_COUNT1_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 1 (low) */

+#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */

 

 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/

-#define USB_COUNT1_TX_1_COUNT1_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 1 (high) */

+#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */

 

 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/

-#define USB_COUNT2_TX_0_COUNT2_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 2 (low) */

+#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */

 

 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/

-#define USB_COUNT2_TX_1_COUNT2_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 2 (high) */

+#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */

 

 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/

-#define USB_COUNT3_TX_0_COUNT3_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 3 (low) */

+#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */

 

 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/

-#define USB_COUNT3_TX_1_COUNT3_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 3 (high) */

+#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */

 

 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/

-#define USB_COUNT4_TX_0_COUNT4_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 4 (low) */

+#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */

 

 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/

-#define USB_COUNT4_TX_1_COUNT4_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 4 (high) */

+#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */

 

 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/

-#define USB_COUNT5_TX_0_COUNT5_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 5 (low) */

+#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */

 

 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/

-#define USB_COUNT5_TX_1_COUNT5_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 5 (high) */

+#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */

 

 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/

-#define USB_COUNT6_TX_0_COUNT6_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 6 (low) */

+#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */

 

 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/

-#define USB_COUNT6_TX_1_COUNT6_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 6 (high) */

+#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */

 

 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/

-#define USB_COUNT7_TX_0_COUNT7_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 7 (low) */

+#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */

 

 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/

-#define USB_COUNT7_TX_1_COUNT7_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 7 (high) */

+#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */

 

 /*----------------------------------------------------------------------------*/

 

@@ -6135,196 +5678,196 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/

-#define USB_COUNT0_RX_0_COUNT0_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT0_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/

-#define USB_COUNT0_RX_1_COUNT0_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT0_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/

-#define USB_COUNT1_RX_0_COUNT1_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT1_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/

-#define USB_COUNT1_RX_1_COUNT1_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT1_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/

-#define USB_COUNT2_RX_0_COUNT2_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT2_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/

-#define USB_COUNT2_RX_1_COUNT2_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT2_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/

-#define USB_COUNT3_RX_0_COUNT3_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT3_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/

-#define USB_COUNT3_RX_1_COUNT3_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT3_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/

-#define USB_COUNT4_RX_0_COUNT4_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT4_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/

-#define USB_COUNT4_RX_1_COUNT4_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT4_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/

-#define USB_COUNT5_RX_0_COUNT5_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT5_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/

-#define USB_COUNT5_RX_1_COUNT5_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT5_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/

-#define USB_COUNT6_RX_0_COUNT6_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT6_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT6_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/

-#define USB_COUNT6_RX_1_COUNT6_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */

 

-#define USB_COUNT6_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */

 

-#define USB_COUNT6_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/

-#define USB_COUNT7_RX_0_COUNT7_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT7_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/

-#define USB_COUNT7_RX_1_COUNT7_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT7_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 

 /******************************************************************************/

@@ -6532,8 +6075,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -6578,6 +6121,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -7163,6 +6711,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -7177,6 +6728,8 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)              0U

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3)    || \

@@ -7247,7 +6800,7 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)               0U

 

 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

    ((((INSTANCE) == TIM2) &&                   \

@@ -7268,14 +6821,14 @@ typedef struct
       ((CHANNEL) == TIM_CHANNEL_3) ||          \

       ((CHANNEL) == TIM_CHANNEL_4))))

 

-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)        0U

 

 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)   0U

 

 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM2)    || \

@@ -7292,7 +6845,17 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

     

-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)     0U

+

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

 

 /****************************** END TIM Instances *****************************/

 

@@ -7353,10 +6916,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103x6.h b/os/common/ext/ST/STM32F1xx/stm32f103x6.h
index 78c09d133..d311634c8 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103x6.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f103x6.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f103x6.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -138,7 +138,6 @@ typedef enum
   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -612,67 +611,67 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x08007FFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-

-

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

+#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+

+

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 /* USB device FS */

-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */

-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */

+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */

+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */

 

 

 /**

@@ -683,43 +682,43 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define USB                 ((USB_TypeDef *) USB_BASE)

-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define USB                 ((USB_TypeDef *)USB_BASE)

+#define CAN1                ((CAN_TypeDef *)CAN1_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *)ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -790,14 +789,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -962,9 +971,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -973,9 +982,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -986,15 +995,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1004,11 +1013,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1018,11 +1027,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1031,10 +1040,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1053,10 +1062,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1111,11 +1120,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1371,10 +1380,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1944,7 +1953,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -1999,7 +2008,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2039,7 +2048,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2054,7 +2063,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2072,7 +2081,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2088,7 +2097,7 @@ typedef struct
 #define AFIO_MAPR_CAN_REMAP_1                (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */

 

 /*!< CAN_REMAP configuration */

-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)            /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

+#define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */

@@ -2108,7 +2117,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2135,7 +2144,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2156,7 +2165,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2177,7 +2186,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2198,7 +2207,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2233,7 +2242,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2254,7 +2263,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2275,7 +2284,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2296,7 +2305,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2331,7 +2340,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2352,7 +2361,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2373,7 +2382,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2394,7 +2403,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2429,7 +2438,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2450,7 +2459,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2471,7 +2480,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2492,7 +2501,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2518,440 +2527,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3014,9 +2589,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3038,8 +2610,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3098,9 +2670,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3122,7 +2691,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3182,9 +2750,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3206,7 +2771,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3266,9 +2830,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3290,7 +2851,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3350,9 +2910,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3374,7 +2931,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3434,9 +2990,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3458,7 +3011,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4319,10 +3871,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -4667,9 +4215,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -4773,8 +4318,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5367,28 +4910,28 @@ typedef struct
 #define USB_EP_TYPE_MASK_Pos                    (9U)                           

 #define USB_EP_TYPE_MASK_Msk                    (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */

 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */

-#define USB_EP_BULK                             ((uint32_t)0x00000000)         /*!< EndPoint BULK */

-#define USB_EP_CONTROL                          ((uint32_t)0x00000200)         /*!< EndPoint CONTROL */

-#define USB_EP_ISOCHRONOUS                      ((uint32_t)0x00000400)         /*!< EndPoint ISOCHRONOUS */

-#define USB_EP_INTERRUPT                        ((uint32_t)0x00000600)         /*!< EndPoint INTERRUPT */

-#define  USB_EP_T_MASK                       (~USB_EP_T_FIELD & USB_EPREG_MASK)

-                                                                 

-#define  USB_EPKIND_MASK                     (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

-                                                                           /*!< STAT_TX[1:0] STATus for TX transfer */

-#define USB_EP_TX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint TX DISabled */

-#define USB_EP_TX_STALL                         ((uint32_t)0x00000010)         /*!< EndPoint TX STALLed */

-#define USB_EP_TX_NAK                           ((uint32_t)0x00000020)         /*!< EndPoint TX NAKed */

-#define USB_EP_TX_VALID                         ((uint32_t)0x00000030)         /*!< EndPoint TX VALID */

-#define USB_EPTX_DTOG1                          ((uint32_t)0x00000010)         /*!< EndPoint TX Data TOGgle bit1 */

-#define USB_EPTX_DTOG2                          ((uint32_t)0x00000020)         /*!< EndPoint TX Data TOGgle bit2 */

+#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */

+#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */

+#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */

+#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */

+#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)

+

+#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */

+#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */

+#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */

+#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */

+#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */

+#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */

+#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */

 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)

-                                                                           /*!< STAT_RX[1:0] STATus for RX transfer */

-#define USB_EP_RX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint RX DISabled */

-#define USB_EP_RX_STALL                         ((uint32_t)0x00001000)         /*!< EndPoint RX STALLed */

-#define USB_EP_RX_NAK                           ((uint32_t)0x00002000)         /*!< EndPoint RX NAKed */

-#define USB_EP_RX_VALID                         ((uint32_t)0x00003000)         /*!< EndPoint RX VALID */

-#define USB_EPRX_DTOG1                          ((uint32_t)0x00001000)         /*!< EndPoint RX Data TOGgle bit1 */

-#define USB_EPRX_DTOG2                          ((uint32_t)0x00002000)         /*!< EndPoint RX Data TOGgle bit1 */

+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */

+#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */

+#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */

+#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */

+#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */

+#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */

+#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */

 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)

 

 /*******************  Bit definition for USB_EP0R register  *******************/

@@ -5955,52 +5498,52 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/

-#define USB_COUNT0_TX_0_COUNT0_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 0 (low) */

+#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */

 

 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/

-#define USB_COUNT0_TX_1_COUNT0_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 0 (high) */

+#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */

 

 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/

-#define USB_COUNT1_TX_0_COUNT1_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 1 (low) */

+#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */

 

 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/

-#define USB_COUNT1_TX_1_COUNT1_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 1 (high) */

+#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */

 

 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/

-#define USB_COUNT2_TX_0_COUNT2_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 2 (low) */

+#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */

 

 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/

-#define USB_COUNT2_TX_1_COUNT2_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 2 (high) */

+#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */

 

 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/

-#define USB_COUNT3_TX_0_COUNT3_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 3 (low) */

+#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */

 

 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/

-#define USB_COUNT3_TX_1_COUNT3_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 3 (high) */

+#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */

 

 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/

-#define USB_COUNT4_TX_0_COUNT4_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 4 (low) */

+#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */

 

 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/

-#define USB_COUNT4_TX_1_COUNT4_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 4 (high) */

+#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */

 

 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/

-#define USB_COUNT5_TX_0_COUNT5_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 5 (low) */

+#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */

 

 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/

-#define USB_COUNT5_TX_1_COUNT5_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 5 (high) */

+#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */

 

 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/

-#define USB_COUNT6_TX_0_COUNT6_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 6 (low) */

+#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */

 

 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/

-#define USB_COUNT6_TX_1_COUNT6_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 6 (high) */

+#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */

 

 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/

-#define USB_COUNT7_TX_0_COUNT7_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 7 (low) */

+#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */

 

 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/

-#define USB_COUNT7_TX_1_COUNT7_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 7 (high) */

+#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */

 

 /*----------------------------------------------------------------------------*/

 

@@ -6193,196 +5736,196 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/

-#define USB_COUNT0_RX_0_COUNT0_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT0_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/

-#define USB_COUNT0_RX_1_COUNT0_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT0_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/

-#define USB_COUNT1_RX_0_COUNT1_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT1_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/

-#define USB_COUNT1_RX_1_COUNT1_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT1_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/

-#define USB_COUNT2_RX_0_COUNT2_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT2_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/

-#define USB_COUNT2_RX_1_COUNT2_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT2_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/

-#define USB_COUNT3_RX_0_COUNT3_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT3_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/

-#define USB_COUNT3_RX_1_COUNT3_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT3_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/

-#define USB_COUNT4_RX_0_COUNT4_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT4_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/

-#define USB_COUNT4_RX_1_COUNT4_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT4_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/

-#define USB_COUNT5_RX_0_COUNT5_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT5_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/

-#define USB_COUNT5_RX_1_COUNT5_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT5_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/

-#define USB_COUNT6_RX_0_COUNT6_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT6_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT6_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/

-#define USB_COUNT6_RX_1_COUNT6_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */

 

-#define USB_COUNT6_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */

 

-#define USB_COUNT6_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/

-#define USB_COUNT7_RX_0_COUNT7_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT7_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/

-#define USB_COUNT7_RX_1_COUNT7_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT7_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /******************************************************************************/

 /*                                                                            */

@@ -10075,8 +9618,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -10121,6 +9664,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -10687,6 +10235,9 @@ typedef struct
 /******************************** I2C Instances *******************************/

 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -10700,6 +10251,8 @@ typedef struct
    ((INSTANCE) == TIM2)    || \

    ((INSTANCE) == TIM3))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM2)    || \

@@ -10824,6 +10377,16 @@ typedef struct
 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\

   ((INSTANCE) == TIM1)

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -10861,7 +10424,7 @@ typedef struct
 

 /***************** UART Instances : DMA mode available **********************/

 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

-                                        ((INSTANCE) == USART2) )

+                                        ((INSTANCE) == USART2))

 

 /****************************** RTC Instances *********************************/

 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

@@ -10874,10 +10437,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -10888,40 +10455,40 @@ typedef struct
 

 /* Aliases for __IRQn */

 #define ADC1_IRQn               ADC1_2_IRQn

-#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

-#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

 #define TIM9_IRQn               TIM1_BRK_IRQn

-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

+#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

+#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

 #define TIM11_IRQn              TIM1_TRG_COM_IRQn

-#define TIM10_IRQn              TIM1_UP_IRQn

-#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

 #define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn

-#define CEC_IRQn                USBWakeUp_IRQn

+#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

+#define TIM10_IRQn              TIM1_UP_IRQn

 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn

-#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn

+#define CEC_IRQn                USBWakeUp_IRQn

 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn

-#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn

+#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn

 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn

+#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn

 

 

 /* Aliases for __IRQHandler */

 #define ADC1_IRQHandler               ADC1_2_IRQHandler

-#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

-#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler

-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

+#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

 #define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

-#define TIM10_IRQHandler              TIM1_UP_IRQHandler

-#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler

-#define CEC_IRQHandler                USBWakeUp_IRQHandler

+#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

+#define TIM10_IRQHandler              TIM1_UP_IRQHandler

 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler

-#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler

+#define CEC_IRQHandler                USBWakeUp_IRQHandler

 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler

-#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

+#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler

 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler

+#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

 

 

 /**

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103xb.h b/os/common/ext/ST/STM32F1xx/stm32f103xb.h
index 77cbd679c..271473107 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103xb.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f103xb.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f103xb.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -143,7 +143,6 @@ typedef enum
   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -617,72 +616,72 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0801FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-

-

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+

+

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 /* USB device FS */

-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */

-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */

+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */

+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */

 

 

 /**

@@ -693,48 +692,48 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define USB                 ((USB_TypeDef *) USB_BASE)

-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define USB                 ((USB_TypeDef *)USB_BASE)

+#define CAN1                ((CAN_TypeDef *)CAN1_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *)ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -805,14 +804,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -977,9 +986,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -988,9 +997,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1001,15 +1010,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1019,11 +1028,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1033,11 +1042,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1046,10 +1055,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1068,10 +1077,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1126,11 +1135,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1416,10 +1425,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1989,7 +1998,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2044,7 +2053,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2083,7 +2092,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2098,7 +2107,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2113,7 +2122,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2131,7 +2140,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2150,7 +2159,7 @@ typedef struct
 #define AFIO_MAPR_CAN_REMAP_1                (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */

 

 /*!< CAN_REMAP configuration */

-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)            /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

+#define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */

@@ -2170,7 +2179,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2197,7 +2206,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2218,7 +2227,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2239,7 +2248,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2260,7 +2269,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2295,7 +2304,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2316,7 +2325,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2337,7 +2346,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2358,7 +2367,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2393,7 +2402,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2414,7 +2423,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2435,7 +2444,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2456,7 +2465,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2491,7 +2500,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2512,7 +2521,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2533,7 +2542,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2554,7 +2563,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -2580,440 +2589,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3076,9 +2651,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3100,8 +2672,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3160,9 +2732,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3184,7 +2753,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3244,9 +2812,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3268,7 +2833,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3328,9 +2892,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3352,7 +2913,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3412,9 +2972,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3436,7 +2993,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3496,9 +3052,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3520,7 +3073,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4381,10 +3933,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -4729,9 +4277,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -4835,8 +4380,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5429,28 +4972,28 @@ typedef struct
 #define USB_EP_TYPE_MASK_Pos                    (9U)                           

 #define USB_EP_TYPE_MASK_Msk                    (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */

 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */

-#define USB_EP_BULK                             ((uint32_t)0x00000000)         /*!< EndPoint BULK */

-#define USB_EP_CONTROL                          ((uint32_t)0x00000200)         /*!< EndPoint CONTROL */

-#define USB_EP_ISOCHRONOUS                      ((uint32_t)0x00000400)         /*!< EndPoint ISOCHRONOUS */

-#define USB_EP_INTERRUPT                        ((uint32_t)0x00000600)         /*!< EndPoint INTERRUPT */

-#define  USB_EP_T_MASK                       (~USB_EP_T_FIELD & USB_EPREG_MASK)

-                                                                 

-#define  USB_EPKIND_MASK                     (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

-                                                                           /*!< STAT_TX[1:0] STATus for TX transfer */

-#define USB_EP_TX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint TX DISabled */

-#define USB_EP_TX_STALL                         ((uint32_t)0x00000010)         /*!< EndPoint TX STALLed */

-#define USB_EP_TX_NAK                           ((uint32_t)0x00000020)         /*!< EndPoint TX NAKed */

-#define USB_EP_TX_VALID                         ((uint32_t)0x00000030)         /*!< EndPoint TX VALID */

-#define USB_EPTX_DTOG1                          ((uint32_t)0x00000010)         /*!< EndPoint TX Data TOGgle bit1 */

-#define USB_EPTX_DTOG2                          ((uint32_t)0x00000020)         /*!< EndPoint TX Data TOGgle bit2 */

+#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */

+#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */

+#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */

+#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */

+#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)

+

+#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */

+#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */

+#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */

+#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */

+#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */

+#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */

+#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */

 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)

-                                                                           /*!< STAT_RX[1:0] STATus for RX transfer */

-#define USB_EP_RX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint RX DISabled */

-#define USB_EP_RX_STALL                         ((uint32_t)0x00001000)         /*!< EndPoint RX STALLed */

-#define USB_EP_RX_NAK                           ((uint32_t)0x00002000)         /*!< EndPoint RX NAKed */

-#define USB_EP_RX_VALID                         ((uint32_t)0x00003000)         /*!< EndPoint RX VALID */

-#define USB_EPRX_DTOG1                          ((uint32_t)0x00001000)         /*!< EndPoint RX Data TOGgle bit1 */

-#define USB_EPRX_DTOG2                          ((uint32_t)0x00002000)         /*!< EndPoint RX Data TOGgle bit1 */

+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */

+#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */

+#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */

+#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */

+#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */

+#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */

+#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */

 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)

 

 /*******************  Bit definition for USB_EP0R register  *******************/

@@ -6017,52 +5560,52 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/

-#define USB_COUNT0_TX_0_COUNT0_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 0 (low) */

+#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */

 

 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/

-#define USB_COUNT0_TX_1_COUNT0_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 0 (high) */

+#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */

 

 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/

-#define USB_COUNT1_TX_0_COUNT1_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 1 (low) */

+#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */

 

 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/

-#define USB_COUNT1_TX_1_COUNT1_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 1 (high) */

+#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */

 

 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/

-#define USB_COUNT2_TX_0_COUNT2_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 2 (low) */

+#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */

 

 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/

-#define USB_COUNT2_TX_1_COUNT2_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 2 (high) */

+#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */

 

 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/

-#define USB_COUNT3_TX_0_COUNT3_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 3 (low) */

+#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */

 

 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/

-#define USB_COUNT3_TX_1_COUNT3_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 3 (high) */

+#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */

 

 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/

-#define USB_COUNT4_TX_0_COUNT4_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 4 (low) */

+#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */

 

 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/

-#define USB_COUNT4_TX_1_COUNT4_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 4 (high) */

+#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */

 

 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/

-#define USB_COUNT5_TX_0_COUNT5_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 5 (low) */

+#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */

 

 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/

-#define USB_COUNT5_TX_1_COUNT5_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 5 (high) */

+#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */

 

 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/

-#define USB_COUNT6_TX_0_COUNT6_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 6 (low) */

+#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */

 

 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/

-#define USB_COUNT6_TX_1_COUNT6_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 6 (high) */

+#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */

 

 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/

-#define USB_COUNT7_TX_0_COUNT7_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 7 (low) */

+#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */

 

 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/

-#define USB_COUNT7_TX_1_COUNT7_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 7 (high) */

+#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */

 

 /*----------------------------------------------------------------------------*/

 

@@ -6255,196 +5798,196 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/

-#define USB_COUNT0_RX_0_COUNT0_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT0_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/

-#define USB_COUNT0_RX_1_COUNT0_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT0_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/

-#define USB_COUNT1_RX_0_COUNT1_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT1_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/

-#define USB_COUNT1_RX_1_COUNT1_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT1_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/

-#define USB_COUNT2_RX_0_COUNT2_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT2_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/

-#define USB_COUNT2_RX_1_COUNT2_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT2_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/

-#define USB_COUNT3_RX_0_COUNT3_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT3_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/

-#define USB_COUNT3_RX_1_COUNT3_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT3_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/

-#define USB_COUNT4_RX_0_COUNT4_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT4_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/

-#define USB_COUNT4_RX_1_COUNT4_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT4_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/

-#define USB_COUNT5_RX_0_COUNT5_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT5_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/

-#define USB_COUNT5_RX_1_COUNT5_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT5_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/

-#define USB_COUNT6_RX_0_COUNT6_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT6_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT6_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/

-#define USB_COUNT6_RX_1_COUNT6_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */

 

-#define USB_COUNT6_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */

 

-#define USB_COUNT6_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/

-#define USB_COUNT7_RX_0_COUNT7_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT7_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/

-#define USB_COUNT7_RX_1_COUNT7_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT7_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /******************************************************************************/

 /*                                                                            */

@@ -10137,8 +9680,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -10183,6 +9726,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -10781,6 +10329,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

@@ -10796,6 +10347,8 @@ typedef struct
    ((INSTANCE) == TIM3)    || \

    ((INSTANCE) == TIM4))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM2)    || \

@@ -10944,6 +10497,18 @@ typedef struct
 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\

   ((INSTANCE) == TIM1)

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -11003,10 +10568,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -11017,40 +10586,40 @@ typedef struct
 

 /* Aliases for __IRQn */

 #define ADC1_IRQn               ADC1_2_IRQn

-#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

-#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

 #define TIM9_IRQn               TIM1_BRK_IRQn

-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

+#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

+#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

 #define TIM11_IRQn              TIM1_TRG_COM_IRQn

-#define TIM10_IRQn              TIM1_UP_IRQn

-#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

 #define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn

-#define CEC_IRQn                USBWakeUp_IRQn

+#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

+#define TIM10_IRQn              TIM1_UP_IRQn

 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn

-#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn

+#define CEC_IRQn                USBWakeUp_IRQn

 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn

-#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn

+#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn

 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn

+#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn

 

 

 /* Aliases for __IRQHandler */

 #define ADC1_IRQHandler               ADC1_2_IRQHandler

-#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

-#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler

-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

+#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

 #define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

-#define TIM10_IRQHandler              TIM1_UP_IRQHandler

-#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler

-#define CEC_IRQHandler                USBWakeUp_IRQHandler

+#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

+#define TIM10_IRQHandler              TIM1_UP_IRQHandler

 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler

-#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler

+#define CEC_IRQHandler                USBWakeUp_IRQHandler

 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler

-#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

+#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler

 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler

+#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

 

 

 /**

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103xe.h b/os/common/ext/ST/STM32F1xx/stm32f103xe.h
index 464e82cec..c97aecc55 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103xe.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f103xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f103xe.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -160,7 +160,6 @@ typedef enum
   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -741,105 +740,105 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0807FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

-#define FSMC_BASE             ((uint32_t)0x60000000) /*!< FSMC base address */

-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */

+#define FSMC_BASE             0x60000000U /*!< FSMC base address */

+#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address */

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)

+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)

-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

+#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x00001C00U)

+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x00002000U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+#define ADC3_BASE             (APB2PERIPH_BASE + 0x00003C00U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400U)

+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408U)

+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CU)

+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430U)

+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444U)

+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

 

 

 #define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */

 #define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */

-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */

-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */

-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */

+#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */

+#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */

+#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */

 

-#define FSMC_BANK2            (FSMC_BASE + 0x10000000)  /*!< FSMC Bank2 base address */

-#define FSMC_BANK3            (FSMC_BASE + 0x20000000)  /*!< FSMC Bank3 base address */

-#define FSMC_BANK4            (FSMC_BASE + 0x30000000)  /*!< FSMC Bank4 base address */

+#define FSMC_BANK2            (FSMC_BASE + 0x10000000U)  /*!< FSMC Bank2 base address */

+#define FSMC_BANK3            (FSMC_BASE + 0x20000000U)  /*!< FSMC Bank3 base address */

+#define FSMC_BANK4            (FSMC_BASE + 0x30000000U)  /*!< FSMC Bank4 base address */

 

-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000)    /*!< FSMC Bank1 registers base address */

-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104)    /*!< FSMC Bank1E registers base address */

-#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x0060)    /*!< FSMC Bank2/Bank3 registers base address */

-#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x00A0)    /*!< FSMC Bank4 registers base address */

+#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x00000000U)    /*!< FSMC Bank1 registers base address */

+#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x00000104U)    /*!< FSMC Bank1E registers base address */

+#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x00000060U)    /*!< FSMC Bank2/Bank3 registers base address */

+#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x000000A0U)    /*!< FSMC Bank4 registers base address */

 

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 /* USB device FS */

-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */

-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */

+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */

+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */

 

 

 /**

@@ -850,69 +849,70 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define UART4               ((USART_TypeDef *) UART4_BASE)

-#define UART5               ((USART_TypeDef *) UART5_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define USB                 ((USB_TypeDef *) USB_BASE)

-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)

-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)

-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)

-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *)TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define UART4               ((USART_TypeDef *)UART4_BASE)

+#define UART5               ((USART_TypeDef *)UART5_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define USB                 ((USB_TypeDef *)USB_BASE)

+#define CAN1                ((CAN_TypeDef *)CAN1_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *)GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *)GPIOG_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *)ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *)ADC3_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *)TIM8_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA2                ((DMA_TypeDef *)DMA2_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

+#define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

+#define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

+#define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

+#define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)

+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)

+#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)

+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -983,14 +983,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -1315,9 +1325,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -1326,9 +1336,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1339,15 +1349,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1357,11 +1367,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1371,11 +1381,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1384,10 +1394,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1406,10 +1416,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1464,11 +1474,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1829,10 +1839,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -2402,7 +2412,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2457,7 +2467,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2496,7 +2506,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2511,7 +2521,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2526,7 +2536,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2544,7 +2554,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2563,7 +2573,7 @@ typedef struct
 #define AFIO_MAPR_CAN_REMAP_1                (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */

 

 /*!< CAN_REMAP configuration */

-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)            /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

+#define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */

@@ -2598,7 +2608,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2625,7 +2635,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2646,7 +2656,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2667,7 +2677,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2688,7 +2698,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2723,7 +2733,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2744,7 +2754,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2765,7 +2775,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2786,7 +2796,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2821,7 +2831,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2842,7 +2852,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2863,7 +2873,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2884,7 +2894,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2919,7 +2929,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2940,7 +2950,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -2961,7 +2971,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -2982,7 +2992,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -3011,440 +3021,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3507,9 +3083,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3531,8 +3104,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3591,9 +3164,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3615,7 +3185,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3675,9 +3244,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3699,7 +3265,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3759,9 +3324,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3783,7 +3345,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3843,9 +3404,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3867,7 +3425,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3927,9 +3484,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -3951,7 +3505,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -4961,10 +4514,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -5309,9 +4858,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5415,8 +4961,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5839,14 +5383,14 @@ typedef struct
 #define FSMC_PMEMx_MEMWAITx_Pos             (8U)                               

 #define FSMC_PMEMx_MEMWAITx_Msk             (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */

 #define FSMC_PMEMx_MEMWAITx                 FSMC_PMEMx_MEMWAITx_Msk            /*!< MEMWAITx[7:0] bits (Common memory x wait time) */

-#define FSMC_PMEMx_MEMWAIT2_0               ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define FSMC_PMEMx_MEMWAITx_1               ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define FSMC_PMEMx_MEMWAITx_2               ((uint32_t)0x00000400)             /*!< Bit 2 */

-#define FSMC_PMEMx_MEMWAITx_3               ((uint32_t)0x00000800)             /*!< Bit 3 */

-#define FSMC_PMEMx_MEMWAITx_4               ((uint32_t)0x00001000)             /*!< Bit 4 */

-#define FSMC_PMEMx_MEMWAITx_5               ((uint32_t)0x00002000)             /*!< Bit 5 */

-#define FSMC_PMEMx_MEMWAITx_6               ((uint32_t)0x00004000)             /*!< Bit 6 */

-#define FSMC_PMEMx_MEMWAITx_7               ((uint32_t)0x00008000)             /*!< Bit 7 */

+#define FSMC_PMEMx_MEMWAIT2_0               0x00000100U                        /*!< Bit 0 */

+#define FSMC_PMEMx_MEMWAITx_1               0x00000200U                        /*!< Bit 1 */

+#define FSMC_PMEMx_MEMWAITx_2               0x00000400U                        /*!< Bit 2 */

+#define FSMC_PMEMx_MEMWAITx_3               0x00000800U                        /*!< Bit 3 */

+#define FSMC_PMEMx_MEMWAITx_4               0x00001000U                        /*!< Bit 4 */

+#define FSMC_PMEMx_MEMWAITx_5               0x00002000U                        /*!< Bit 5 */

+#define FSMC_PMEMx_MEMWAITx_6               0x00004000U                        /*!< Bit 6 */

+#define FSMC_PMEMx_MEMWAITx_7               0x00008000U                        /*!< Bit 7 */

 

 #define FSMC_PMEMx_MEMHOLDx_Pos             (16U)                              

 #define FSMC_PMEMx_MEMHOLDx_Msk             (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */

@@ -6391,28 +5935,28 @@ typedef struct
 #define USB_EP_TYPE_MASK_Pos                    (9U)                           

 #define USB_EP_TYPE_MASK_Msk                    (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */

 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */

-#define USB_EP_BULK                             ((uint32_t)0x00000000)         /*!< EndPoint BULK */

-#define USB_EP_CONTROL                          ((uint32_t)0x00000200)         /*!< EndPoint CONTROL */

-#define USB_EP_ISOCHRONOUS                      ((uint32_t)0x00000400)         /*!< EndPoint ISOCHRONOUS */

-#define USB_EP_INTERRUPT                        ((uint32_t)0x00000600)         /*!< EndPoint INTERRUPT */

-#define  USB_EP_T_MASK                       (~USB_EP_T_FIELD & USB_EPREG_MASK)

-                                                                 

-#define  USB_EPKIND_MASK                     (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

-                                                                           /*!< STAT_TX[1:0] STATus for TX transfer */

-#define USB_EP_TX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint TX DISabled */

-#define USB_EP_TX_STALL                         ((uint32_t)0x00000010)         /*!< EndPoint TX STALLed */

-#define USB_EP_TX_NAK                           ((uint32_t)0x00000020)         /*!< EndPoint TX NAKed */

-#define USB_EP_TX_VALID                         ((uint32_t)0x00000030)         /*!< EndPoint TX VALID */

-#define USB_EPTX_DTOG1                          ((uint32_t)0x00000010)         /*!< EndPoint TX Data TOGgle bit1 */

-#define USB_EPTX_DTOG2                          ((uint32_t)0x00000020)         /*!< EndPoint TX Data TOGgle bit2 */

+#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */

+#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */

+#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */

+#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */

+#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)

+

+#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */

+#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */

+#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */

+#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */

+#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */

+#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */

+#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */

 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)

-                                                                           /*!< STAT_RX[1:0] STATus for RX transfer */

-#define USB_EP_RX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint RX DISabled */

-#define USB_EP_RX_STALL                         ((uint32_t)0x00001000)         /*!< EndPoint RX STALLed */

-#define USB_EP_RX_NAK                           ((uint32_t)0x00002000)         /*!< EndPoint RX NAKed */

-#define USB_EP_RX_VALID                         ((uint32_t)0x00003000)         /*!< EndPoint RX VALID */

-#define USB_EPRX_DTOG1                          ((uint32_t)0x00001000)         /*!< EndPoint RX Data TOGgle bit1 */

-#define USB_EPRX_DTOG2                          ((uint32_t)0x00002000)         /*!< EndPoint RX Data TOGgle bit1 */

+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */

+#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */

+#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */

+#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */

+#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */

+#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */

+#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */

 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)

 

 /*******************  Bit definition for USB_EP0R register  *******************/

@@ -6979,52 +6523,52 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/

-#define USB_COUNT0_TX_0_COUNT0_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 0 (low) */

+#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */

 

 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/

-#define USB_COUNT0_TX_1_COUNT0_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 0 (high) */

+#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */

 

 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/

-#define USB_COUNT1_TX_0_COUNT1_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 1 (low) */

+#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */

 

 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/

-#define USB_COUNT1_TX_1_COUNT1_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 1 (high) */

+#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */

 

 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/

-#define USB_COUNT2_TX_0_COUNT2_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 2 (low) */

+#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */

 

 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/

-#define USB_COUNT2_TX_1_COUNT2_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 2 (high) */

+#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */

 

 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/

-#define USB_COUNT3_TX_0_COUNT3_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 3 (low) */

+#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */

 

 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/

-#define USB_COUNT3_TX_1_COUNT3_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 3 (high) */

+#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */

 

 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/

-#define USB_COUNT4_TX_0_COUNT4_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 4 (low) */

+#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */

 

 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/

-#define USB_COUNT4_TX_1_COUNT4_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 4 (high) */

+#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */

 

 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/

-#define USB_COUNT5_TX_0_COUNT5_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 5 (low) */

+#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */

 

 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/

-#define USB_COUNT5_TX_1_COUNT5_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 5 (high) */

+#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */

 

 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/

-#define USB_COUNT6_TX_0_COUNT6_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 6 (low) */

+#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */

 

 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/

-#define USB_COUNT6_TX_1_COUNT6_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 6 (high) */

+#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */

 

 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/

-#define USB_COUNT7_TX_0_COUNT7_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 7 (low) */

+#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */

 

 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/

-#define USB_COUNT7_TX_1_COUNT7_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 7 (high) */

+#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */

 

 /*----------------------------------------------------------------------------*/

 

@@ -7217,196 +6761,196 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/

-#define USB_COUNT0_RX_0_COUNT0_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT0_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/

-#define USB_COUNT0_RX_1_COUNT0_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT0_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/

-#define USB_COUNT1_RX_0_COUNT1_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT1_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/

-#define USB_COUNT1_RX_1_COUNT1_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT1_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/

-#define USB_COUNT2_RX_0_COUNT2_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT2_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/

-#define USB_COUNT2_RX_1_COUNT2_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT2_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/

-#define USB_COUNT3_RX_0_COUNT3_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT3_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/

-#define USB_COUNT3_RX_1_COUNT3_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT3_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/

-#define USB_COUNT4_RX_0_COUNT4_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT4_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/

-#define USB_COUNT4_RX_1_COUNT4_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT4_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/

-#define USB_COUNT5_RX_0_COUNT5_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT5_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/

-#define USB_COUNT5_RX_1_COUNT5_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT5_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/

-#define USB_COUNT6_RX_0_COUNT6_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT6_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT6_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/

-#define USB_COUNT6_RX_1_COUNT6_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */

 

-#define USB_COUNT6_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */

 

-#define USB_COUNT6_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/

-#define USB_COUNT7_RX_0_COUNT7_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT7_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/

-#define USB_COUNT7_RX_1_COUNT7_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT7_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /******************************************************************************/

 /*                                                                            */

@@ -10899,7 +10443,10 @@ typedef struct
 /*                        Serial Peripheral Interface                         */

 /*                                                                            */

 /******************************************************************************/

-

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define SPI_I2S_SUPPORT       /*!< I2S support */

 /*******************  Bit definition for SPI_CR1 register  ********************/

 #define SPI_CR1_CPHA_Pos                    (0U)                               

 #define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */

@@ -11142,8 +10689,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -11188,6 +10735,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -11773,7 +11325,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -11808,6 +11360,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /******************************** I2S Instances *******************************/

 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \

                                        ((INSTANCE) == SPI3))

@@ -11835,6 +11390,10 @@ typedef struct
    ((INSTANCE) == TIM6)    || \

    ((INSTANCE) == TIM7))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM8)    || \

@@ -12043,6 +11602,22 @@ typedef struct
   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM8))

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4)    || \

+                                        ((INSTANCE) == TIM5)    || \

+                                        ((INSTANCE) == TIM8))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4)    || \

+                                                         ((INSTANCE) == TIM5)    || \

+                                                         ((INSTANCE) == TIM8))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -12113,10 +11688,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -12128,26 +11707,26 @@ typedef struct
 /* Aliases for __IRQn */

 #define ADC1_IRQn               ADC1_2_IRQn

 #define DMA2_Channel4_IRQn      DMA2_Channel4_5_IRQn

-#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

 #define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

+#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

 #define TIM9_IRQn               TIM1_BRK_IRQn

 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

 #define TIM11_IRQn              TIM1_TRG_COM_IRQn

+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

 #define TIM10_IRQn              TIM1_UP_IRQn

-#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

 #define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn

+#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

 #define TIM6_DAC_IRQn           TIM6_IRQn

 #define TIM12_IRQn              TIM8_BRK_IRQn

 #define TIM8_BRK_TIM12_IRQn     TIM8_BRK_IRQn

-#define TIM14_IRQn              TIM8_TRG_COM_IRQn

 #define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn

+#define TIM14_IRQn              TIM8_TRG_COM_IRQn

 #define TIM8_UP_TIM13_IRQn      TIM8_UP_IRQn

 #define TIM13_IRQn              TIM8_UP_IRQn

 #define CEC_IRQn                USBWakeUp_IRQn

 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn

-#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn

 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn

+#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn

 #define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn

 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn

 

@@ -12155,30 +11734,29 @@ typedef struct
 /* Aliases for __IRQHandler */

 #define ADC1_IRQHandler               ADC1_2_IRQHandler

 #define DMA2_Channel4_IRQHandler      DMA2_Channel4_5_IRQHandler

-#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

 #define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

+#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler

 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

 #define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

 #define TIM10_IRQHandler              TIM1_UP_IRQHandler

-#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler

+#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler

 #define TIM12_IRQHandler              TIM8_BRK_IRQHandler

 #define TIM8_BRK_TIM12_IRQHandler     TIM8_BRK_IRQHandler

-#define TIM14_IRQHandler              TIM8_TRG_COM_IRQHandler

 #define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler

+#define TIM14_IRQHandler              TIM8_TRG_COM_IRQHandler

 #define TIM8_UP_TIM13_IRQHandler      TIM8_UP_IRQHandler

 #define TIM13_IRQHandler              TIM8_UP_IRQHandler

 #define CEC_IRQHandler                USBWakeUp_IRQHandler

 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler

-#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler

 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler

+#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler

 #define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler

 

-

 /**

   * @}

   */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103xg.h b/os/common/ext/ST/STM32F1xx/stm32f103xg.h
index 1d30f78c9..f725e56c1 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f103xg.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f103xg.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f103xg.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             1      /*!< STM32 XL-density devices provide an MPU      */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             1U       /*!< STM32 XL-density devices provide an MPU      */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -160,7 +160,6 @@ typedef enum
   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -747,112 +746,112 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */

-#define FLASH_BANK2_END       ((uint32_t)0x080FFFFF) /*!< FLASH END address of bank2 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0807FFFFU /*!< FLASH END address of bank1 */

+#define FLASH_BANK2_END       0x080FFFFFU /*!< FLASH END address of bank2 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

-#define FSMC_BASE             ((uint32_t)0x60000000) /*!< FSMC base address */

-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */

+#define FSMC_BASE             0x60000000U /*!< FSMC base address */

+#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address */

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)

-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)

-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define TIM12_BASE            (APB1PERIPH_BASE + 0x00001800U)

+#define TIM13_BASE            (APB1PERIPH_BASE + 0x00001C00U)

+#define TIM14_BASE            (APB1PERIPH_BASE + 0x00002000U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)

+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)

-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)

-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)

-#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)

-#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

+#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x00001C00U)

+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x00002000U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+#define ADC3_BASE             (APB2PERIPH_BASE + 0x00003C00U)

+#define TIM9_BASE             (APB2PERIPH_BASE + 0x00004C00U)

+#define TIM10_BASE            (APB2PERIPH_BASE + 0x00005000U)

+#define TIM11_BASE            (APB2PERIPH_BASE + 0x00005400U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400U)

+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408U)

+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CU)

+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430U)

+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444U)

+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

 

 

 #define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */

 #define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */

-#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */

-#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */

-#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */

+#define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */

+#define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */

+#define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */

 

-#define FSMC_BANK2            (FSMC_BASE + 0x10000000)  /*!< FSMC Bank2 base address */

-#define FSMC_BANK3            (FSMC_BASE + 0x20000000)  /*!< FSMC Bank3 base address */

-#define FSMC_BANK4            (FSMC_BASE + 0x30000000)  /*!< FSMC Bank4 base address */

+#define FSMC_BANK2            (FSMC_BASE + 0x10000000U)  /*!< FSMC Bank2 base address */

+#define FSMC_BANK3            (FSMC_BASE + 0x20000000U)  /*!< FSMC Bank3 base address */

+#define FSMC_BANK4            (FSMC_BASE + 0x30000000U)  /*!< FSMC Bank4 base address */

 

-#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000)    /*!< FSMC Bank1 registers base address */

-#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104)    /*!< FSMC Bank1E registers base address */

-#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x0060)    /*!< FSMC Bank2/Bank3 registers base address */

-#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x00A0)    /*!< FSMC Bank4 registers base address */

+#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x00000000U)    /*!< FSMC Bank1 registers base address */

+#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x00000104U)    /*!< FSMC Bank1E registers base address */

+#define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x00000060U)    /*!< FSMC Bank2/Bank3 registers base address */

+#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x000000A0U)    /*!< FSMC Bank4 registers base address */

 

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 /* USB device FS */

-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */

-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */

+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */

+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */

 

 

 /**

@@ -863,75 +862,76 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define UART4               ((USART_TypeDef *) UART4_BASE)

-#define UART5               ((USART_TypeDef *) UART5_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define USB                 ((USB_TypeDef *) USB_BASE)

-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)

-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)

-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)

-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)

-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)

-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *)TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define TIM12               ((TIM_TypeDef *)TIM12_BASE)

+#define TIM13               ((TIM_TypeDef *)TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *)TIM14_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define UART4               ((USART_TypeDef *)UART4_BASE)

+#define UART5               ((USART_TypeDef *)UART5_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define USB                 ((USB_TypeDef *)USB_BASE)

+#define CAN1                ((CAN_TypeDef *)CAN1_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *)GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *)GPIOG_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *)ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *)ADC3_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *)TIM8_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define TIM9                ((TIM_TypeDef *)TIM9_BASE)

+#define TIM10               ((TIM_TypeDef *)TIM10_BASE)

+#define TIM11               ((TIM_TypeDef *)TIM11_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA2                ((DMA_TypeDef *)DMA2_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

+#define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

+#define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

+#define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

+#define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)

+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)

+#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)

+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

 

 /**

@@ -1002,14 +1002,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -1334,9 +1344,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -1345,9 +1355,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1358,15 +1368,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1376,11 +1386,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1390,11 +1400,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1403,10 +1413,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1425,10 +1435,10 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_HSE                ((uint32_t)0x00000000)            /*!< HSE clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_HSE_DIV2           ((uint32_t)0x00020000)            /*!< HSE clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */

 

-#define RCC_CFGR_PLLMULL2                    ((uint32_t)0x00000000)            /*!< PLL input clock*2 */

+#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */

 #define RCC_CFGR_PLLMULL3_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL3_Msk                (0x1U << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */

 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */

@@ -1483,11 +1493,11 @@ typedef struct
 #define RCC_CFGR_MCO_1                       (0x2U << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */

 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source  */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1884,10 +1894,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -2457,7 +2467,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2512,7 +2522,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2551,7 +2561,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2566,7 +2576,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2581,7 +2591,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2599,7 +2609,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2618,7 +2628,7 @@ typedef struct
 #define AFIO_MAPR_CAN_REMAP_1                (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */

 

 /*!< CAN_REMAP configuration */

-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)            /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

+#define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */

@@ -2653,7 +2663,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2680,7 +2690,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2701,7 +2711,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2722,7 +2732,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2743,7 +2753,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2778,7 +2788,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2799,7 +2809,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2820,7 +2830,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -2841,7 +2851,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -2876,7 +2886,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -2897,7 +2907,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -2918,7 +2928,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -2939,7 +2949,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -2974,7 +2984,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -2995,7 +3005,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -3016,7 +3026,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -3037,7 +3047,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -3081,440 +3091,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3577,9 +3153,6 @@ typedef struct
 #define EXTI_IMR_MR18_Pos                   (18U)                              

 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */

-#define EXTI_IMR_MR19_Pos                   (19U)                              

-#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_IMR_IM0 EXTI_IMR_MR0

@@ -3601,8 +3174,8 @@ typedef struct
 #define  EXTI_IMR_IM16 EXTI_IMR_MR16

 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

-#define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -3661,9 +3234,6 @@ typedef struct
 #define EXTI_EMR_MR18_Pos                   (18U)                              

 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */

 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */

-#define EXTI_EMR_MR19_Pos                   (19U)                              

-#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */

-#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */

 

 /* References Defines */

 #define  EXTI_EMR_EM0 EXTI_EMR_MR0

@@ -3685,7 +3255,6 @@ typedef struct
 #define  EXTI_EMR_EM16 EXTI_EMR_MR16

 #define  EXTI_EMR_EM17 EXTI_EMR_MR17

 #define  EXTI_EMR_EM18 EXTI_EMR_MR18

-#define  EXTI_EMR_EM19 EXTI_EMR_MR19

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define EXTI_RTSR_TR0_Pos                   (0U)                               

@@ -3745,9 +3314,6 @@ typedef struct
 #define EXTI_RTSR_TR18_Pos                  (18U)                              

 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */

-#define EXTI_RTSR_TR19_Pos                  (19U)                              

-#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0

@@ -3769,7 +3335,6 @@ typedef struct
 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16

 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17

 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18

-#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define EXTI_FTSR_TR0_Pos                   (0U)                               

@@ -3829,9 +3394,6 @@ typedef struct
 #define EXTI_FTSR_TR18_Pos                  (18U)                              

 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */

 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */

-#define EXTI_FTSR_TR19_Pos                  (19U)                              

-#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */

-#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */

 

 /* References Defines */

 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0

@@ -3853,7 +3415,6 @@ typedef struct
 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16

 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17

 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18

-#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define EXTI_SWIER_SWIER0_Pos               (0U)                               

@@ -3913,9 +3474,6 @@ typedef struct
 #define EXTI_SWIER_SWIER18_Pos              (18U)                              

 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */

 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */

-#define EXTI_SWIER_SWIER19_Pos              (19U)                              

-#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */

-#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */

 

 /* References Defines */

 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

@@ -3937,7 +3495,6 @@ typedef struct
 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

-#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define EXTI_PR_PR0_Pos                     (0U)                               

@@ -3997,9 +3554,6 @@ typedef struct
 #define EXTI_PR_PR18_Pos                    (18U)                              

 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */

 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */

-#define EXTI_PR_PR19_Pos                    (19U)                              

-#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */

-#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */

 

 /* References Defines */

 #define  EXTI_PR_PIF0 EXTI_PR_PR0

@@ -4021,7 +3575,6 @@ typedef struct
 #define  EXTI_PR_PIF16 EXTI_PR_PR16

 #define  EXTI_PR_PIF17 EXTI_PR_PR17

 #define  EXTI_PR_PIF18 EXTI_PR_PR18

-#define  EXTI_PR_PIF19 EXTI_PR_PR19

 

 /******************************************************************************/

 /*                                                                            */

@@ -5031,10 +4584,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -5379,9 +4928,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5485,8 +5031,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -5909,14 +5453,14 @@ typedef struct
 #define FSMC_PMEMx_MEMWAITx_Pos             (8U)                               

 #define FSMC_PMEMx_MEMWAITx_Msk             (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */

 #define FSMC_PMEMx_MEMWAITx                 FSMC_PMEMx_MEMWAITx_Msk            /*!< MEMWAITx[7:0] bits (Common memory x wait time) */

-#define FSMC_PMEMx_MEMWAIT2_0               ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define FSMC_PMEMx_MEMWAITx_1               ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define FSMC_PMEMx_MEMWAITx_2               ((uint32_t)0x00000400)             /*!< Bit 2 */

-#define FSMC_PMEMx_MEMWAITx_3               ((uint32_t)0x00000800)             /*!< Bit 3 */

-#define FSMC_PMEMx_MEMWAITx_4               ((uint32_t)0x00001000)             /*!< Bit 4 */

-#define FSMC_PMEMx_MEMWAITx_5               ((uint32_t)0x00002000)             /*!< Bit 5 */

-#define FSMC_PMEMx_MEMWAITx_6               ((uint32_t)0x00004000)             /*!< Bit 6 */

-#define FSMC_PMEMx_MEMWAITx_7               ((uint32_t)0x00008000)             /*!< Bit 7 */

+#define FSMC_PMEMx_MEMWAIT2_0               0x00000100U                        /*!< Bit 0 */

+#define FSMC_PMEMx_MEMWAITx_1               0x00000200U                        /*!< Bit 1 */

+#define FSMC_PMEMx_MEMWAITx_2               0x00000400U                        /*!< Bit 2 */

+#define FSMC_PMEMx_MEMWAITx_3               0x00000800U                        /*!< Bit 3 */

+#define FSMC_PMEMx_MEMWAITx_4               0x00001000U                        /*!< Bit 4 */

+#define FSMC_PMEMx_MEMWAITx_5               0x00002000U                        /*!< Bit 5 */

+#define FSMC_PMEMx_MEMWAITx_6               0x00004000U                        /*!< Bit 6 */

+#define FSMC_PMEMx_MEMWAITx_7               0x00008000U                        /*!< Bit 7 */

 

 #define FSMC_PMEMx_MEMHOLDx_Pos             (16U)                              

 #define FSMC_PMEMx_MEMHOLDx_Msk             (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */

@@ -6461,28 +6005,28 @@ typedef struct
 #define USB_EP_TYPE_MASK_Pos                    (9U)                           

 #define USB_EP_TYPE_MASK_Msk                    (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */

 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */

-#define USB_EP_BULK                             ((uint32_t)0x00000000)         /*!< EndPoint BULK */

-#define USB_EP_CONTROL                          ((uint32_t)0x00000200)         /*!< EndPoint CONTROL */

-#define USB_EP_ISOCHRONOUS                      ((uint32_t)0x00000400)         /*!< EndPoint ISOCHRONOUS */

-#define USB_EP_INTERRUPT                        ((uint32_t)0x00000600)         /*!< EndPoint INTERRUPT */

-#define  USB_EP_T_MASK                       (~USB_EP_T_FIELD & USB_EPREG_MASK)

-                                                                 

-#define  USB_EPKIND_MASK                     (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

-                                                                           /*!< STAT_TX[1:0] STATus for TX transfer */

-#define USB_EP_TX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint TX DISabled */

-#define USB_EP_TX_STALL                         ((uint32_t)0x00000010)         /*!< EndPoint TX STALLed */

-#define USB_EP_TX_NAK                           ((uint32_t)0x00000020)         /*!< EndPoint TX NAKed */

-#define USB_EP_TX_VALID                         ((uint32_t)0x00000030)         /*!< EndPoint TX VALID */

-#define USB_EPTX_DTOG1                          ((uint32_t)0x00000010)         /*!< EndPoint TX Data TOGgle bit1 */

-#define USB_EPTX_DTOG2                          ((uint32_t)0x00000020)         /*!< EndPoint TX Data TOGgle bit2 */

+#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */

+#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */

+#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */

+#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */

+#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)

+

+#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */

+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */

+#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */

+#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */

+#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */

+#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */

+#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */

+#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */

 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)

-                                                                           /*!< STAT_RX[1:0] STATus for RX transfer */

-#define USB_EP_RX_DIS                           ((uint32_t)0x00000000)         /*!< EndPoint RX DISabled */

-#define USB_EP_RX_STALL                         ((uint32_t)0x00001000)         /*!< EndPoint RX STALLed */

-#define USB_EP_RX_NAK                           ((uint32_t)0x00002000)         /*!< EndPoint RX NAKed */

-#define USB_EP_RX_VALID                         ((uint32_t)0x00003000)         /*!< EndPoint RX VALID */

-#define USB_EPRX_DTOG1                          ((uint32_t)0x00001000)         /*!< EndPoint RX Data TOGgle bit1 */

-#define USB_EPRX_DTOG2                          ((uint32_t)0x00002000)         /*!< EndPoint RX Data TOGgle bit1 */

+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */

+#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */

+#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */

+#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */

+#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */

+#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */

+#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */

 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)

 

 /*******************  Bit definition for USB_EP0R register  *******************/

@@ -7049,52 +6593,52 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/

-#define USB_COUNT0_TX_0_COUNT0_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 0 (low) */

+#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */

 

 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/

-#define USB_COUNT0_TX_1_COUNT0_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 0 (high) */

+#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */

 

 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/

-#define USB_COUNT1_TX_0_COUNT1_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 1 (low) */

+#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */

 

 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/

-#define USB_COUNT1_TX_1_COUNT1_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 1 (high) */

+#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */

 

 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/

-#define USB_COUNT2_TX_0_COUNT2_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 2 (low) */

+#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */

 

 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/

-#define USB_COUNT2_TX_1_COUNT2_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 2 (high) */

+#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */

 

 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/

-#define USB_COUNT3_TX_0_COUNT3_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 3 (low) */

+#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */

 

 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/

-#define USB_COUNT3_TX_1_COUNT3_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 3 (high) */

+#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */

 

 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/

-#define USB_COUNT4_TX_0_COUNT4_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 4 (low) */

+#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */

 

 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/

-#define USB_COUNT4_TX_1_COUNT4_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 4 (high) */

+#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */

 

 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/

-#define USB_COUNT5_TX_0_COUNT5_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 5 (low) */

+#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */

 

 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/

-#define USB_COUNT5_TX_1_COUNT5_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 5 (high) */

+#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */

 

 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/

-#define USB_COUNT6_TX_0_COUNT6_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 6 (low) */

+#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */

 

 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/

-#define USB_COUNT6_TX_1_COUNT6_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 6 (high) */

+#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */

 

 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/

-#define USB_COUNT7_TX_0_COUNT7_TX_0             ((uint32_t)0x000003FF)         /*!< Transmission Byte Count 7 (low) */

+#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */

 

 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/

-#define USB_COUNT7_TX_1_COUNT7_TX_1             ((uint32_t)0x03FF0000)         /*!< Transmission Byte Count 7 (high) */

+#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */

 

 /*----------------------------------------------------------------------------*/

 

@@ -7287,196 +6831,196 @@ typedef struct
 /*----------------------------------------------------------------------------*/

 

 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/

-#define USB_COUNT0_RX_0_COUNT0_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT0_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/

-#define USB_COUNT0_RX_1_COUNT0_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT0_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT0_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/

-#define USB_COUNT1_RX_0_COUNT1_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT1_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/

-#define USB_COUNT1_RX_1_COUNT1_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT1_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT1_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/

-#define USB_COUNT2_RX_0_COUNT2_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT2_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/

-#define USB_COUNT2_RX_1_COUNT2_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT2_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT2_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/

-#define USB_COUNT3_RX_0_COUNT3_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT3_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/

-#define USB_COUNT3_RX_1_COUNT3_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT3_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT3_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/

-#define USB_COUNT4_RX_0_COUNT4_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT4_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/

-#define USB_COUNT4_RX_1_COUNT4_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT4_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT4_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/

-#define USB_COUNT5_RX_0_COUNT5_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT5_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/

-#define USB_COUNT5_RX_1_COUNT5_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT5_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT5_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/

-#define USB_COUNT6_RX_0_COUNT6_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT6_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT6_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/

-#define USB_COUNT6_RX_1_COUNT6_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */

 

-#define USB_COUNT6_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */

+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */

 

-#define USB_COUNT6_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */

 

 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/

-#define USB_COUNT7_RX_0_COUNT7_RX_0             ((uint32_t)0x000003FF)         /*!< Reception Byte Count (low) */

+#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */

 

-#define USB_COUNT7_RX_0_NUM_BLOCK_0             ((uint32_t)0x00007C00)         /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           ((uint32_t)0x00000400)         /*!< Bit 0 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           ((uint32_t)0x00000800)         /*!< Bit 1 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           ((uint32_t)0x00001000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           ((uint32_t)0x00002000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           ((uint32_t)0x00004000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_0_BLSIZE_0                ((uint32_t)0x00008000)         /*!< BLock SIZE (low) */

+#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */

 

 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/

-#define USB_COUNT7_RX_1_COUNT7_RX_1             ((uint32_t)0x03FF0000)         /*!< Reception Byte Count (high) */

+#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */

 

-#define USB_COUNT7_RX_1_NUM_BLOCK_1             ((uint32_t)0x7C000000)         /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           ((uint32_t)0x04000000)         /*!< Bit 0 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           ((uint32_t)0x08000000)         /*!< Bit 1 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           ((uint32_t)0x10000000)         /*!< Bit 2 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           ((uint32_t)0x20000000)         /*!< Bit 3 */

-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           ((uint32_t)0x40000000)         /*!< Bit 4 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */

+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */

 

-#define USB_COUNT7_RX_1_BLSIZE_1                ((uint32_t)0x80000000)         /*!< BLock SIZE (high) */

+#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */

 

 /******************************************************************************/

 /*                                                                            */

@@ -10969,7 +10513,10 @@ typedef struct
 /*                        Serial Peripheral Interface                         */

 /*                                                                            */

 /******************************************************************************/

-

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define SPI_I2S_SUPPORT       /*!< I2S support */

 /*******************  Bit definition for SPI_CR1 register  ********************/

 #define SPI_CR1_CPHA_Pos                    (0U)                               

 #define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */

@@ -11212,8 +10759,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -11258,6 +10805,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -11911,7 +11463,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -11946,6 +11498,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /******************************** I2S Instances *******************************/

 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \

                                        ((INSTANCE) == SPI3))

@@ -11979,6 +11534,10 @@ typedef struct
    ((INSTANCE) == TIM13)   || \

    ((INSTANCE) == TIM14))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM8)    || \

@@ -12227,6 +11786,22 @@ typedef struct
   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM8))

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4)    || \

+                                        ((INSTANCE) == TIM5)    || \

+                                        ((INSTANCE) == TIM8))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4)    || \

+                                                         ((INSTANCE) == TIM5)    || \

+                                                         ((INSTANCE) == TIM8))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -12297,10 +11872,14 @@ typedef struct
 

 

 

+#define RCC_HSE_MIN         4000000U

+#define RCC_HSE_MAX        16000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -12312,20 +11891,20 @@ typedef struct
 /* Aliases for __IRQn */

 #define ADC1_IRQn               ADC1_2_IRQn

 #define DMA2_Channel4_IRQn      DMA2_Channel4_5_IRQn

-#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_TIM9_IRQn

 #define TIM1_BRK_IRQn           TIM1_BRK_TIM9_IRQn

+#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_TIM9_IRQn

 #define TIM9_IRQn               TIM1_BRK_TIM9_IRQn

-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn

-#define TIM1_TRG_COM_IRQn       TIM1_TRG_COM_TIM11_IRQn

 #define TIM11_IRQn              TIM1_TRG_COM_TIM11_IRQn

+#define TIM1_TRG_COM_IRQn       TIM1_TRG_COM_TIM11_IRQn

+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn

 #define TIM10_IRQn              TIM1_UP_TIM10_IRQn

 #define TIM1_UP_TIM16_IRQn      TIM1_UP_TIM10_IRQn

 #define TIM1_UP_IRQn            TIM1_UP_TIM10_IRQn

 #define TIM6_DAC_IRQn           TIM6_IRQn

 #define TIM12_IRQn              TIM8_BRK_TIM12_IRQn

 #define TIM8_BRK_IRQn           TIM8_BRK_TIM12_IRQn

-#define TIM14_IRQn              TIM8_TRG_COM_TIM14_IRQn

 #define TIM8_TRG_COM_IRQn       TIM8_TRG_COM_TIM14_IRQn

+#define TIM14_IRQn              TIM8_TRG_COM_TIM14_IRQn

 #define TIM8_UP_IRQn            TIM8_UP_TIM13_IRQn

 #define TIM13_IRQn              TIM8_UP_TIM13_IRQn

 #define CEC_IRQn                USBWakeUp_IRQn

@@ -12339,20 +11918,20 @@ typedef struct
 /* Aliases for __IRQHandler */

 #define ADC1_IRQHandler               ADC1_2_IRQHandler

 #define DMA2_Channel4_IRQHandler      DMA2_Channel4_5_IRQHandler

-#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_TIM9_IRQHandler

 #define TIM1_BRK_IRQHandler           TIM1_BRK_TIM9_IRQHandler

+#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_TIM9_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_TIM9_IRQHandler

-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler

-#define TIM1_TRG_COM_IRQHandler       TIM1_TRG_COM_TIM11_IRQHandler

 #define TIM11_IRQHandler              TIM1_TRG_COM_TIM11_IRQHandler

+#define TIM1_TRG_COM_IRQHandler       TIM1_TRG_COM_TIM11_IRQHandler

+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler

 #define TIM10_IRQHandler              TIM1_UP_TIM10_IRQHandler

 #define TIM1_UP_TIM16_IRQHandler      TIM1_UP_TIM10_IRQHandler

 #define TIM1_UP_IRQHandler            TIM1_UP_TIM10_IRQHandler

 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler

 #define TIM12_IRQHandler              TIM8_BRK_TIM12_IRQHandler

 #define TIM8_BRK_IRQHandler           TIM8_BRK_TIM12_IRQHandler

-#define TIM14_IRQHandler              TIM8_TRG_COM_TIM14_IRQHandler

 #define TIM8_TRG_COM_IRQHandler       TIM8_TRG_COM_TIM14_IRQHandler

+#define TIM14_IRQHandler              TIM8_TRG_COM_TIM14_IRQHandler

 #define TIM8_UP_IRQHandler            TIM8_UP_TIM13_IRQHandler

 #define TIM13_IRQHandler              TIM8_UP_TIM13_IRQHandler

 #define CEC_IRQHandler                USBWakeUp_IRQHandler

@@ -12362,7 +11941,6 @@ typedef struct
 #define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler

 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler

 

-

 /**

   * @}

   */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f105xc.h b/os/common/ext/ST/STM32F1xx/stm32f105xc.h
index 137ebfa3a..c3dab14d6 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f105xc.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f105xc.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f105xc.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -159,7 +159,6 @@ typedef enum
   OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -770,99 +769,99 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0803FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)

+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)

-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-

-

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400U)

+#define CAN2_BASE             (APB1PERIPH_BASE + 0x00006800U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400U)

+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408U)

+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CU)

+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430U)

+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444U)

+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+

+

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 /*!< USB registers base address */

-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)

-

-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x00000000)

-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x00000800)

-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x00000900)

-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0x00000B00)

-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x00000020)

-#define USB_OTG_HOST_BASE                    ((uint32_t )0x00000400)

-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x00000440)

-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x00000500)

-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x00000020)

-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0x00000E00)

-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x00001000)

-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x00001000)

+#define USB_OTG_FS_PERIPH_BASE               0x50000000U

+

+#define USB_OTG_GLOBAL_BASE                  0x00000000U

+#define USB_OTG_DEVICE_BASE                  0x00000800U

+#define USB_OTG_IN_ENDPOINT_BASE             0x00000900U

+#define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00U

+#define USB_OTG_EP_REG_SIZE                  0x00000020U

+#define USB_OTG_HOST_BASE                    0x00000400U

+#define USB_OTG_HOST_PORT_BASE               0x00000440U

+#define USB_OTG_HOST_CHANNEL_BASE            0x00000500U

+#define USB_OTG_HOST_CHANNEL_SIZE            0x00000020U

+#define USB_OTG_PCGCCTL_BASE                 0x00000E00U

+#define USB_OTG_FIFO_BASE                    0x00001000U

+#define USB_OTG_FIFO_SIZE                    0x00001000U

 

 /**

   * @}

@@ -872,63 +871,64 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define UART4               ((USART_TypeDef *) UART4_BASE)

-#define UART5               ((USART_TypeDef *) UART5_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)

-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

-

-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *)TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define UART4               ((USART_TypeDef *)UART4_BASE)

+#define UART5               ((USART_TypeDef *)UART5_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define CAN1                ((CAN_TypeDef *)CAN1_BASE)

+#define CAN2                ((CAN_TypeDef *)CAN2_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *)ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA2                ((DMA_TypeDef *)DMA2_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

+#define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

+#define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

+#define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

+#define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

+

+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)

 

 /**

   * @}

@@ -998,14 +998,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -1321,12 +1331,23 @@ typedef struct
 #define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */

 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< PLL clock ready flag */

 

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define RCC_PLL2_SUPPORT                                                       /*!< Support PLL2 */

+

 #define RCC_CR_PLL2ON_Pos                    (26U)                             

 #define RCC_CR_PLL2ON_Msk                    (0x1U << RCC_CR_PLL2ON_Pos)       /*!< 0x04000000 */

 #define RCC_CR_PLL2ON                        RCC_CR_PLL2ON_Msk                 /*!< PLL2 enable */

 #define RCC_CR_PLL2RDY_Pos                   (27U)                             

 #define RCC_CR_PLL2RDY_Msk                   (0x1U << RCC_CR_PLL2RDY_Pos)      /*!< 0x08000000 */

 #define RCC_CR_PLL2RDY                       RCC_CR_PLL2RDY_Msk                /*!< PLL2 clock ready flag */

+

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLL3 (PLLI2S)*/

+

 #define RCC_CR_PLL3ON_Pos                    (28U)                             

 #define RCC_CR_PLL3ON_Msk                    (0x1U << RCC_CR_PLL3ON_Pos)       /*!< 0x10000000 */

 #define RCC_CR_PLL3ON                        RCC_CR_PLL3ON_Msk                 /*!< PLL3 enable */

@@ -1342,9 +1363,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -1353,9 +1374,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1366,15 +1387,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1384,11 +1405,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1398,11 +1419,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1411,10 +1432,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1433,8 +1454,8 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_PREDIV1            ((uint32_t)0x00000000)            /*!< PREDIV1 clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       ((uint32_t)0x00020000)            /*!< PREDIV1 clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1            0x00000000U                       /*!< PREDIV1 clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       0x00020000U                       /*!< PREDIV1 clock divided by 2 for PLL entry */

 

 #define RCC_CFGR_PLLMULL4_Pos                (19U)                             

 #define RCC_CFGR_PLLMULL4_Msk                (0x1U << RCC_CFGR_PLLMULL4_Pos)   /*!< 0x00080000 */

@@ -1454,7 +1475,7 @@ typedef struct
 #define RCC_CFGR_PLLMULL9_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL9_Msk                (0x7U << RCC_CFGR_PLLMULL9_Pos)   /*!< 0x001C0000 */

 #define RCC_CFGR_PLLMULL9                    RCC_CFGR_PLLMULL9_Msk             /*!< PLL input clock * 9 */

-#define RCC_CFGR_PLLMULL6_5                  ((uint32_t)0x00340000)            /*!< PLL input clock * 6.5 */

+#define RCC_CFGR_PLLMULL6_5                  0x00340000U                       /*!< PLL input clock * 6.5 */

  

 #define RCC_CFGR_OTGFSPRE_Pos                (22U)                             

 #define RCC_CFGR_OTGFSPRE_Msk                (0x1U << RCC_CFGR_OTGFSPRE_Pos)   /*!< 0x00400000 */

@@ -1469,15 +1490,15 @@ typedef struct
 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 #define RCC_CFGR_MCO_3                       (0x8U << RCC_CFGR_MCO_Pos)        /*!< 0x08000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

-#define RCC_CFGR_MCO_PLL2CLK                 ((uint32_t)0x08000000)            /*!< PLL2 clock selected as MCO source*/

-#define RCC_CFGR_MCO_PLL3CLK_DIV2            ((uint32_t)0x09000000)            /*!< PLL3 clock divided by 2 selected as MCO source*/

-#define RCC_CFGR_MCO_EXT_HSE                 ((uint32_t)0x0A000000)            /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */

-#define RCC_CFGR_MCO_PLL3CLK                 ((uint32_t)0x0B000000)            /*!< PLL3 clock selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                       /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                       /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                       /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                       /*!< HSE clock selected as MCO source */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                       /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_PLL2CLK                 0x08000000U                       /*!< PLL2 clock selected as MCO source*/

+#define RCC_CFGR_MCO_PLL3CLK_DIV2            0x09000000U                       /*!< PLL3 clock divided by 2 selected as MCO source*/

+#define RCC_CFGR_MCO_EXT_HSE                 0x0A000000U                       /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */

+#define RCC_CFGR_MCO_PLL3CLK                 0x0B000000U                       /*!< PLL3 clock selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1834,10 +1855,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1890,7 +1911,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV1_2                  (0x4U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000004 */

 #define RCC_CFGR2_PREDIV1_3                  (0x8U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000008 */

 

-#define RCC_CFGR2_PREDIV1_DIV1               ((uint32_t)0x00000000)            /*!< PREDIV1 input clock not divided */

+#define RCC_CFGR2_PREDIV1_DIV1               0x00000000U                       /*!< PREDIV1 input clock not divided */

 #define RCC_CFGR2_PREDIV1_DIV2_Pos           (0U)                              

 #define RCC_CFGR2_PREDIV1_DIV2_Msk           (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */

 #define RCC_CFGR2_PREDIV1_DIV2               RCC_CFGR2_PREDIV1_DIV2_Msk        /*!< PREDIV1 input clock divided by 2 */

@@ -1946,7 +1967,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV2_2                  (0x4U << RCC_CFGR2_PREDIV2_Pos)   /*!< 0x00000040 */

 #define RCC_CFGR2_PREDIV2_3                  (0x8U << RCC_CFGR2_PREDIV2_Pos)   /*!< 0x00000080 */

 

-#define RCC_CFGR2_PREDIV2_DIV1               ((uint32_t)0x00000000)            /*!< PREDIV2 input clock not divided */

+#define RCC_CFGR2_PREDIV2_DIV1               0x00000000U                       /*!< PREDIV2 input clock not divided */

 #define RCC_CFGR2_PREDIV2_DIV2_Pos           (4U)                              

 #define RCC_CFGR2_PREDIV2_DIV2_Msk           (0x1U << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */

 #define RCC_CFGR2_PREDIV2_DIV2               RCC_CFGR2_PREDIV2_DIV2_Msk        /*!< PREDIV2 input clock divided by 2 */

@@ -2073,7 +2094,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV1SRC_PLL2_Pos        (16U)                             

 #define RCC_CFGR2_PREDIV1SRC_PLL2_Msk        (0x1U << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */

 #define RCC_CFGR2_PREDIV1SRC_PLL2            RCC_CFGR2_PREDIV1SRC_PLL2_Msk     /*!< PLL2 selected as PREDIV1 entry clock source */

-#define RCC_CFGR2_PREDIV1SRC_HSE             ((uint32_t)0x00000000)            /*!< HSE selected as PREDIV1 entry clock source */

+#define RCC_CFGR2_PREDIV1SRC_HSE             0x00000000U                       /*!< HSE selected as PREDIV1 entry clock source */

 #define RCC_CFGR2_I2S2SRC_Pos                (17U)                             

 #define RCC_CFGR2_I2S2SRC_Msk                (0x1U << RCC_CFGR2_I2S2SRC_Pos)   /*!< 0x00020000 */

 #define RCC_CFGR2_I2S2SRC                    RCC_CFGR2_I2S2SRC_Msk             /*!< I2S2 entry clock source */

@@ -2612,7 +2633,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2667,7 +2688,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2706,7 +2727,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2721,7 +2742,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2736,7 +2757,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2754,7 +2775,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2773,7 +2794,7 @@ typedef struct
 #define AFIO_MAPR_CAN_REMAP_1                (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */

 

 /*!< CAN_REMAP configuration */

-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)            /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

+#define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */

@@ -2796,7 +2817,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2852,7 +2873,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2873,7 +2894,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2894,7 +2915,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -2915,7 +2936,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -2950,7 +2971,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -2971,7 +2992,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -2992,7 +3013,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -3013,7 +3034,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -3048,7 +3069,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -3069,7 +3090,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -3090,7 +3111,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -3111,7 +3132,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -3146,7 +3167,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -3167,7 +3188,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -3188,7 +3209,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -3209,7 +3230,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -3235,440 +3256,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3756,7 +3343,8 @@ typedef struct
 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

 #define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x000FFFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -5185,10 +4773,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -5533,9 +5117,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5639,8 +5220,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -12583,7 +12162,11 @@ typedef struct
 /*                        Serial Peripheral Interface                         */

 /*                                                                            */

 /******************************************************************************/

-

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define SPI_I2S_SUPPORT       /*!< I2S support */

+#define I2S2_I2S3_CLOCK_FEATURE

 /*******************  Bit definition for SPI_CR1 register  ********************/

 #define SPI_CR1_CPHA_Pos                    (0U)                               

 #define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */

@@ -12826,8 +12409,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -12872,6 +12455,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -13622,10 +13210,11 @@ typedef struct
 #define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           

 #define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

 #define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */

-#define USB_OTG_GAHBCFG_HBSTLEN_0               (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */

-#define USB_OTG_GAHBCFG_HBSTLEN_1               (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */

-#define USB_OTG_GAHBCFG_HBSTLEN_2               (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */

-#define USB_OTG_GAHBCFG_HBSTLEN_3               (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

 #define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           

 #define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

 #define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */

@@ -14762,7 +14351,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -14795,6 +14384,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /******************************** I2S Instances *******************************/

 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \

                                        ((INSTANCE) == SPI3))

@@ -14818,6 +14410,8 @@ typedef struct
    ((INSTANCE) == TIM6)    || \

    ((INSTANCE) == TIM7))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)  ((INSTANCE) == TIM1)

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM2)    || \

@@ -14994,6 +14588,20 @@ typedef struct
 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\

   ((INSTANCE) == TIM1)

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4)    || \

+                                        ((INSTANCE) == TIM5))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4)    || \

+                                                         ((INSTANCE) == TIM5))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -15064,10 +14672,14 @@ typedef struct
 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)

 

 

+#define RCC_HSE_MIN         3000000U

+#define RCC_HSE_MAX        25000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -15078,19 +14690,19 @@ typedef struct
 

 /* Aliases for __IRQn */

 #define ADC1_IRQn               ADC1_2_IRQn

-#define USB_LP_IRQn             CAN1_RX0_IRQn

 #define USB_LP_CAN1_RX0_IRQn    CAN1_RX0_IRQn

+#define USB_LP_IRQn             CAN1_RX0_IRQn

 #define USB_HP_CAN1_TX_IRQn     CAN1_TX_IRQn

 #define USB_HP_IRQn             CAN1_TX_IRQn

 #define DMA2_Channel4_5_IRQn    DMA2_Channel4_IRQn

 #define USBWakeUp_IRQn          OTG_FS_WKUP_IRQn

 #define CEC_IRQn                OTG_FS_WKUP_IRQn

-#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

 #define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

+#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

 #define TIM9_IRQn               TIM1_BRK_IRQn

+#define TIM11_IRQn              TIM1_TRG_COM_IRQn

 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

-#define TIM11_IRQn              TIM1_TRG_COM_IRQn

 #define TIM10_IRQn              TIM1_UP_IRQn

 #define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

 #define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn

@@ -15099,25 +14711,24 @@ typedef struct
 

 /* Aliases for __IRQHandler */

 #define ADC1_IRQHandler               ADC1_2_IRQHandler

-#define USB_LP_IRQHandler             CAN1_RX0_IRQHandler

 #define USB_LP_CAN1_RX0_IRQHandler    CAN1_RX0_IRQHandler

+#define USB_LP_IRQHandler             CAN1_RX0_IRQHandler

 #define USB_HP_CAN1_TX_IRQHandler     CAN1_TX_IRQHandler

 #define USB_HP_IRQHandler             CAN1_TX_IRQHandler

 #define DMA2_Channel4_5_IRQHandler    DMA2_Channel4_IRQHandler

 #define USBWakeUp_IRQHandler          OTG_FS_WKUP_IRQHandler

 #define CEC_IRQHandler                OTG_FS_WKUP_IRQHandler

-#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

 #define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

+#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler

+#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

-#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

 #define TIM10_IRQHandler              TIM1_UP_IRQHandler

 #define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler

 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler

 

-

 /**

   * @}

   */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f107xc.h b/os/common/ext/ST/STM32F1xx/stm32f107xc.h
index 542f5aa5f..7cec10ce6 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f107xc.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f107xc.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f107xc.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 

   *          This file contains all the peripheral register's definitions, bits 

   *          definitions and memory mapping for STM32F1xx devices.            

@@ -16,7 +16,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -65,10 +65,10 @@
 /**

   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 

  */

- #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */

-#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */

-#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */

-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */

+#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */

+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */

+#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */

+#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */

 

 /**

   * @}

@@ -161,7 +161,6 @@ typedef enum
   OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */

 } IRQn_Type;

 

-

 /**

   * @}

   */

@@ -844,104 +843,104 @@ typedef struct
   */

 

 

-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */

-#define FLASH_BANK1_END       ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */

-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */

-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

+#define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */

+#define FLASH_BANK1_END       0x0803FFFFU /*!< FLASH END address of bank1 */

+#define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */

+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */

 

-#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */

-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */

+#define SRAM_BB_BASE          0x22000000U /*!< SRAM base address in the bit-band region */

+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region */

 

 

 /*!< Peripheral memory map */

 #define APB1PERIPH_BASE       PERIPH_BASE

-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)

-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

-

-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)

-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)

-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)

-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)

-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)

-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)

-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)

-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)

-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)

-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)

-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)

-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)

-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)

-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)

-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)

-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)

+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)

+

+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)

+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)

+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)

+#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)

+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)

+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)

+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)

+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)

+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)

+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)

+#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)

+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)

+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)

+#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)

+#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)

+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)

 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)

-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)

-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)

-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)

-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)

-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)

-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)

-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)

-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)

-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)

-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)

-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)

-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)

-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)

-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)

-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)

-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

-

-#define SDIO_BASE             (PERIPH_BASE + 0x18000)

-

-#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)

-#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)

-#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)

-#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)

-#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)

-#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)

-#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)

-#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)

-#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)

-#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)

-#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)

-#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)

-#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)

-#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)

-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

-#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)

-

-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

-#define FLASHSIZE_BASE        ((uint32_t)0x1FFFF7E0)    /*!< FLASH Size register base address */

-#define UID_BASE              ((uint32_t)0x1FFFF7E8)    /*!< Unique device ID register base address */

-#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */

-

-#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)

+#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400U)

+#define CAN2_BASE             (APB1PERIPH_BASE + 0x00006800U)

+#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00U)

+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)

+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)

+#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000U)

+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)

+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800U)

+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00U)

+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000U)

+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400U)

+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800U)

+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)

+#define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800U)

+#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00U)

+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)

+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)

+

+#define SDIO_BASE             (PERIPH_BASE + 0x00018000U)

+

+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000U)

+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008U)

+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CU)

+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030U)

+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044U)

+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058U)

+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CU)

+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080U)

+#define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400U)

+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408U)

+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CU)

+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430U)

+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444U)

+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458U)

+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000U)

+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)

+

+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */

+#define FLASHSIZE_BASE        0x1FFFF7E0U    /*!< FLASH Size register base address */

+#define UID_BASE              0x1FFFF7E8U    /*!< Unique device ID register base address */

+#define OB_BASE               0x1FFFF800U    /*!< Flash Option Bytes base address */

+

+#define ETH_BASE              (AHBPERIPH_BASE + 0x00008000U)

 #define ETH_MAC_BASE          (ETH_BASE)

-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)

-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)

-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)

+#define ETH_MMC_BASE          (ETH_BASE + 0x00000100U)

+#define ETH_PTP_BASE          (ETH_BASE + 0x00000700U)

+#define ETH_DMA_BASE          (ETH_BASE + 0x00001000U)

 

 

-#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */

+#define DBGMCU_BASE          0xE0042000U /*!< Debug MCU registers base address */

 

 

 /*!< USB registers base address */

-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)

-

-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x00000000)

-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x00000800)

-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x00000900)

-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0x00000B00)

-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x00000020)

-#define USB_OTG_HOST_BASE                    ((uint32_t )0x00000400)

-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x00000440)

-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x00000500)

-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x00000020)

-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0x00000E00)

-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x00001000)

-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x00001000)

+#define USB_OTG_FS_PERIPH_BASE               0x50000000U

+

+#define USB_OTG_GLOBAL_BASE                  0x00000000U

+#define USB_OTG_DEVICE_BASE                  0x00000800U

+#define USB_OTG_IN_ENDPOINT_BASE             0x00000900U

+#define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00U

+#define USB_OTG_EP_REG_SIZE                  0x00000020U

+#define USB_OTG_HOST_BASE                    0x00000400U

+#define USB_OTG_HOST_PORT_BASE               0x00000440U

+#define USB_OTG_HOST_CHANNEL_BASE            0x00000500U

+#define USB_OTG_HOST_CHANNEL_SIZE            0x00000020U

+#define USB_OTG_PCGCCTL_BASE                 0x00000E00U

+#define USB_OTG_FIFO_BASE                    0x00001000U

+#define USB_OTG_FIFO_SIZE                    0x00001000U

 

 /**

   * @}

@@ -951,64 +950,65 @@ typedef struct
   * @{

   */  

 

-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

-#define RTC                 ((RTC_TypeDef *) RTC_BASE)

-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)

-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)

-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

-#define USART2              ((USART_TypeDef *) USART2_BASE)

-#define USART3              ((USART_TypeDef *) USART3_BASE)

-#define UART4               ((USART_TypeDef *) UART4_BASE)

-#define UART5               ((USART_TypeDef *) UART5_BASE)

-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)

-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)

-#define BKP                 ((BKP_TypeDef *) BKP_BASE)

-#define PWR                 ((PWR_TypeDef *) PWR_BASE)

-#define DAC                 ((DAC_TypeDef *) DAC_BASE)

-#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)

-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

-#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_BASE)

-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

-#define USART1              ((USART_TypeDef *) USART1_BASE)

-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)

-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

-#define RCC                 ((RCC_TypeDef *) RCC_BASE)

-#define CRC                 ((CRC_TypeDef *) CRC_BASE)

-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

-#define OB                  ((OB_TypeDef *) OB_BASE)

+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *)TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)

+#define RTC                 ((RTC_TypeDef *)RTC_BASE)

+#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)

+#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)

+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)

+#define USART2              ((USART_TypeDef *)USART2_BASE)

+#define USART3              ((USART_TypeDef *)USART3_BASE)

+#define UART4               ((USART_TypeDef *)UART4_BASE)

+#define UART5               ((USART_TypeDef *)UART5_BASE)

+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)

+#define CAN1                ((CAN_TypeDef *)CAN1_BASE)

+#define CAN2                ((CAN_TypeDef *)CAN2_BASE)

+#define BKP                 ((BKP_TypeDef *)BKP_BASE)

+#define PWR                 ((PWR_TypeDef *)PWR_BASE)

+#define DAC1                ((DAC_TypeDef *)DAC_BASE)

+#define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */

+#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)

+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)

+#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)

+#define ADC1                ((ADC_TypeDef *)ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *)ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)

+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)

+#define USART1              ((USART_TypeDef *)USART1_BASE)

+#define SDIO                ((SDIO_TypeDef *)SDIO_BASE)

+#define DMA1                ((DMA_TypeDef *)DMA1_BASE)

+#define DMA2                ((DMA_TypeDef *)DMA2_BASE)

+#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

+#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

+#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

+#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

+#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

+#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

+#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

+#define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

+#define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

+#define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

+#define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

+#define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

+#define RCC                 ((RCC_TypeDef *)RCC_BASE)

+#define CRC                 ((CRC_TypeDef *)CRC_BASE)

+#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)

+#define OB                  ((OB_TypeDef *)OB_BASE)

 #define ETH                 ((ETH_TypeDef *) ETH_BASE)

-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)

 

-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)

+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)

 

 /**

   * @}

@@ -1078,14 +1078,24 @@ typedef struct
 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */

 

 /*!< PVD level configuration */

-#define PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)             /*!< PVD level 2.2V */

-#define PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)             /*!< PVD level 2.3V */

-#define PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)             /*!< PVD level 2.4V */

-#define PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)             /*!< PVD level 2.5V */

-#define PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)             /*!< PVD level 2.6V */

-#define PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)             /*!< PVD level 2.7V */

-#define PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)             /*!< PVD level 2.8V */

-#define PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)             /*!< PVD level 2.9V */

+#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */

+#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */

+#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */

+#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */

+#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */

+#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */

+#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */

+#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */

+

+/* Legacy defines */

+#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0

+#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1

+#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2

+#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3

+#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4

+#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5

+#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6

+#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7

 

 #define PWR_CR_DBP_Pos                      (8U)                               

 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */

@@ -1401,12 +1411,23 @@ typedef struct
 #define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */

 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< PLL clock ready flag */

 

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define RCC_PLL2_SUPPORT                                                       /*!< Support PLL2 */

+

 #define RCC_CR_PLL2ON_Pos                    (26U)                             

 #define RCC_CR_PLL2ON_Msk                    (0x1U << RCC_CR_PLL2ON_Pos)       /*!< 0x04000000 */

 #define RCC_CR_PLL2ON                        RCC_CR_PLL2ON_Msk                 /*!< PLL2 enable */

 #define RCC_CR_PLL2RDY_Pos                   (27U)                             

 #define RCC_CR_PLL2RDY_Msk                   (0x1U << RCC_CR_PLL2RDY_Pos)      /*!< 0x08000000 */

 #define RCC_CR_PLL2RDY                       RCC_CR_PLL2RDY_Msk                /*!< PLL2 clock ready flag */

+

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLL3 (PLLI2S)*/

+

 #define RCC_CR_PLL3ON_Pos                    (28U)                             

 #define RCC_CR_PLL3ON_Msk                    (0x1U << RCC_CR_PLL3ON_Pos)       /*!< 0x10000000 */

 #define RCC_CR_PLL3ON                        RCC_CR_PLL3ON_Msk                 /*!< PLL3 enable */

@@ -1422,9 +1443,9 @@ typedef struct
 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */

 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */

 

-#define RCC_CFGR_SW_HSI                      ((uint32_t)0x00000000)            /*!< HSI selected as system clock */

-#define RCC_CFGR_SW_HSE                      ((uint32_t)0x00000001)            /*!< HSE selected as system clock */

-#define RCC_CFGR_SW_PLL                      ((uint32_t)0x00000002)            /*!< PLL selected as system clock */

+#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */

+#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */

+#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */

 

 /*!< SWS configuration */

 #define RCC_CFGR_SWS_Pos                     (2U)                              

@@ -1433,9 +1454,9 @@ typedef struct
 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */

 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */

 

-#define RCC_CFGR_SWS_HSI                     ((uint32_t)0x00000000)            /*!< HSI oscillator used as system clock */

-#define RCC_CFGR_SWS_HSE                     ((uint32_t)0x00000004)            /*!< HSE oscillator used as system clock */

-#define RCC_CFGR_SWS_PLL                     ((uint32_t)0x00000008)            /*!< PLL used as system clock */

+#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */

+#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */

+#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */

 

 /*!< HPRE configuration */

 #define RCC_CFGR_HPRE_Pos                    (4U)                              

@@ -1446,15 +1467,15 @@ typedef struct
 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */

 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */

 

-#define RCC_CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)            /*!< SYSCLK not divided */

-#define RCC_CFGR_HPRE_DIV2                   ((uint32_t)0x00000080)            /*!< SYSCLK divided by 2 */

-#define RCC_CFGR_HPRE_DIV4                   ((uint32_t)0x00000090)            /*!< SYSCLK divided by 4 */

-#define RCC_CFGR_HPRE_DIV8                   ((uint32_t)0x000000A0)            /*!< SYSCLK divided by 8 */

-#define RCC_CFGR_HPRE_DIV16                  ((uint32_t)0x000000B0)            /*!< SYSCLK divided by 16 */

-#define RCC_CFGR_HPRE_DIV64                  ((uint32_t)0x000000C0)            /*!< SYSCLK divided by 64 */

-#define RCC_CFGR_HPRE_DIV128                 ((uint32_t)0x000000D0)            /*!< SYSCLK divided by 128 */

-#define RCC_CFGR_HPRE_DIV256                 ((uint32_t)0x000000E0)            /*!< SYSCLK divided by 256 */

-#define RCC_CFGR_HPRE_DIV512                 ((uint32_t)0x000000F0)            /*!< SYSCLK divided by 512 */

+#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */

+#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */

+#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */

+#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */

+#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */

+#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */

+#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */

+#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */

+#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */

 

 /*!< PPRE1 configuration */

 #define RCC_CFGR_PPRE1_Pos                   (8U)                              

@@ -1464,11 +1485,11 @@ typedef struct
 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */

 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */

 

-#define RCC_CFGR_PPRE1_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE1_DIV2                  ((uint32_t)0x00000400)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE1_DIV4                  ((uint32_t)0x00000500)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE1_DIV8                  ((uint32_t)0x00000600)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE1_DIV16                 ((uint32_t)0x00000700)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */

 

 /*!< PPRE2 configuration */

 #define RCC_CFGR_PPRE2_Pos                   (11U)                             

@@ -1478,11 +1499,11 @@ typedef struct
 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */

 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */

 

-#define RCC_CFGR_PPRE2_DIV1                  ((uint32_t)0x00000000)            /*!< HCLK not divided */

-#define RCC_CFGR_PPRE2_DIV2                  ((uint32_t)0x00002000)            /*!< HCLK divided by 2 */

-#define RCC_CFGR_PPRE2_DIV4                  ((uint32_t)0x00002800)            /*!< HCLK divided by 4 */

-#define RCC_CFGR_PPRE2_DIV8                  ((uint32_t)0x00003000)            /*!< HCLK divided by 8 */

-#define RCC_CFGR_PPRE2_DIV16                 ((uint32_t)0x00003800)            /*!< HCLK divided by 16 */

+#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */

+#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */

+#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */

+#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */

+#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */

 

 /*!< ADCPPRE configuration */

 #define RCC_CFGR_ADCPRE_Pos                  (14U)                             

@@ -1491,10 +1512,10 @@ typedef struct
 #define RCC_CFGR_ADCPRE_0                    (0x1U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */

 #define RCC_CFGR_ADCPRE_1                    (0x2U << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */

 

-#define RCC_CFGR_ADCPRE_DIV2                 ((uint32_t)0x00000000)            /*!< PCLK2 divided by 2 */

-#define RCC_CFGR_ADCPRE_DIV4                 ((uint32_t)0x00004000)            /*!< PCLK2 divided by 4 */

-#define RCC_CFGR_ADCPRE_DIV6                 ((uint32_t)0x00008000)            /*!< PCLK2 divided by 6 */

-#define RCC_CFGR_ADCPRE_DIV8                 ((uint32_t)0x0000C000)            /*!< PCLK2 divided by 8 */

+#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */

+#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */

+#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */

+#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */

 

 #define RCC_CFGR_PLLSRC_Pos                  (16U)                             

 #define RCC_CFGR_PLLSRC_Msk                  (0x1U << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */

@@ -1513,8 +1534,8 @@ typedef struct
 #define RCC_CFGR_PLLMULL_2                   (0x4U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */

 #define RCC_CFGR_PLLMULL_3                   (0x8U << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */

 

-#define RCC_CFGR_PLLXTPRE_PREDIV1            ((uint32_t)0x00000000)            /*!< PREDIV1 clock not divided for PLL entry */

-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       ((uint32_t)0x00020000)            /*!< PREDIV1 clock divided by 2 for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1            0x00000000U                       /*!< PREDIV1 clock not divided for PLL entry */

+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2       0x00020000U                       /*!< PREDIV1 clock divided by 2 for PLL entry */

 

 #define RCC_CFGR_PLLMULL4_Pos                (19U)                             

 #define RCC_CFGR_PLLMULL4_Msk                (0x1U << RCC_CFGR_PLLMULL4_Pos)   /*!< 0x00080000 */

@@ -1534,7 +1555,7 @@ typedef struct
 #define RCC_CFGR_PLLMULL9_Pos                (18U)                             

 #define RCC_CFGR_PLLMULL9_Msk                (0x7U << RCC_CFGR_PLLMULL9_Pos)   /*!< 0x001C0000 */

 #define RCC_CFGR_PLLMULL9                    RCC_CFGR_PLLMULL9_Msk             /*!< PLL input clock * 9 */

-#define RCC_CFGR_PLLMULL6_5                  ((uint32_t)0x00340000)            /*!< PLL input clock * 6.5 */

+#define RCC_CFGR_PLLMULL6_5                  0x00340000U                       /*!< PLL input clock * 6.5 */

  

 #define RCC_CFGR_OTGFSPRE_Pos                (22U)                             

 #define RCC_CFGR_OTGFSPRE_Msk                (0x1U << RCC_CFGR_OTGFSPRE_Pos)   /*!< 0x00400000 */

@@ -1549,15 +1570,15 @@ typedef struct
 #define RCC_CFGR_MCO_2                       (0x4U << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */

 #define RCC_CFGR_MCO_3                       (0x8U << RCC_CFGR_MCO_Pos)        /*!< 0x08000000 */

 

-#define RCC_CFGR_MCO_NOCLOCK                 ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_CFGR_MCO_SYSCLK                  ((uint32_t)0x04000000)            /*!< System clock selected as MCO source */

-#define RCC_CFGR_MCO_HSI                     ((uint32_t)0x05000000)            /*!< HSI clock selected as MCO source */

-#define RCC_CFGR_MCO_HSE                     ((uint32_t)0x06000000)            /*!< HSE clock selected as MCO source */

-#define RCC_CFGR_MCO_PLLCLK_DIV2             ((uint32_t)0x07000000)            /*!< PLL clock divided by 2 selected as MCO source */

-#define RCC_CFGR_MCO_PLL2CLK                 ((uint32_t)0x08000000)            /*!< PLL2 clock selected as MCO source*/

-#define RCC_CFGR_MCO_PLL3CLK_DIV2            ((uint32_t)0x09000000)            /*!< PLL3 clock divided by 2 selected as MCO source*/

-#define RCC_CFGR_MCO_EXT_HSE                 ((uint32_t)0x0A000000)            /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */

-#define RCC_CFGR_MCO_PLL3CLK                 ((uint32_t)0x0B000000)            /*!< PLL3 clock selected as MCO source */

+#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                       /*!< No clock */

+#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                       /*!< System clock selected as MCO source */

+#define RCC_CFGR_MCO_HSI                     0x05000000U                       /*!< HSI clock selected as MCO source */

+#define RCC_CFGR_MCO_HSE                     0x06000000U                       /*!< HSE clock selected as MCO source */

+#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                       /*!< PLL clock divided by 2 selected as MCO source */

+#define RCC_CFGR_MCO_PLL2CLK                 0x08000000U                       /*!< PLL2 clock selected as MCO source*/

+#define RCC_CFGR_MCO_PLL3CLK_DIV2            0x09000000U                       /*!< PLL3 clock divided by 2 selected as MCO source*/

+#define RCC_CFGR_MCO_EXT_HSE                 0x0A000000U                       /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */

+#define RCC_CFGR_MCO_PLL3CLK                 0x0B000000U                       /*!< PLL3 clock selected as MCO source */

 

  /* Reference defines */

  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO

@@ -1923,10 +1944,10 @@ typedef struct
 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */

 

 /*!< RTC congiguration */

-#define RCC_BDCR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)            /*!< No clock */

-#define RCC_BDCR_RTCSEL_LSE                  ((uint32_t)0x00000100)            /*!< LSE oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_LSI                  ((uint32_t)0x00000200)            /*!< LSI oscillator clock used as RTC clock */

-#define RCC_BDCR_RTCSEL_HSE                  ((uint32_t)0x00000300)            /*!< HSE oscillator clock divided by 128 used as RTC clock */

+#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */

+#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */

+#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */

 

 #define RCC_BDCR_RTCEN_Pos                   (15U)                             

 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */

@@ -1982,7 +2003,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV1_2                  (0x4U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000004 */

 #define RCC_CFGR2_PREDIV1_3                  (0x8U << RCC_CFGR2_PREDIV1_Pos)   /*!< 0x00000008 */

 

-#define RCC_CFGR2_PREDIV1_DIV1               ((uint32_t)0x00000000)            /*!< PREDIV1 input clock not divided */

+#define RCC_CFGR2_PREDIV1_DIV1               0x00000000U                       /*!< PREDIV1 input clock not divided */

 #define RCC_CFGR2_PREDIV1_DIV2_Pos           (0U)                              

 #define RCC_CFGR2_PREDIV1_DIV2_Msk           (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */

 #define RCC_CFGR2_PREDIV1_DIV2               RCC_CFGR2_PREDIV1_DIV2_Msk        /*!< PREDIV1 input clock divided by 2 */

@@ -2038,7 +2059,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV2_2                  (0x4U << RCC_CFGR2_PREDIV2_Pos)   /*!< 0x00000040 */

 #define RCC_CFGR2_PREDIV2_3                  (0x8U << RCC_CFGR2_PREDIV2_Pos)   /*!< 0x00000080 */

 

-#define RCC_CFGR2_PREDIV2_DIV1               ((uint32_t)0x00000000)            /*!< PREDIV2 input clock not divided */

+#define RCC_CFGR2_PREDIV2_DIV1               0x00000000U                       /*!< PREDIV2 input clock not divided */

 #define RCC_CFGR2_PREDIV2_DIV2_Pos           (4U)                              

 #define RCC_CFGR2_PREDIV2_DIV2_Msk           (0x1U << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */

 #define RCC_CFGR2_PREDIV2_DIV2               RCC_CFGR2_PREDIV2_DIV2_Msk        /*!< PREDIV2 input clock divided by 2 */

@@ -2165,7 +2186,7 @@ typedef struct
 #define RCC_CFGR2_PREDIV1SRC_PLL2_Pos        (16U)                             

 #define RCC_CFGR2_PREDIV1SRC_PLL2_Msk        (0x1U << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */

 #define RCC_CFGR2_PREDIV1SRC_PLL2            RCC_CFGR2_PREDIV1SRC_PLL2_Msk     /*!< PLL2 selected as PREDIV1 entry clock source */

-#define RCC_CFGR2_PREDIV1SRC_HSE             ((uint32_t)0x00000000)            /*!< HSE selected as PREDIV1 entry clock source */

+#define RCC_CFGR2_PREDIV1SRC_HSE             0x00000000U                       /*!< HSE selected as PREDIV1 entry clock source */

 #define RCC_CFGR2_I2S2SRC_Pos                (17U)                             

 #define RCC_CFGR2_I2S2SRC_Msk                (0x1U << RCC_CFGR2_I2S2SRC_Pos)   /*!< 0x00020000 */

 #define RCC_CFGR2_I2S2SRC                    RCC_CFGR2_I2S2SRC_Msk             /*!< I2S2 entry clock source */

@@ -2704,7 +2725,7 @@ typedef struct
 #define AFIO_EVCR_PIN_3                      (0x8U << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */

 

 /*!< PIN configuration */

-#define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)            /*!< Pin 0 selected */

+#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */

 #define AFIO_EVCR_PIN_PX1_Pos                (0U)                              

 #define AFIO_EVCR_PIN_PX1_Msk                (0x1U << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */

 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */

@@ -2759,7 +2780,7 @@ typedef struct
 #define AFIO_EVCR_PORT_2                     (0x4U << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */

 

 /*!< PORT configuration */

-#define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)            /*!< Port A selected */

+#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */

 #define AFIO_EVCR_PORT_PB_Pos                (4U)                              

 #define AFIO_EVCR_PORT_PB_Msk                (0x1U << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */

 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */

@@ -2798,7 +2819,7 @@ typedef struct
 #define AFIO_MAPR_USART3_REMAP_1             (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

 

 /* USART3_REMAP configuration */

-#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)            /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

+#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */

 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */

@@ -2813,7 +2834,7 @@ typedef struct
 #define AFIO_MAPR_TIM1_REMAP_1               (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

 

 /*!< TIM1_REMAP configuration */

-#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */

 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */

@@ -2828,7 +2849,7 @@ typedef struct
 #define AFIO_MAPR_TIM2_REMAP_1               (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

 

 /*!< TIM2_REMAP configuration */

-#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */

 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */

@@ -2846,7 +2867,7 @@ typedef struct
 #define AFIO_MAPR_TIM3_REMAP_1               (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

 

 /*!< TIM3_REMAP configuration */

-#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)            /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */

 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */

@@ -2865,7 +2886,7 @@ typedef struct
 #define AFIO_MAPR_CAN_REMAP_1                (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */

 

 /*!< CAN_REMAP configuration */

-#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)            /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

+#define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             

 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */

 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */

@@ -2888,7 +2909,7 @@ typedef struct
 #define AFIO_MAPR_SWJ_CFG_1                  (0x2U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */

 #define AFIO_MAPR_SWJ_CFG_2                  (0x4U << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */

 

-#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)            /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

+#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */

 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */

@@ -2944,7 +2965,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */

 

 /*!< EXTI0 configuration */

-#define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */

+#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */

 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              

 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */

@@ -2965,7 +2986,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */

 

 /*!< EXTI1 configuration */

-#define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */

+#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */

 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              

 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */

@@ -2986,7 +3007,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */

 

 /*!< EXTI2 configuration */  

-#define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */

+#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */

 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              

 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */

@@ -3007,7 +3028,7 @@ typedef struct
 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */

 

 /*!< EXTI3 configuration */

-#define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */

+#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */

 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             

 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */

@@ -3042,7 +3063,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */

 

 /*!< EXTI4 configuration */

-#define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */

+#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */

 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              

 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */

@@ -3063,7 +3084,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */

 

 /* EXTI5 configuration */

-#define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */

+#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */

 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              

 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */

@@ -3084,7 +3105,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */

 

 /*!< EXTI6 configuration */  

-#define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */

+#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */

 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              

 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */

@@ -3105,7 +3126,7 @@ typedef struct
 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */

 

 /*!< EXTI7 configuration */

-#define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */

+#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */

 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             

 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */

@@ -3140,7 +3161,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

 

 /*!< EXTI8 configuration */

-#define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */

+#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */

 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              

 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */

@@ -3161,7 +3182,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */

 

 /*!< EXTI9 configuration */

-#define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */

+#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */

 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              

 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */

@@ -3182,7 +3203,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */

 

 /*!< EXTI10 configuration */  

-#define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */

+#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */

 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              

 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */

@@ -3203,7 +3224,7 @@ typedef struct
 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */

 

 /*!< EXTI11 configuration */

-#define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */

+#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */

 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             

 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */

@@ -3238,7 +3259,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

 

 /* EXTI12 configuration */

-#define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */

+#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */

 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              

 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */

 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */

@@ -3259,7 +3280,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */

 

 /* EXTI13 configuration */

-#define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */

+#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */

 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              

 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */

 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */

@@ -3280,7 +3301,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */

 

 /*!< EXTI14 configuration */  

-#define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */

+#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */

 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              

 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */

 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */

@@ -3301,7 +3322,7 @@ typedef struct
 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */

 

 /*!< EXTI15 configuration */

-#define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */

+#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */

 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             

 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */

 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */

@@ -3327,440 +3348,6 @@ typedef struct
 

 /******************************************************************************/

 /*                                                                            */

-/*                               SystemTick                                   */

-/*                                                                            */

-/******************************************************************************/

-

-/*****************  Bit definition for SysTick_CTRL register  *****************/

-#define SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)             /*!< Counter enable */

-#define SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)             /*!< Counting down to 0 pends the SysTick handler */

-#define SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)             /*!< Clock source */

-#define SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)             /*!< Count Flag */

-

-/*****************  Bit definition for SysTick_LOAD register  *****************/

-#define SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)             /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */

-

-/*****************  Bit definition for SysTick_VAL register  ******************/

-#define SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)             /*!< Current value at the time the register is accessed */

-

-/*****************  Bit definition for SysTick_CALIB register  ****************/

-#define SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)             /*!< Reload value to use for 10ms timing */

-#define SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)             /*!< Calibration value is not exactly 10 ms */

-#define SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)             /*!< The reference clock is not provided */

-

-/******************************************************************************/

-/*                                                                            */

-/*                  Nested Vectored Interrupt Controller                      */

-/*                                                                            */

-/******************************************************************************/

-

-/******************  Bit definition for NVIC_ISER register  *******************/

-#define NVIC_ISER_SETENA_Pos                (0U)                               

-#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */

-#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */

-#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */

-#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */

-#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */

-#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */

-#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */

-#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */

-#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */

-#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */

-#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */

-#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */

-#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */

-#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */

-#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */

-#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */

-#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */

-#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */

-#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */

-#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */

-#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */

-#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */

-#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */

-#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */

-#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */

-#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */

-#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */

-#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */

-#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */

-#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */

-#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */

-#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */

-#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICER register  *******************/

-#define NVIC_ICER_CLRENA_Pos                (0U)                               

-#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */

-#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */

-#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */

-#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */

-#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */

-#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */

-#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */

-#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */

-#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */

-#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */

-#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */

-#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */

-#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */

-#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */

-#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */

-#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */

-#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */

-#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */

-#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */

-#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */

-#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */

-#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */

-#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */

-#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */

-#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */

-#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */

-#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */

-#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */

-#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */

-#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */

-#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */

-#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */

-#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ISPR register  *******************/

-#define NVIC_ISPR_SETPEND_Pos               (0U)                               

-#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */

-#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_ICPR register  *******************/

-#define NVIC_ICPR_CLRPEND_Pos               (0U)                               

-#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */

-#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */

-#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */

-#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */

-#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */

-#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */

-#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */

-#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */

-#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */

-#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */

-#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */

-#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */

-#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */

-#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */

-#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */

-#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */

-#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */

-#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */

-#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */

-#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */

-#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */

-#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */

-#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */

-#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */

-#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */

-#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */

-#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */

-#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */

-#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */

-#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */

-#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */

-#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */

-#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_IABR register  *******************/

-#define NVIC_IABR_ACTIVE_Pos                (0U)                               

-#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */

-#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */

-#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */

-#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */

-#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */

-#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */

-#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */

-#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */

-#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */

-#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */

-#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */

-#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */

-#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */

-#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */

-#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */

-#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */

-#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */

-#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */

-#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */

-#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */

-#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */

-#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */

-#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */

-#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */

-#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */

-#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */

-#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */

-#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */

-#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */

-#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */

-#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */

-#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */

-#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */

-#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */

-

-/******************  Bit definition for NVIC_PRI0 register  *******************/

-#define NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 0 */

-#define NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 1 */

-#define NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 2 */

-#define NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 3 */

-

-/******************  Bit definition for NVIC_PRI1 register  *******************/

-#define NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 4 */

-#define NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 5 */

-#define NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 6 */

-#define NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)             /*!< Priority of interrupt 7 */

-

-/******************  Bit definition for NVIC_PRI2 register  *******************/

-#define NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)             /*!< Priority of interrupt 8 */

-#define NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 9 */

-#define NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 10 */

-#define NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 11 */

-

-/******************  Bit definition for NVIC_PRI3 register  *******************/

-#define NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 12 */

-#define NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 13 */

-#define NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 14 */

-#define NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 15 */

-

-/******************  Bit definition for NVIC_PRI4 register  *******************/

-#define NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 16 */

-#define NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 17 */

-#define NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 18 */

-#define NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 19 */

-

-/******************  Bit definition for NVIC_PRI5 register  *******************/

-#define NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 20 */

-#define NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 21 */

-#define NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 22 */

-#define NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 23 */

-

-/******************  Bit definition for NVIC_PRI6 register  *******************/

-#define NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 24 */

-#define NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 25 */

-#define NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 26 */

-#define NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 27 */

-

-/******************  Bit definition for NVIC_PRI7 register  *******************/

-#define NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)             /*!< Priority of interrupt 28 */

-#define NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)             /*!< Priority of interrupt 29 */

-#define NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)             /*!< Priority of interrupt 30 */

-#define NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)             /*!< Priority of interrupt 31 */

-

-/******************  Bit definition for SCB_CPUID register  *******************/

-#define SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)             /*!< Implementation defined revision number */

-#define SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)             /*!< Number of processor within family */

-#define SCB_CPUID_Constant                  ((uint32_t)0x000F0000)             /*!< Reads as 0x0F */

-#define SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)             /*!< Implementation defined variant number */

-#define SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)             /*!< Implementer code. ARM is 0x41 */

-

-/*******************  Bit definition for SCB_ICSR register  *******************/

-#define SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)             /*!< Active ISR number field */

-#define SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)             /*!< All active exceptions minus the IPSR_current_exception yields the empty set */

-#define SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)             /*!< Pending ISR number field */

-#define SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)             /*!< Interrupt pending flag */

-#define SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)             /*!< It indicates that a pending interrupt becomes active in the next running cycle */

-#define SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)             /*!< Clear pending SysTick bit */

-#define SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)             /*!< Set pending SysTick bit */

-#define SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)             /*!< Clear pending pendSV bit */

-#define SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)             /*!< Set pending pendSV bit */

-#define SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)             /*!< Set pending NMI bit */

-

-/*******************  Bit definition for SCB_VTOR register  *******************/

-#define SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)             /*!< Vector table base offset field */

-#define SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)             /*!< Table base in code(0) or RAM(1) */

-

-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/

-#define SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)             /*!< System Reset bit */

-#define SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)             /*!< Clear active vector bit */

-#define SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)             /*!< Requests chip control logic to generate a reset */

-

-#define SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)             /*!< PRIGROUP[2:0] bits (Priority group) */

-#define SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)             /*!< Bit 0 */

-#define SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)             /*!< Bit 1 */

-#define SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)             /*!< Bit 2  */

-

-/* prority group configuration */

-#define SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)             /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */

-#define SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)             /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)             /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)             /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)             /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)             /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)             /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */

-#define SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)             /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */

-

-#define SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)             /*!< Data endianness bit */

-#define SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)             /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */

-

-/*******************  Bit definition for SCB_SCR register  ********************/

-#define SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)             /*!< Sleep on exit bit */

-#define SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)             /*!< Sleep deep bit */

-#define SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)             /*!< Wake up from WFE */

-

-/********************  Bit definition for SCB_CCR register  *******************/

-#define SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)             /*!< Thread mode can be entered from any level in Handler mode by controlled return value */

-#define SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)             /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */

-#define SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)             /*!< Trap for unaligned access */

-#define SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)             /*!< Trap on Divide by 0 */

-#define SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)             /*!< Handlers running at priority -1 and -2 */

-#define SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)             /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */

-

-/*******************  Bit definition for SCB_SHPR register ********************/

-#define SCB_SHPR_PRI_N_Pos                  (0U)                               

-#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */

-#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */

-#define SCB_SHPR_PRI_N1_Pos                 (8U)                               

-#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */

-#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */

-#define SCB_SHPR_PRI_N2_Pos                 (16U)                              

-#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */

-#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */

-#define SCB_SHPR_PRI_N3_Pos                 (24U)                              

-#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */

-#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */

-

-/******************  Bit definition for SCB_SHCSR register  *******************/

-#define SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)             /*!< MemManage is active */

-#define SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)             /*!< BusFault is active */

-#define SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)             /*!< UsageFault is active */

-#define SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)             /*!< SVCall is active */

-#define SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)             /*!< Monitor is active */

-#define SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)             /*!< PendSV is active */

-#define SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)             /*!< SysTick is active */

-#define SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)             /*!< Usage Fault is pended */

-#define SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)             /*!< MemManage is pended */

-#define SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)             /*!< Bus Fault is pended */

-#define SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)             /*!< SVCall is pended */

-#define SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)             /*!< MemManage enable */

-#define SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)             /*!< Bus Fault enable */

-#define SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)             /*!< UsageFault enable */

-

-/*******************  Bit definition for SCB_CFSR register  *******************/

-/*!< MFSR */

-#define SCB_CFSR_IACCVIOL_Pos               (0U)                               

-#define SCB_CFSR_IACCVIOL_Msk               (0x1U << SCB_CFSR_IACCVIOL_Pos)    /*!< 0x00000001 */

-#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */

-#define SCB_CFSR_DACCVIOL_Pos               (1U)                               

-#define SCB_CFSR_DACCVIOL_Msk               (0x1U << SCB_CFSR_DACCVIOL_Pos)    /*!< 0x00000002 */

-#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */

-#define SCB_CFSR_MUNSTKERR_Pos              (3U)                               

-#define SCB_CFSR_MUNSTKERR_Msk              (0x1U << SCB_CFSR_MUNSTKERR_Pos)   /*!< 0x00000008 */

-#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */

-#define SCB_CFSR_MSTKERR_Pos                (4U)                               

-#define SCB_CFSR_MSTKERR_Msk                (0x1U << SCB_CFSR_MSTKERR_Pos)     /*!< 0x00000010 */

-#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */

-#define SCB_CFSR_MMARVALID_Pos              (7U)                               

-#define SCB_CFSR_MMARVALID_Msk              (0x1U << SCB_CFSR_MMARVALID_Pos)   /*!< 0x00000080 */

-#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */

-/*!< BFSR */

-#define SCB_CFSR_IBUSERR_Pos                (8U)                               

-#define SCB_CFSR_IBUSERR_Msk                (0x1U << SCB_CFSR_IBUSERR_Pos)     /*!< 0x00000100 */

-#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */

-#define SCB_CFSR_PRECISERR_Pos              (9U)                               

-#define SCB_CFSR_PRECISERR_Msk              (0x1U << SCB_CFSR_PRECISERR_Pos)   /*!< 0x00000200 */

-#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */

-#define SCB_CFSR_IMPRECISERR_Pos            (10U)                              

-#define SCB_CFSR_IMPRECISERR_Msk            (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */

-#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */

-#define SCB_CFSR_UNSTKERR_Pos               (11U)                              

-#define SCB_CFSR_UNSTKERR_Msk               (0x1U << SCB_CFSR_UNSTKERR_Pos)    /*!< 0x00000800 */

-#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */

-#define SCB_CFSR_STKERR_Pos                 (12U)                              

-#define SCB_CFSR_STKERR_Msk                 (0x1U << SCB_CFSR_STKERR_Pos)      /*!< 0x00001000 */

-#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */

-#define SCB_CFSR_BFARVALID_Pos              (15U)                              

-#define SCB_CFSR_BFARVALID_Msk              (0x1U << SCB_CFSR_BFARVALID_Pos)   /*!< 0x00008000 */

-#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */

-/*!< UFSR */

-#define SCB_CFSR_UNDEFINSTR_Pos             (16U)                              

-#define SCB_CFSR_UNDEFINSTR_Msk             (0x1U << SCB_CFSR_UNDEFINSTR_Pos)  /*!< 0x00010000 */

-#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to execute an undefined instruction */

-#define SCB_CFSR_INVSTATE_Pos               (17U)                              

-#define SCB_CFSR_INVSTATE_Msk               (0x1U << SCB_CFSR_INVSTATE_Pos)    /*!< 0x00020000 */

-#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */

-#define SCB_CFSR_INVPC_Pos                  (18U)                              

-#define SCB_CFSR_INVPC_Msk                  (0x1U << SCB_CFSR_INVPC_Pos)       /*!< 0x00040000 */

-#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */

-#define SCB_CFSR_NOCP_Pos                   (19U)                              

-#define SCB_CFSR_NOCP_Msk                   (0x1U << SCB_CFSR_NOCP_Pos)        /*!< 0x00080000 */

-#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */

-#define SCB_CFSR_UNALIGNED_Pos              (24U)                              

-#define SCB_CFSR_UNALIGNED_Msk              (0x1U << SCB_CFSR_UNALIGNED_Pos)   /*!< 0x01000000 */

-#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */

-#define SCB_CFSR_DIVBYZERO_Pos              (25U)                              

-#define SCB_CFSR_DIVBYZERO_Msk              (0x1U << SCB_CFSR_DIVBYZERO_Pos)   /*!< 0x02000000 */

-#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */

-

-/*******************  Bit definition for SCB_HFSR register  *******************/

-#define SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)             /*!< Fault occurs because of vector table read on exception processing */

-#define SCB_HFSR_FORCED                     ((uint32_t)0x40000000)             /*!< Hard Fault activated when a configurable Fault was received and cannot activate */

-#define SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)             /*!< Fault related to debug */

-

-/*******************  Bit definition for SCB_DFSR register  *******************/

-#define SCB_DFSR_HALTED                     ((uint32_t)0x00000001)             /*!< Halt request flag */

-#define SCB_DFSR_BKPT                       ((uint32_t)0x00000002)             /*!< BKPT flag */

-#define SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)             /*!< Data Watchpoint and Trace (DWT) flag */

-#define SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)             /*!< Vector catch flag */

-#define SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)             /*!< External debug request flag */

-

-/*******************  Bit definition for SCB_MMFAR register  ******************/

-#define SCB_MMFAR_ADDRESS_Pos               (0U)                               

-#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */

-

-/*******************  Bit definition for SCB_BFAR register  *******************/

-#define SCB_BFAR_ADDRESS_Pos                (0U)                               

-#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

-#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */

-

-/*******************  Bit definition for SCB_afsr register  *******************/

-#define SCB_AFSR_IMPDEF_Pos                 (0U)                               

-#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */

-#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */

-

-/******************************************************************************/

-/*                                                                            */

 /*                    External Interrupt/Event Controller                     */

 /*                                                                            */

 /******************************************************************************/

@@ -3848,7 +3435,8 @@ typedef struct
 #define  EXTI_IMR_IM17 EXTI_IMR_MR17

 #define  EXTI_IMR_IM18 EXTI_IMR_MR18

 #define  EXTI_IMR_IM19 EXTI_IMR_MR19

-

+#define  EXTI_IMR_IM   0x000FFFFFU        /*!< Interrupt Mask All */

+ 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define EXTI_EMR_MR0_Pos                    (0U)                               

 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */

@@ -5277,10 +4865,6 @@ typedef struct
 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */

 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */

 

-#define TIM_SMCR_OCCS_Pos                   (3U)                               

-#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */

-#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */

-

 #define TIM_SMCR_TS_Pos                     (4U)                               

 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */

 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */

@@ -5625,9 +5209,6 @@ typedef struct
 #define TIM_CCER_CC4P_Pos                   (13U)                              

 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */

 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */

-#define TIM_CCER_CC4NP_Pos                  (15U)                              

-#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */

-#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */

 

 /*******************  Bit definition for TIM_CNT register  *******************/

 #define TIM_CNT_CNT_Pos                     (0U)                               

@@ -5731,8 +5312,6 @@ typedef struct
 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */

 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */

 

-/*******************  Bit definition for TIM_OR register  ********************/

-

 /******************************************************************************/

 /*                                                                            */

 /*                             Real-Time Clock                                */

@@ -12675,7 +12254,11 @@ typedef struct
 /*                        Serial Peripheral Interface                         */

 /*                                                                            */

 /******************************************************************************/

-

+/*

+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)

+ */

+#define SPI_I2S_SUPPORT       /*!< I2S support */

+#define I2S2_I2S3_CLOCK_FEATURE

 /*******************  Bit definition for SPI_CR1 register  ********************/

 #define SPI_CR1_CPHA_Pos                    (0U)                               

 #define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */

@@ -12918,8 +12501,8 @@ typedef struct
 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */

 

 /*******************  Bit definition for I2C_OAR1 register  *******************/

-#define I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)             /*!< Interface Address */

-#define I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)             /*!< Interface Address */

+#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */

+#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */

 

 #define I2C_OAR1_ADD0_Pos                   (0U)                               

 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */

@@ -12964,6 +12547,11 @@ typedef struct
 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */

 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */

 

+/********************  Bit definition for I2C_DR register  ********************/

+#define I2C_DR_DR_Pos             (0U)                                         

+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */

+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */

+

 /*******************  Bit definition for I2C_SR1 register  ********************/

 #define I2C_SR1_SB_Pos                      (0U)                               

 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */

@@ -13538,14 +13126,14 @@ typedef struct
 #define ETH_MACCR_IFG_Pos                      (17U)                           

 #define ETH_MACCR_IFG_Msk                      (0x7U << ETH_MACCR_IFG_Pos)     /*!< 0x000E0000 */

 #define ETH_MACCR_IFG                          ETH_MACCR_IFG_Msk               /* Inter-frame gap */

-#define ETH_MACCR_IFG_96Bit                    ((uint32_t)0x00000000)          /* Minimum IFG between frames during transmission is 96Bit */

-#define ETH_MACCR_IFG_88Bit                    ((uint32_t)0x00020000)          /* Minimum IFG between frames during transmission is 88Bit */

-#define ETH_MACCR_IFG_80Bit                    ((uint32_t)0x00040000)          /* Minimum IFG between frames during transmission is 80Bit */

-#define ETH_MACCR_IFG_72Bit                    ((uint32_t)0x00060000)          /* Minimum IFG between frames during transmission is 72Bit */

-#define ETH_MACCR_IFG_64Bit                    ((uint32_t)0x00080000)          /* Minimum IFG between frames during transmission is 64Bit */        

-#define ETH_MACCR_IFG_56Bit                    ((uint32_t)0x000A0000)          /* Minimum IFG between frames during transmission is 56Bit */

-#define ETH_MACCR_IFG_48Bit                    ((uint32_t)0x000C0000)          /* Minimum IFG between frames during transmission is 48Bit */

-#define ETH_MACCR_IFG_40Bit                    ((uint32_t)0x000E0000)          /* Minimum IFG between frames during transmission is 40Bit */              

+#define ETH_MACCR_IFG_96Bit                    0x00000000U                     /* Minimum IFG between frames during transmission is 96Bit */

+#define ETH_MACCR_IFG_88Bit                    0x00020000U                     /* Minimum IFG between frames during transmission is 88Bit */

+#define ETH_MACCR_IFG_80Bit                    0x00040000U                     /* Minimum IFG between frames during transmission is 80Bit */

+#define ETH_MACCR_IFG_72Bit                    0x00060000U                     /* Minimum IFG between frames during transmission is 72Bit */

+#define ETH_MACCR_IFG_64Bit                    0x00080000U                     /* Minimum IFG between frames during transmission is 64Bit */        

+#define ETH_MACCR_IFG_56Bit                    0x000A0000U                     /* Minimum IFG between frames during transmission is 56Bit */

+#define ETH_MACCR_IFG_48Bit                    0x000C0000U                     /* Minimum IFG between frames during transmission is 48Bit */

+#define ETH_MACCR_IFG_40Bit                    0x000E0000U                     /* Minimum IFG between frames during transmission is 40Bit */              

 #define ETH_MACCR_CSD_Pos                      (16U)                           

 #define ETH_MACCR_CSD_Msk                      (0x1U << ETH_MACCR_CSD_Pos)     /*!< 0x00010000 */

 #define ETH_MACCR_CSD                          ETH_MACCR_CSD_Msk               /* Carrier sense disable (during transmission) */

@@ -13574,10 +13162,10 @@ typedef struct
 #define ETH_MACCR_BL_Msk                       (0x3U << ETH_MACCR_BL_Pos)      /*!< 0x00000060 */

 #define ETH_MACCR_BL                           ETH_MACCR_BL_Msk                /* Back-off limit: random integer number (r) of slot time delays before rescheduling

                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */

-#define ETH_MACCR_BL_10                        ((uint32_t)0x00000000)          /* k = min (n, 10) */

-#define ETH_MACCR_BL_8                         ((uint32_t)0x00000020)          /* k = min (n, 8) */

-#define ETH_MACCR_BL_4                         ((uint32_t)0x00000040)          /* k = min (n, 4) */

-#define ETH_MACCR_BL_1                         ((uint32_t)0x00000060)          /* k = min (n, 1) */ 

+#define ETH_MACCR_BL_10                        0x00000000U                     /* k = min (n, 10) */

+#define ETH_MACCR_BL_8                         0x00000020U                     /* k = min (n, 8) */

+#define ETH_MACCR_BL_4                         0x00000040U                     /* k = min (n, 4) */

+#define ETH_MACCR_BL_1                         0x00000060U                     /* k = min (n, 1) */ 

 #define ETH_MACCR_DC_Pos                       (4U)                            

 #define ETH_MACCR_DC_Msk                       (0x1U << ETH_MACCR_DC_Pos)      /*!< 0x00000010 */

 #define ETH_MACCR_DC                           ETH_MACCR_DC_Msk                /* Defferal check */

@@ -13652,7 +13240,7 @@ typedef struct
 #define ETH_MACMIIAR_CR_Pos                    (2U)                            

 #define ETH_MACMIIAR_CR_Msk                    (0x7U << ETH_MACMIIAR_CR_Pos)   /*!< 0x0000001C */

 #define ETH_MACMIIAR_CR                        ETH_MACMIIAR_CR_Msk             /* CR clock range: 6 cases */ 

-#define ETH_MACMIIAR_CR_DIV42                  ((uint32_t)0x00000000)          /* HCLK:60-72 MHz; MDC clock= HCLK/42 */

+#define ETH_MACMIIAR_CR_DIV42                  0x00000000U                     /* HCLK:60-72 MHz; MDC clock= HCLK/42 */

 #define ETH_MACMIIAR_CR_DIV16_Pos              (3U)                            

 #define ETH_MACMIIAR_CR_DIV16_Msk              (0x1U << ETH_MACMIIAR_CR_DIV16_Pos) /*!< 0x00000008 */

 #define ETH_MACMIIAR_CR_DIV16                  ETH_MACMIIAR_CR_DIV16_Msk       /* HCLK:20-35 MHz; MDC clock= HCLK/16 */

@@ -13681,7 +13269,7 @@ typedef struct
 #define ETH_MACFCR_PLT_Pos                     (4U)                            

 #define ETH_MACFCR_PLT_Msk                     (0x3U << ETH_MACFCR_PLT_Pos)    /*!< 0x00000030 */

 #define ETH_MACFCR_PLT                         ETH_MACFCR_PLT_Msk              /* Pause low threshold: 4 cases */

-#define ETH_MACFCR_PLT_Minus4                  ((uint32_t)0x00000000)          /* Pause time minus 4 slot times */

+#define ETH_MACFCR_PLT_Minus4                  0x00000000U                     /* Pause time minus 4 slot times */

 #define ETH_MACFCR_PLT_Minus28_Pos             (4U)                            

 #define ETH_MACFCR_PLT_Minus28_Msk             (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */

 #define ETH_MACFCR_PLT_Minus28                 ETH_MACFCR_PLT_Minus28_Msk      /* Pause time minus 28 slot times */

@@ -13796,12 +13384,12 @@ typedef struct
 #define ETH_MACA1HR_MBC_Pos                    (24U)                           

 #define ETH_MACA1HR_MBC_Msk                    (0x3FU << ETH_MACA1HR_MBC_Pos)  /*!< 0x3F000000 */

 #define ETH_MACA1HR_MBC                        ETH_MACA1HR_MBC_Msk             /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

-#define ETH_MACA1HR_MBC_HBits15_8              ((uint32_t)0x20000000)          /* Mask MAC Address high reg bits [15:8] */

-#define ETH_MACA1HR_MBC_HBits7_0               ((uint32_t)0x10000000)          /* Mask MAC Address high reg bits [7:0] */

-#define ETH_MACA1HR_MBC_LBits31_24             ((uint32_t)0x08000000)          /* Mask MAC Address low reg bits [31:24] */

-#define ETH_MACA1HR_MBC_LBits23_16             ((uint32_t)0x04000000)          /* Mask MAC Address low reg bits [23:16] */

-#define ETH_MACA1HR_MBC_LBits15_8              ((uint32_t)0x02000000)          /* Mask MAC Address low reg bits [15:8] */

-#define ETH_MACA1HR_MBC_LBits7_0               ((uint32_t)0x01000000)          /* Mask MAC Address low reg bits [7:0] */ 

+#define ETH_MACA1HR_MBC_HBits15_8              0x20000000U                     /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACA1HR_MBC_HBits7_0               0x10000000U                     /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACA1HR_MBC_LBits31_24             0x08000000U                     /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACA1HR_MBC_LBits23_16             0x04000000U                     /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACA1HR_MBC_LBits15_8              0x02000000U                     /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACA1HR_MBC_LBits7_0               0x01000000U                     /* Mask MAC Address low reg bits [7:0] */ 

 #define ETH_MACA1HR_MACA1H_Pos                 (0U)                            

 #define ETH_MACA1HR_MACA1H_Msk                 (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */

 #define ETH_MACA1HR_MACA1H                     ETH_MACA1HR_MACA1H_Msk          /* MAC address1 high */

@@ -13821,12 +13409,12 @@ typedef struct
 #define ETH_MACA2HR_MBC_Pos                    (24U)                           

 #define ETH_MACA2HR_MBC_Msk                    (0x3FU << ETH_MACA2HR_MBC_Pos)  /*!< 0x3F000000 */

 #define ETH_MACA2HR_MBC                        ETH_MACA2HR_MBC_Msk             /* Mask byte control */

-#define ETH_MACA2HR_MBC_HBits15_8              ((uint32_t)0x20000000)          /* Mask MAC Address high reg bits [15:8] */

-#define ETH_MACA2HR_MBC_HBits7_0               ((uint32_t)0x10000000)          /* Mask MAC Address high reg bits [7:0] */

-#define ETH_MACA2HR_MBC_LBits31_24             ((uint32_t)0x08000000)          /* Mask MAC Address low reg bits [31:24] */

-#define ETH_MACA2HR_MBC_LBits23_16             ((uint32_t)0x04000000)          /* Mask MAC Address low reg bits [23:16] */

-#define ETH_MACA2HR_MBC_LBits15_8              ((uint32_t)0x02000000)          /* Mask MAC Address low reg bits [15:8] */

-#define ETH_MACA2HR_MBC_LBits7_0               ((uint32_t)0x01000000)          /* Mask MAC Address low reg bits [70] */

+#define ETH_MACA2HR_MBC_HBits15_8              0x20000000U                     /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACA2HR_MBC_HBits7_0               0x10000000U                     /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACA2HR_MBC_LBits31_24             0x08000000U                     /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACA2HR_MBC_LBits23_16             0x04000000U                     /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACA2HR_MBC_LBits15_8              0x02000000U                     /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACA2HR_MBC_LBits7_0               0x01000000U                     /* Mask MAC Address low reg bits [70] */

 #define ETH_MACA2HR_MACA2H_Pos                 (0U)                            

 #define ETH_MACA2HR_MACA2H_Msk                 (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */

 #define ETH_MACA2HR_MACA2H                     ETH_MACA2HR_MACA2H_Msk          /* MAC address1 high */

@@ -13846,12 +13434,12 @@ typedef struct
 #define ETH_MACA3HR_MBC_Pos                    (24U)                           

 #define ETH_MACA3HR_MBC_Msk                    (0x3FU << ETH_MACA3HR_MBC_Pos)  /*!< 0x3F000000 */

 #define ETH_MACA3HR_MBC                        ETH_MACA3HR_MBC_Msk             /* Mask byte control */

-#define ETH_MACA3HR_MBC_HBits15_8              ((uint32_t)0x20000000)          /* Mask MAC Address high reg bits [15:8] */

-#define ETH_MACA3HR_MBC_HBits7_0               ((uint32_t)0x10000000)          /* Mask MAC Address high reg bits [7:0] */

-#define ETH_MACA3HR_MBC_LBits31_24             ((uint32_t)0x08000000)          /* Mask MAC Address low reg bits [31:24] */

-#define ETH_MACA3HR_MBC_LBits23_16             ((uint32_t)0x04000000)          /* Mask MAC Address low reg bits [23:16] */

-#define ETH_MACA3HR_MBC_LBits15_8              ((uint32_t)0x02000000)          /* Mask MAC Address low reg bits [15:8] */

-#define ETH_MACA3HR_MBC_LBits7_0               ((uint32_t)0x01000000)          /* Mask MAC Address low reg bits [70] */

+#define ETH_MACA3HR_MBC_HBits15_8              0x20000000U                     /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACA3HR_MBC_HBits7_0               0x10000000U                     /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACA3HR_MBC_LBits31_24             0x08000000U                     /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACA3HR_MBC_LBits23_16             0x04000000U                     /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACA3HR_MBC_LBits15_8              0x02000000U                     /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACA3HR_MBC_LBits7_0               0x01000000U                     /* Mask MAC Address low reg bits [70] */

 #define ETH_MACA3HR_MACA3H_Pos                 (0U)                            

 #define ETH_MACA3HR_MACA3H_Msk                 (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */

 #define ETH_MACA3HR_MACA3H                     ETH_MACA3HR_MACA3H_Msk          /* MAC address3 high */

@@ -14040,43 +13628,43 @@ typedef struct
 #define ETH_DMABMR_RDP_Pos                     (17U)                           

 #define ETH_DMABMR_RDP_Msk                     (0x3FU << ETH_DMABMR_RDP_Pos)   /*!< 0x007E0000 */

 #define ETH_DMABMR_RDP                         ETH_DMABMR_RDP_Msk              /* RxDMA PBL */

-#define ETH_DMABMR_RDP_1Beat                   ((uint32_t)0x00020000)          /* maximum number of beats to be transferred in one RxDMA transaction is 1 */

-#define ETH_DMABMR_RDP_2Beat                   ((uint32_t)0x00040000)          /* maximum number of beats to be transferred in one RxDMA transaction is 2 */

-#define ETH_DMABMR_RDP_4Beat                   ((uint32_t)0x00080000)          /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

-#define ETH_DMABMR_RDP_8Beat                   ((uint32_t)0x00100000)          /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

-#define ETH_DMABMR_RDP_16Beat                  ((uint32_t)0x00200000)          /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

-#define ETH_DMABMR_RDP_32Beat                  ((uint32_t)0x00400000)          /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                

-#define ETH_DMABMR_RDP_4xPBL_4Beat             ((uint32_t)0x01020000)          /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

-#define ETH_DMABMR_RDP_4xPBL_8Beat             ((uint32_t)0x01040000)          /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

-#define ETH_DMABMR_RDP_4xPBL_16Beat            ((uint32_t)0x01080000)          /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

-#define ETH_DMABMR_RDP_4xPBL_32Beat            ((uint32_t)0x01100000)          /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

-#define ETH_DMABMR_RDP_4xPBL_64Beat            ((uint32_t)0x01200000)          /* maximum number of beats to be transferred in one RxDMA transaction is 64 */

-#define ETH_DMABMR_RDP_4xPBL_128Beat           ((uint32_t)0x01400000)          /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  

+#define ETH_DMABMR_RDP_1Beat                   0x00020000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 1 */

+#define ETH_DMABMR_RDP_2Beat                   0x00040000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 2 */

+#define ETH_DMABMR_RDP_4Beat                   0x00080000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

+#define ETH_DMABMR_RDP_8Beat                   0x00100000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

+#define ETH_DMABMR_RDP_16Beat                  0x00200000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

+#define ETH_DMABMR_RDP_32Beat                  0x00400000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                

+#define ETH_DMABMR_RDP_4xPBL_4Beat             0x01020000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

+#define ETH_DMABMR_RDP_4xPBL_8Beat             0x01040000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

+#define ETH_DMABMR_RDP_4xPBL_16Beat            0x01080000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

+#define ETH_DMABMR_RDP_4xPBL_32Beat            0x01100000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

+#define ETH_DMABMR_RDP_4xPBL_64Beat            0x01200000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 64 */

+#define ETH_DMABMR_RDP_4xPBL_128Beat           0x01400000U                     /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  

 #define ETH_DMABMR_FB_Pos                      (16U)                           

 #define ETH_DMABMR_FB_Msk                      (0x1U << ETH_DMABMR_FB_Pos)     /*!< 0x00010000 */

 #define ETH_DMABMR_FB                          ETH_DMABMR_FB_Msk               /* Fixed Burst */

 #define ETH_DMABMR_RTPR_Pos                    (14U)                           

 #define ETH_DMABMR_RTPR_Msk                    (0x3U << ETH_DMABMR_RTPR_Pos)   /*!< 0x0000C000 */

 #define ETH_DMABMR_RTPR                        ETH_DMABMR_RTPR_Msk             /* Rx Tx priority ratio */

-#define ETH_DMABMR_RTPR_1_1                    ((uint32_t)0x00000000)          /* Rx Tx priority ratio */

-#define ETH_DMABMR_RTPR_2_1                    ((uint32_t)0x00004000)          /* Rx Tx priority ratio */

-#define ETH_DMABMR_RTPR_3_1                    ((uint32_t)0x00008000)          /* Rx Tx priority ratio */

-#define ETH_DMABMR_RTPR_4_1                    ((uint32_t)0x0000C000)          /* Rx Tx priority ratio */  

+#define ETH_DMABMR_RTPR_1_1                    0x00000000U                     /* Rx Tx priority ratio */

+#define ETH_DMABMR_RTPR_2_1                    0x00004000U                     /* Rx Tx priority ratio */

+#define ETH_DMABMR_RTPR_3_1                    0x00008000U                     /* Rx Tx priority ratio */

+#define ETH_DMABMR_RTPR_4_1                    0x0000C000U                     /* Rx Tx priority ratio */  

 #define ETH_DMABMR_PBL_Pos                     (8U)                            

 #define ETH_DMABMR_PBL_Msk                     (0x3FU << ETH_DMABMR_PBL_Pos)   /*!< 0x00003F00 */

 #define ETH_DMABMR_PBL                         ETH_DMABMR_PBL_Msk              /* Programmable burst length */

-#define ETH_DMABMR_PBL_1Beat                   ((uint32_t)0x00000100)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */

-#define ETH_DMABMR_PBL_2Beat                   ((uint32_t)0x00000200)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */

-#define ETH_DMABMR_PBL_4Beat                   ((uint32_t)0x00000400)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

-#define ETH_DMABMR_PBL_8Beat                   ((uint32_t)0x00000800)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

-#define ETH_DMABMR_PBL_16Beat                  ((uint32_t)0x00001000)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

-#define ETH_DMABMR_PBL_32Beat                  ((uint32_t)0x00002000)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                

-#define ETH_DMABMR_PBL_4xPBL_4Beat             ((uint32_t)0x01000100)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

-#define ETH_DMABMR_PBL_4xPBL_8Beat             ((uint32_t)0x01000200)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

-#define ETH_DMABMR_PBL_4xPBL_16Beat            ((uint32_t)0x01000400)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

-#define ETH_DMABMR_PBL_4xPBL_32Beat            ((uint32_t)0x01000800)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

-#define ETH_DMABMR_PBL_4xPBL_64Beat            ((uint32_t)0x01001000)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */

-#define ETH_DMABMR_PBL_4xPBL_128Beat           ((uint32_t)0x01002000)          /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */

+#define ETH_DMABMR_PBL_1Beat                   0x00000100U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */

+#define ETH_DMABMR_PBL_2Beat                   0x00000200U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */

+#define ETH_DMABMR_PBL_4Beat                   0x00000400U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

+#define ETH_DMABMR_PBL_8Beat                   0x00000800U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

+#define ETH_DMABMR_PBL_16Beat                  0x00001000U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

+#define ETH_DMABMR_PBL_32Beat                  0x00002000U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                

+#define ETH_DMABMR_PBL_4xPBL_4Beat             0x01000100U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

+#define ETH_DMABMR_PBL_4xPBL_8Beat             0x01000200U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

+#define ETH_DMABMR_PBL_4xPBL_16Beat            0x01000400U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

+#define ETH_DMABMR_PBL_4xPBL_32Beat            0x01000800U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

+#define ETH_DMABMR_PBL_4xPBL_64Beat            0x01001000U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */

+#define ETH_DMABMR_PBL_4xPBL_128Beat           0x01002000U                     /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */

 #define ETH_DMABMR_DSL_Pos                     (2U)                            

 #define ETH_DMABMR_DSL_Msk                     (0x1FU << ETH_DMABMR_DSL_Pos)   /*!< 0x0000007C */

 #define ETH_DMABMR_DSL                         ETH_DMABMR_DSL_Msk              /* Descriptor Skip Length */

@@ -14133,7 +13721,7 @@ typedef struct
 #define ETH_DMASR_TPS_Pos                      (20U)                           

 #define ETH_DMASR_TPS_Msk                      (0x7U << ETH_DMASR_TPS_Pos)     /*!< 0x00700000 */

 #define ETH_DMASR_TPS                          ETH_DMASR_TPS_Msk               /* Transmit process state */

-#define ETH_DMASR_TPS_Stopped                  ((uint32_t)0x00000000)          /* Stopped - Reset or Stop Tx Command issued  */

+#define ETH_DMASR_TPS_Stopped                  0x00000000U                     /* Stopped - Reset or Stop Tx Command issued  */

 #define ETH_DMASR_TPS_Fetching_Pos             (20U)                           

 #define ETH_DMASR_TPS_Fetching_Msk             (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */

 #define ETH_DMASR_TPS_Fetching                 ETH_DMASR_TPS_Fetching_Msk      /* Running - fetching the Tx descriptor */

@@ -14152,7 +13740,7 @@ typedef struct
 #define ETH_DMASR_RPS_Pos                      (17U)                           

 #define ETH_DMASR_RPS_Msk                      (0x7U << ETH_DMASR_RPS_Pos)     /*!< 0x000E0000 */

 #define ETH_DMASR_RPS                          ETH_DMASR_RPS_Msk               /* Receive process state */

-#define ETH_DMASR_RPS_Stopped                  ((uint32_t)0x00000000)          /* Stopped - Reset or Stop Rx Command issued */

+#define ETH_DMASR_RPS_Stopped                  0x00000000U                     /* Stopped - Reset or Stop Rx Command issued */

 #define ETH_DMASR_RPS_Fetching_Pos             (17U)                           

 #define ETH_DMASR_RPS_Fetching_Msk             (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */

 #define ETH_DMASR_RPS_Fetching                 ETH_DMASR_RPS_Fetching_Msk      /* Running - fetching the Rx descriptor */

@@ -14233,14 +13821,14 @@ typedef struct
 #define ETH_DMAOMR_TTC_Pos                     (14U)                           

 #define ETH_DMAOMR_TTC_Msk                     (0x7U << ETH_DMAOMR_TTC_Pos)    /*!< 0x0001C000 */

 #define ETH_DMAOMR_TTC                         ETH_DMAOMR_TTC_Msk              /* Transmit threshold control */

-#define ETH_DMAOMR_TTC_64Bytes                 ((uint32_t)0x00000000)          /* threshold level of the MTL Transmit FIFO is 64 Bytes */

-#define ETH_DMAOMR_TTC_128Bytes                ((uint32_t)0x00004000)          /* threshold level of the MTL Transmit FIFO is 128 Bytes */

-#define ETH_DMAOMR_TTC_192Bytes                ((uint32_t)0x00008000)          /* threshold level of the MTL Transmit FIFO is 192 Bytes */

-#define ETH_DMAOMR_TTC_256Bytes                ((uint32_t)0x0000C000)          /* threshold level of the MTL Transmit FIFO is 256 Bytes */

-#define ETH_DMAOMR_TTC_40Bytes                 ((uint32_t)0x00010000)          /* threshold level of the MTL Transmit FIFO is 40 Bytes */

-#define ETH_DMAOMR_TTC_32Bytes                 ((uint32_t)0x00014000)          /* threshold level of the MTL Transmit FIFO is 32 Bytes */

-#define ETH_DMAOMR_TTC_24Bytes                 ((uint32_t)0x00018000)          /* threshold level of the MTL Transmit FIFO is 24 Bytes */

-#define ETH_DMAOMR_TTC_16Bytes                 ((uint32_t)0x0001C000)          /* threshold level of the MTL Transmit FIFO is 16 Bytes */

+#define ETH_DMAOMR_TTC_64Bytes                 0x00000000U                     /* threshold level of the MTL Transmit FIFO is 64 Bytes */

+#define ETH_DMAOMR_TTC_128Bytes                0x00004000U                     /* threshold level of the MTL Transmit FIFO is 128 Bytes */

+#define ETH_DMAOMR_TTC_192Bytes                0x00008000U                     /* threshold level of the MTL Transmit FIFO is 192 Bytes */

+#define ETH_DMAOMR_TTC_256Bytes                0x0000C000U                     /* threshold level of the MTL Transmit FIFO is 256 Bytes */

+#define ETH_DMAOMR_TTC_40Bytes                 0x00010000U                     /* threshold level of the MTL Transmit FIFO is 40 Bytes */

+#define ETH_DMAOMR_TTC_32Bytes                 0x00014000U                     /* threshold level of the MTL Transmit FIFO is 32 Bytes */

+#define ETH_DMAOMR_TTC_24Bytes                 0x00018000U                     /* threshold level of the MTL Transmit FIFO is 24 Bytes */

+#define ETH_DMAOMR_TTC_16Bytes                 0x0001C000U                     /* threshold level of the MTL Transmit FIFO is 16 Bytes */

 #define ETH_DMAOMR_ST_Pos                      (13U)                           

 #define ETH_DMAOMR_ST_Msk                      (0x1U << ETH_DMAOMR_ST_Pos)     /*!< 0x00002000 */

 #define ETH_DMAOMR_ST                          ETH_DMAOMR_ST_Msk               /* Start/stop transmission command */

@@ -14253,10 +13841,10 @@ typedef struct
 #define ETH_DMAOMR_RTC_Pos                     (3U)                            

 #define ETH_DMAOMR_RTC_Msk                     (0x3U << ETH_DMAOMR_RTC_Pos)    /*!< 0x00000018 */

 #define ETH_DMAOMR_RTC                         ETH_DMAOMR_RTC_Msk              /* receive threshold control */

-#define ETH_DMAOMR_RTC_64Bytes                 ((uint32_t)0x00000000)          /* threshold level of the MTL Receive FIFO is 64 Bytes */

-#define ETH_DMAOMR_RTC_32Bytes                 ((uint32_t)0x00000008)          /* threshold level of the MTL Receive FIFO is 32 Bytes */

-#define ETH_DMAOMR_RTC_96Bytes                 ((uint32_t)0x00000010)          /* threshold level of the MTL Receive FIFO is 96 Bytes */

-#define ETH_DMAOMR_RTC_128Bytes                ((uint32_t)0x00000018)          /* threshold level of the MTL Receive FIFO is 128 Bytes */

+#define ETH_DMAOMR_RTC_64Bytes                 0x00000000U                     /* threshold level of the MTL Receive FIFO is 64 Bytes */

+#define ETH_DMAOMR_RTC_32Bytes                 0x00000008U                     /* threshold level of the MTL Receive FIFO is 32 Bytes */

+#define ETH_DMAOMR_RTC_96Bytes                 0x00000010U                     /* threshold level of the MTL Receive FIFO is 96 Bytes */

+#define ETH_DMAOMR_RTC_128Bytes                0x00000018U                     /* threshold level of the MTL Receive FIFO is 128 Bytes */

 #define ETH_DMAOMR_OSF_Pos                     (2U)                            

 #define ETH_DMAOMR_OSF_Msk                     (0x1U << ETH_DMAOMR_OSF_Pos)    /*!< 0x00000004 */

 #define ETH_DMAOMR_OSF                         ETH_DMAOMR_OSF_Msk              /* operate on second frame */

@@ -14533,10 +14121,11 @@ typedef struct
 #define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           

 #define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

 #define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */

-#define USB_OTG_GAHBCFG_HBSTLEN_0               (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */

-#define USB_OTG_GAHBCFG_HBSTLEN_1               (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */

-#define USB_OTG_GAHBCFG_HBSTLEN_2               (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */

-#define USB_OTG_GAHBCFG_HBSTLEN_3               (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

 #define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           

 #define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

 #define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */

@@ -15673,7 +15262,7 @@ typedef struct
 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

 

 /****************************** DAC Instances *********************************/

-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

 

 /****************************** DMA Instances *********************************/

 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \

@@ -15706,6 +15295,9 @@ typedef struct
 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

                                        ((INSTANCE) == I2C2))

 

+/******************************* SMBUS Instances ******************************/

+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

+

 /******************************** I2S Instances *******************************/

 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \

                                        ((INSTANCE) == SPI3))

@@ -15729,6 +15321,8 @@ typedef struct
    ((INSTANCE) == TIM6)    || \

    ((INSTANCE) == TIM7))

 

+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)  ((INSTANCE) == TIM1)

+

 #define IS_TIM_CC1_INSTANCE(INSTANCE)\

   (((INSTANCE) == TIM1)    || \

    ((INSTANCE) == TIM2)    || \

@@ -15905,6 +15499,20 @@ typedef struct
 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\

   ((INSTANCE) == TIM1)

 

+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \

+                                        ((INSTANCE) == TIM2)    || \

+                                        ((INSTANCE) == TIM3)    || \

+                                        ((INSTANCE) == TIM4)    || \

+                                        ((INSTANCE) == TIM5))

+

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                         ((INSTANCE) == TIM2)    || \

+                                                         ((INSTANCE) == TIM3)    || \

+                                                         ((INSTANCE) == TIM4)    || \

+                                                         ((INSTANCE) == TIM5))

+

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U

+

 /****************************** END TIM Instances *****************************/

 

 

@@ -15977,10 +15585,14 @@ typedef struct
 /****************************** USB Instances ********************************/

 #define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH) 

 

+#define RCC_HSE_MIN         3000000U

+#define RCC_HSE_MAX        25000000U

+

+#define RCC_MAX_FREQUENCY  72000000U

 

 /**

   * @}

-*/ 

+  */ 

 /******************************************************************************/

 /*  For a painless codes migration between the STM32F1xx device product       */

 /*  lines, the aliases defined below are put in place to overcome the         */

@@ -15996,14 +15608,14 @@ typedef struct
 #define USB_HP_CAN1_TX_IRQn     CAN1_TX_IRQn

 #define USB_HP_IRQn             CAN1_TX_IRQn

 #define DMA2_Channel4_5_IRQn    DMA2_Channel4_IRQn

-#define USBWakeUp_IRQn          OTG_FS_WKUP_IRQn

 #define CEC_IRQn                OTG_FS_WKUP_IRQn

+#define USBWakeUp_IRQn          OTG_FS_WKUP_IRQn

 #define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn

 #define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn

 #define TIM9_IRQn               TIM1_BRK_IRQn

+#define TIM11_IRQn              TIM1_TRG_COM_IRQn

 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

-#define TIM11_IRQn              TIM1_TRG_COM_IRQn

 #define TIM10_IRQn              TIM1_UP_IRQn

 #define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn

 #define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn

@@ -16017,20 +15629,19 @@ typedef struct
 #define USB_HP_CAN1_TX_IRQHandler     CAN1_TX_IRQHandler

 #define USB_HP_IRQHandler             CAN1_TX_IRQHandler

 #define DMA2_Channel4_5_IRQHandler    DMA2_Channel4_IRQHandler

-#define USBWakeUp_IRQHandler          OTG_FS_WKUP_IRQHandler

 #define CEC_IRQHandler                OTG_FS_WKUP_IRQHandler

+#define USBWakeUp_IRQHandler          OTG_FS_WKUP_IRQHandler

 #define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler

 #define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler

 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler

+#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

-#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler

 #define TIM10_IRQHandler              TIM1_UP_IRQHandler

 #define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler

 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler

 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler

 

-

 /**

   * @}

   */

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f1xx.h b/os/common/ext/ST/STM32F1xx/stm32f1xx.h
index 233d1b3ed..333095bae 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/stm32f1xx.h
+++ b/os/common/ext/ST/STM32F1xx/stm32f1xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f1xx.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. 

   *

   *          The file is the unique include file that the application programmer

@@ -18,7 +18,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -108,10 +108,10 @@
 #endif /* USE_HAL_DRIVER */

 

 /**

-  * @brief CMSIS Device version number

+  * @brief CMSIS Device version number V4.2.0

   */

-#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */                                  

-#define __STM32F1_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */

+#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */

+#define __STM32F1_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */

 #define __STM32F1_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */

 #define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 

 #define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\

diff --git a/os/common/ext/CMSIS/ST/STM32F1xx/system_stm32f1xx.h b/os/common/ext/ST/STM32F1xx/system_stm32f1xx.h
index 35870158c..3652ff591 100644
--- a/os/common/ext/CMSIS/ST/STM32F1xx/system_stm32f1xx.h
+++ b/os/common/ext/ST/STM32F1xx/system_stm32f1xx.h
@@ -2,13 +2,13 @@
   ******************************************************************************

   * @file    system_stm32f10x.h

   * @author  MCD Application Team

-  * @version V4.1.0

-  * @date    29-April-2016

+  * @version V4.2.0

+  * @date    31-March-2017

   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.

   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -67,8 +67,8 @@
   */

 

 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */

-extern const uint8_t  AHBPrescTable[16];  /*!< AHB prescalers table values */

-extern const uint8_t  APBPrescTable[8];   /*!< APB prescalers table values */

+extern const uint8_t  AHBPrescTable[16U];  /*!< AHB prescalers table values */

+extern const uint8_t  APBPrescTable[8U];   /*!< APB prescalers table values */

 

 /**

   * @}

diff --git a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f205xx.h b/os/common/ext/ST/STM32F2xx/stm32f205xx.h
index f6648a3ac..f6648a3ac 100644
--- a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f205xx.h
+++ b/os/common/ext/ST/STM32F2xx/stm32f205xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f207xx.h b/os/common/ext/ST/STM32F2xx/stm32f207xx.h
index 75f7aae8b..75f7aae8b 100644
--- a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f207xx.h
+++ b/os/common/ext/ST/STM32F2xx/stm32f207xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f215xx.h b/os/common/ext/ST/STM32F2xx/stm32f215xx.h
index fce57440a..fce57440a 100644
--- a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f215xx.h
+++ b/os/common/ext/ST/STM32F2xx/stm32f215xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f217xx.h b/os/common/ext/ST/STM32F2xx/stm32f217xx.h
index ee01878e3..ee01878e3 100644
--- a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f217xx.h
+++ b/os/common/ext/ST/STM32F2xx/stm32f217xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f2xx.h b/os/common/ext/ST/STM32F2xx/stm32f2xx.h
index f4897447b..f4897447b 100644
--- a/os/common/ext/CMSIS/ST/STM32F2xx/stm32f2xx.h
+++ b/os/common/ext/ST/STM32F2xx/stm32f2xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F2xx/system_stm32f2xx.h b/os/common/ext/ST/STM32F2xx/system_stm32f2xx.h
index b30c61b35..b30c61b35 100644
--- a/os/common/ext/CMSIS/ST/STM32F2xx/system_stm32f2xx.h
+++ b/os/common/ext/ST/STM32F2xx/system_stm32f2xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f301x8.h b/os/common/ext/ST/STM32F3xx/stm32f301x8.h
index f226230e3..f226230e3 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f301x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f301x8.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f302x8.h b/os/common/ext/ST/STM32F3xx/stm32f302x8.h
index 0d203c7fb..0d203c7fb 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f302x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f302x8.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f302xc.h b/os/common/ext/ST/STM32F3xx/stm32f302xc.h
index 68e6441e4..68e6441e4 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f302xc.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f302xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f302xe.h b/os/common/ext/ST/STM32F3xx/stm32f302xe.h
index 484c51b43..484c51b43 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f302xe.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f302xe.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f303x8.h b/os/common/ext/ST/STM32F3xx/stm32f303x8.h
index 4f5c2f5a2..4f5c2f5a2 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f303x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f303x8.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f303xc.h b/os/common/ext/ST/STM32F3xx/stm32f303xc.h
index 35f1d3a2e..35f1d3a2e 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f303xc.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f303xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f303xe.h b/os/common/ext/ST/STM32F3xx/stm32f303xe.h
index 44520de44..44520de44 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f303xe.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f303xe.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f318xx.h b/os/common/ext/ST/STM32F3xx/stm32f318xx.h
index f59f855eb..f59f855eb 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f318xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f318xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f328xx.h b/os/common/ext/ST/STM32F3xx/stm32f328xx.h
index 768c7fab0..768c7fab0 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f328xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f328xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f334x8.h b/os/common/ext/ST/STM32F3xx/stm32f334x8.h
index cf075c5c3..cf075c5c3 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f334x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f334x8.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f358xx.h b/os/common/ext/ST/STM32F3xx/stm32f358xx.h
index b33054fd5..b33054fd5 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f358xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f358xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f373xc.h b/os/common/ext/ST/STM32F3xx/stm32f373xc.h
index 4a5545a70..4a5545a70 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f373xc.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f373xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f378xx.h b/os/common/ext/ST/STM32F3xx/stm32f378xx.h
index 35e2c1ade..35e2c1ade 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f378xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f378xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f398xx.h b/os/common/ext/ST/STM32F3xx/stm32f398xx.h
index 295d3c5a9..295d3c5a9 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f398xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f398xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f3xx.h b/os/common/ext/ST/STM32F3xx/stm32f3xx.h
index bca50c7d1..bca50c7d1 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/stm32f3xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f3xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F3xx/system_stm32f3xx.h b/os/common/ext/ST/STM32F3xx/system_stm32f3xx.h
index d17cd7dc7..d17cd7dc7 100644
--- a/os/common/ext/CMSIS/ST/STM32F3xx/system_stm32f3xx.h
+++ b/os/common/ext/ST/STM32F3xx/system_stm32f3xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f401xc.h b/os/common/ext/ST/STM32F4xx/stm32f401xc.h
index 50f064d61..50f064d61 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f401xc.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f401xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f401xe.h b/os/common/ext/ST/STM32F4xx/stm32f401xe.h
index 3aaf056e1..3aaf056e1 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f401xe.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f401xe.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f405xx.h b/os/common/ext/ST/STM32F4xx/stm32f405xx.h
index d3dbe967c..d3dbe967c 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f405xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f405xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f407xx.h b/os/common/ext/ST/STM32F4xx/stm32f407xx.h
index 2215cc4d8..2215cc4d8 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f407xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f407xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f410cx.h b/os/common/ext/ST/STM32F4xx/stm32f410cx.h
index 195043fb4..195043fb4 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f410cx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f410cx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f410rx.h b/os/common/ext/ST/STM32F4xx/stm32f410rx.h
index 0bcc9173c..0bcc9173c 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f410rx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f410rx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f410tx.h b/os/common/ext/ST/STM32F4xx/stm32f410tx.h
index 26815665c..26815665c 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f410tx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f410tx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f411xe.h b/os/common/ext/ST/STM32F4xx/stm32f411xe.h
index 737a049e9..737a049e9 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f411xe.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f411xe.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412cx.h b/os/common/ext/ST/STM32F4xx/stm32f412cx.h
index 82da51886..82da51886 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412cx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f412cx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412rx.h b/os/common/ext/ST/STM32F4xx/stm32f412rx.h
index 055e84e02..055e84e02 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412rx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f412rx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412vx.h b/os/common/ext/ST/STM32F4xx/stm32f412vx.h
index 5d32f1d49..5d32f1d49 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412vx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f412vx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412zx.h b/os/common/ext/ST/STM32F4xx/stm32f412zx.h
index 1df370771..1df370771 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f412zx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f412zx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f413xx.h b/os/common/ext/ST/STM32F4xx/stm32f413xx.h
index ae74b998c..ae74b998c 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f413xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f413xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f415xx.h b/os/common/ext/ST/STM32F4xx/stm32f415xx.h
index a0df4bc53..a0df4bc53 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f415xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f415xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f417xx.h b/os/common/ext/ST/STM32F4xx/stm32f417xx.h
index 833fd409b..833fd409b 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f417xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f417xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f423xx.h b/os/common/ext/ST/STM32F4xx/stm32f423xx.h
index b3c43a589..b3c43a589 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f423xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f423xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f427xx.h b/os/common/ext/ST/STM32F4xx/stm32f427xx.h
index 9536072d2..9536072d2 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f427xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f427xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f429xx.h b/os/common/ext/ST/STM32F4xx/stm32f429xx.h
index 85adfb239..85adfb239 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f429xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f429xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f437xx.h b/os/common/ext/ST/STM32F4xx/stm32f437xx.h
index acfb39497..acfb39497 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f437xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f437xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f439xx.h b/os/common/ext/ST/STM32F4xx/stm32f439xx.h
index ada8138c5..ada8138c5 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f439xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f439xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f446xx.h b/os/common/ext/ST/STM32F4xx/stm32f446xx.h
index 2a31af53e..2a31af53e 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f446xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f446xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f469xx.h b/os/common/ext/ST/STM32F4xx/stm32f469xx.h
index dc14598be..dc14598be 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f469xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f469xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f479xx.h b/os/common/ext/ST/STM32F4xx/stm32f479xx.h
index 4562c0b2f6..4562c0b2f6 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f479xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f479xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f4xx.h b/os/common/ext/ST/STM32F4xx/stm32f4xx.h
index e282b297f..e282b297f 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/stm32f4xx.h
+++ b/os/common/ext/ST/STM32F4xx/stm32f4xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F4xx/system_stm32f4xx.h b/os/common/ext/ST/STM32F4xx/system_stm32f4xx.h
index 06309051c..06309051c 100644
--- a/os/common/ext/CMSIS/ST/STM32F4xx/system_stm32f4xx.h
+++ b/os/common/ext/ST/STM32F4xx/system_stm32f4xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f722xx.h b/os/common/ext/ST/STM32F7xx/stm32f722xx.h
index cf66a392c..cf66a392c 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f722xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f722xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f723xx.h b/os/common/ext/ST/STM32F7xx/stm32f723xx.h
index 8b7979f94..8b7979f94 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f723xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f723xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f732xx.h b/os/common/ext/ST/STM32F7xx/stm32f732xx.h
index 513c6767b..513c6767b 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f732xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f732xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f733xx.h b/os/common/ext/ST/STM32F7xx/stm32f733xx.h
index f8526c1f5..f8526c1f5 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f733xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f733xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f745xx.h b/os/common/ext/ST/STM32F7xx/stm32f745xx.h
index 02680b800..02680b800 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f745xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f745xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f746xx.h b/os/common/ext/ST/STM32F7xx/stm32f746xx.h
index a357ade80..a357ade80 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f746xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f746xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f756xx.h b/os/common/ext/ST/STM32F7xx/stm32f756xx.h
index fa41938f8..fa41938f8 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f756xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f756xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f765xx.h b/os/common/ext/ST/STM32F7xx/stm32f765xx.h
index 79687d5f5..79687d5f5 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f765xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f765xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f767xx.h b/os/common/ext/ST/STM32F7xx/stm32f767xx.h
index ae3fc5005..ae3fc5005 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f767xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f767xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f769xx.h b/os/common/ext/ST/STM32F7xx/stm32f769xx.h
index c638b8109..c638b8109 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f769xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f769xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f777xx.h b/os/common/ext/ST/STM32F7xx/stm32f777xx.h
index cce4b4b3d..cce4b4b3d 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f777xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f777xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f779xx.h b/os/common/ext/ST/STM32F7xx/stm32f779xx.h
index 6364801f4..6364801f4 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f779xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f779xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f7xx.h b/os/common/ext/ST/STM32F7xx/stm32f7xx.h
index 614c6dbaf..614c6dbaf 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/stm32f7xx.h
+++ b/os/common/ext/ST/STM32F7xx/stm32f7xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32F7xx/system_stm32f7xx.h b/os/common/ext/ST/STM32F7xx/system_stm32f7xx.h
index 0fec9583d..0fec9583d 100644
--- a/os/common/ext/CMSIS/ST/STM32F7xx/system_stm32f7xx.h
+++ b/os/common/ext/ST/STM32F7xx/system_stm32f7xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32H7xx/stm32h743xx.h b/os/common/ext/ST/STM32H7xx/stm32h743xx.h
index 3d964608b..3d964608b 100644
--- a/os/common/ext/CMSIS/ST/STM32H7xx/stm32h743xx.h
+++ b/os/common/ext/ST/STM32H7xx/stm32h743xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32H7xx/stm32h753xx.h b/os/common/ext/ST/STM32H7xx/stm32h753xx.h
index 65ff549c1..65ff549c1 100644
--- a/os/common/ext/CMSIS/ST/STM32H7xx/stm32h753xx.h
+++ b/os/common/ext/ST/STM32H7xx/stm32h753xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32H7xx/stm32h7xx.h b/os/common/ext/ST/STM32H7xx/stm32h7xx.h
index 2f85befdc..2f85befdc 100644
--- a/os/common/ext/CMSIS/ST/STM32H7xx/stm32h7xx.h
+++ b/os/common/ext/ST/STM32H7xx/stm32h7xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32H7xx/system_stm32h7xx.h b/os/common/ext/ST/STM32H7xx/system_stm32h7xx.h
index f22a6f064..f22a6f064 100644
--- a/os/common/ext/CMSIS/ST/STM32H7xx/system_stm32h7xx.h
+++ b/os/common/ext/ST/STM32H7xx/system_stm32h7xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l011xx.h b/os/common/ext/ST/STM32L0xx/stm32l011xx.h
index dee9ae0c3..dee9ae0c3 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l011xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l011xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l021xx.h b/os/common/ext/ST/STM32L0xx/stm32l021xx.h
index 350173f4c..350173f4c 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l021xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l021xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l031xx.h b/os/common/ext/ST/STM32L0xx/stm32l031xx.h
index 2572ef902..2572ef902 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l031xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l031xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l041xx.h b/os/common/ext/ST/STM32L0xx/stm32l041xx.h
index 7bea4ef68..7bea4ef68 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l041xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l041xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l051xx.h b/os/common/ext/ST/STM32L0xx/stm32l051xx.h
index 42f185050..42f185050 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l051xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l051xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l052xx.h b/os/common/ext/ST/STM32L0xx/stm32l052xx.h
index 37bfb76f2..37bfb76f2 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l052xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l052xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l053xx.h b/os/common/ext/ST/STM32L0xx/stm32l053xx.h
index eb7257df8..eb7257df8 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l053xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l053xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l061xx.h b/os/common/ext/ST/STM32L0xx/stm32l061xx.h
index a1eadf9f6..a1eadf9f6 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l061xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l061xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l062xx.h b/os/common/ext/ST/STM32L0xx/stm32l062xx.h
index 0b917fbb1..0b917fbb1 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l062xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l062xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l063xx.h b/os/common/ext/ST/STM32L0xx/stm32l063xx.h
index 222d94089..222d94089 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l063xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l063xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l071xx.h b/os/common/ext/ST/STM32L0xx/stm32l071xx.h
index ab3ec86fd..ab3ec86fd 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l071xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l071xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l072xx.h b/os/common/ext/ST/STM32L0xx/stm32l072xx.h
index be4822968..be4822968 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l072xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l072xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l073xx.h b/os/common/ext/ST/STM32L0xx/stm32l073xx.h
index 2eb55507f..2eb55507f 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l073xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l073xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l081xx.h b/os/common/ext/ST/STM32L0xx/stm32l081xx.h
index 9b041553b..9b041553b 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l081xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l081xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l082xx.h b/os/common/ext/ST/STM32L0xx/stm32l082xx.h
index 69f951c6b..69f951c6b 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l082xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l082xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l083xx.h b/os/common/ext/ST/STM32L0xx/stm32l083xx.h
index e49ea2d89..e49ea2d89 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l083xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l083xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l0xx.h b/os/common/ext/ST/STM32L0xx/stm32l0xx.h
index ef04251c9..ef04251c9 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l0xx.h
+++ b/os/common/ext/ST/STM32L0xx/stm32l0xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h b/os/common/ext/ST/STM32L0xx/system_stm32l0xx.h
index 64b85cbf1..64b85cbf1 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h
+++ b/os/common/ext/ST/STM32L0xx/system_stm32l0xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l100xb.h b/os/common/ext/ST/STM32L1xx/stm32l100xb.h
index 6fcfde992..6fcfde992 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l100xb.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l100xb.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l100xba.h b/os/common/ext/ST/STM32L1xx/stm32l100xba.h
index 50071fbd6..50071fbd6 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l100xba.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l100xba.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l100xc.h b/os/common/ext/ST/STM32L1xx/stm32l100xc.h
index 164e25087..164e25087 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l100xc.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l100xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h b/os/common/ext/ST/STM32L1xx/stm32l151xb.h
index ec3d620d4..ec3d620d4 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xb.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l151xb.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xba.h b/os/common/ext/ST/STM32L1xx/stm32l151xba.h
index c17b716d2..c17b716d2 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xba.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l151xba.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xc.h b/os/common/ext/ST/STM32L1xx/stm32l151xc.h
index 8813f674a..8813f674a 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xc.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l151xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xca.h b/os/common/ext/ST/STM32L1xx/stm32l151xca.h
index 9b3afa9f4..9b3afa9f4 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xca.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l151xca.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xd.h b/os/common/ext/ST/STM32L1xx/stm32l151xd.h
index 56635715a..56635715a 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xd.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l151xd.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xdx.h b/os/common/ext/ST/STM32L1xx/stm32l151xdx.h
index 7181aef8b..7181aef8b 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xdx.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l151xdx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xe.h b/os/common/ext/ST/STM32L1xx/stm32l151xe.h
index 107d87e73..107d87e73 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l151xe.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l151xe.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xb.h b/os/common/ext/ST/STM32L1xx/stm32l152xb.h
index 59ce10aa9..59ce10aa9 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xb.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l152xb.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xba.h b/os/common/ext/ST/STM32L1xx/stm32l152xba.h
index 3395b2239..3395b2239 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xba.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l152xba.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xc.h b/os/common/ext/ST/STM32L1xx/stm32l152xc.h
index d548988f5..d548988f5 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xc.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l152xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xca.h b/os/common/ext/ST/STM32L1xx/stm32l152xca.h
index fa06998c5..fa06998c5 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xca.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l152xca.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xd.h b/os/common/ext/ST/STM32L1xx/stm32l152xd.h
index 2c7ca6421..2c7ca6421 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xd.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l152xd.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xdx.h b/os/common/ext/ST/STM32L1xx/stm32l152xdx.h
index 9bc02c88c..9bc02c88c 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xdx.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l152xdx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xe.h b/os/common/ext/ST/STM32L1xx/stm32l152xe.h
index 7f3313a4d..7f3313a4d 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l152xe.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l152xe.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xc.h b/os/common/ext/ST/STM32L1xx/stm32l162xc.h
index 1a05b848e..1a05b848e 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xc.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l162xc.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xca.h b/os/common/ext/ST/STM32L1xx/stm32l162xca.h
index cb1031f26..cb1031f26 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xca.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l162xca.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xd.h b/os/common/ext/ST/STM32L1xx/stm32l162xd.h
index 9702619a9..9702619a9 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xd.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l162xd.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xdx.h b/os/common/ext/ST/STM32L1xx/stm32l162xdx.h
index 9797848b5..9797848b5 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xdx.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l162xdx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xe.h b/os/common/ext/ST/STM32L1xx/stm32l162xe.h
index 469d49b6e..469d49b6e 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l162xe.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l162xe.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l1xx.h b/os/common/ext/ST/STM32L1xx/stm32l1xx.h
index 7fd1727fd..7fd1727fd 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/stm32l1xx.h
+++ b/os/common/ext/ST/STM32L1xx/stm32l1xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L1xx/system_stm32l1xx.h b/os/common/ext/ST/STM32L1xx/system_stm32l1xx.h
index a5d2f7b2e..a5d2f7b2e 100644
--- a/os/common/ext/CMSIS/ST/STM32L1xx/system_stm32l1xx.h
+++ b/os/common/ext/ST/STM32L1xx/system_stm32l1xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l431xx.h b/os/common/ext/ST/STM32L4xx/stm32l431xx.h
index f3d455663..f3d455663 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l431xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l431xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l432xx.h b/os/common/ext/ST/STM32L4xx/stm32l432xx.h
index cd341d2c2..cd341d2c2 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l432xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l432xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l433xx.h b/os/common/ext/ST/STM32L4xx/stm32l433xx.h
index 3422ff75c..3422ff75c 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l433xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l433xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l442xx.h b/os/common/ext/ST/STM32L4xx/stm32l442xx.h
index 9e03e770f..9e03e770f 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l442xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l442xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l443xx.h b/os/common/ext/ST/STM32L4xx/stm32l443xx.h
index a555fc045..a555fc045 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l443xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l443xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l451xx.h b/os/common/ext/ST/STM32L4xx/stm32l451xx.h
index e35bf50ea..e35bf50ea 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l451xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l451xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l452xx.h b/os/common/ext/ST/STM32L4xx/stm32l452xx.h
index aca55f7f5..aca55f7f5 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l452xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l452xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l462xx.h b/os/common/ext/ST/STM32L4xx/stm32l462xx.h
index 3d6721ec8..3d6721ec8 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l462xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l462xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l471xx.h b/os/common/ext/ST/STM32L4xx/stm32l471xx.h
index 06535dc0d..06535dc0d 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l471xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l471xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l475xx.h b/os/common/ext/ST/STM32L4xx/stm32l475xx.h
index 46ce02363..46ce02363 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l475xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l475xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l476xx.h b/os/common/ext/ST/STM32L4xx/stm32l476xx.h
index 2ed63d29a..2ed63d29a 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l476xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l476xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l485xx.h b/os/common/ext/ST/STM32L4xx/stm32l485xx.h
index 949481a94..949481a94 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l485xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l485xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l486xx.h b/os/common/ext/ST/STM32L4xx/stm32l486xx.h
index fadb24f3d..fadb24f3d 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l486xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l486xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l496xx.h b/os/common/ext/ST/STM32L4xx/stm32l496xx.h
index 7e4e5aa13..7e4e5aa13 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l496xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l496xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l4a6xx.h b/os/common/ext/ST/STM32L4xx/stm32l4a6xx.h
index 5eb106cd7..5eb106cd7 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l4a6xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l4a6xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l4xx.h b/os/common/ext/ST/STM32L4xx/stm32l4xx.h
index c26260e4c..c26260e4c 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/stm32l4xx.h
+++ b/os/common/ext/ST/STM32L4xx/stm32l4xx.h
diff --git a/os/common/ext/CMSIS/ST/STM32L4xx/system_stm32l4xx.h b/os/common/ext/ST/STM32L4xx/system_stm32l4xx.h
index 40eecec46..40eecec46 100644
--- a/os/common/ext/CMSIS/ST/STM32L4xx/system_stm32l4xx.h
+++ b/os/common/ext/ST/STM32L4xx/system_stm32l4xx.h