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-rw-r--r--os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h b/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h
index 2eafa1248..ce3a7234d 100644
--- a/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h
+++ b/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 18-June-2014
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
- * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/*
+*/
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
+
/**
* @}