diff options
Diffstat (limited to 'os/common/ext/ARM/CMSIS/Core_A')
5 files changed, 26 insertions, 18 deletions
diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armcc.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armcc.h index 7c4c94834..313d7435b 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armcc.h +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_armcc.h @@ -451,8 +451,8 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) * Include common core functions to access Coprocessor 15 registers */ -#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) -#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) #define __get_CP64(cp, op1, Rt, CRm) \ do { \ uint32_t ltmp, htmp; \ diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h index 5ac93d12c..4f464627a 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.1 - * @date 07. Sep 2017 + * @version V1.0.2 + * @date 09. April 2018 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -450,7 +450,9 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else @@ -473,7 +475,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_iccarm.h b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_iccarm.h index a441e2d85..bb0248dc6 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_iccarm.h +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/cmsis_iccarm.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 + * @version V5.0.6 + * @date 02. March 2018 ******************************************************************************/ //------------------------------------------------------------------------------ @@ -109,7 +109,7 @@ #endif #ifndef __RESTRICT - #define __RESTRICT restrict + #define __RESTRICT __restrict #endif #ifndef __STATIC_INLINE diff --git a/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h b/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h index c7c4b511f..dbe9794d4 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h +++ b/os/common/ext/ARM/CMSIS/Core_A/Include/core_ca.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_ca.h * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File - * @version V1.00 - * @date 22. Feb 2017 + * @version V1.0.1 + * @date 07. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -1284,8 +1284,6 @@ __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) } else { // INTID 0-15 Software Generated Interrupt GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); - // Forward the interrupt to the CPU interface that requested it - GICDistributor->SGIR = (IRQn | 0x02000000U); } } diff --git a/os/common/ext/ARM/CMSIS/Core_A/Source/irq_ctrl_gic.c b/os/common/ext/ARM/CMSIS/Core_A/Source/irq_ctrl_gic.c index 5fbe9dc65..25d135915 100644 --- a/os/common/ext/ARM/CMSIS/Core_A/Source/irq_ctrl_gic.c +++ b/os/common/ext/ARM/CMSIS/Core_A/Source/irq_ctrl_gic.c @@ -1,8 +1,8 @@ /**************************************************************************//** * @file irq_ctrl_gic.c * @brief Interrupt controller handling implementation for GIC - * @version V1.0.0 - * @date 30. June 2017 + * @version V1.0.1 + * @date 9. April 2018 ******************************************************************************/ /* * Copyright (c) 2017 ARM Limited. All rights reserved. @@ -37,7 +37,7 @@ #endif static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; -static uint32_t IRQ_ID0; +static uint32_t IRQ_ID0; /// Initialize interrupt controller. __WEAK int32_t IRQ_Initialize (void) { @@ -70,6 +70,9 @@ __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { __WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { IRQHandler_t h; + // Ignore CPUID field (software generated interrupts) + irqn &= 0x3FFU; + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { h = IRQTable[irqn]; } else { @@ -271,9 +274,12 @@ __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { /// Signal end of interrupt processing. __WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { int32_t status; + IRQn_Type irq = (IRQn_Type)irqn; + + irqn &= 0x3FFU; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { - GIC_EndInterrupt ((IRQn_Type)irqn); + GIC_EndInterrupt (irq); if (irqn == 0) { IRQ_ID0 = 0U; |