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-rw-r--r--docs/reports/LPC2148-48-ARM.txt8
-rw-r--r--docs/reports/LPC2148-48-THUMB.txt8
2 files changed, 8 insertions, 8 deletions
diff --git a/docs/reports/LPC2148-48-ARM.txt b/docs/reports/LPC2148-48-ARM.txt
index 3a4ebc0aa..c179db3cf 100644
--- a/docs/reports/LPC2148-48-ARM.txt
+++ b/docs/reports/LPC2148-48-ARM.txt
@@ -5,7 +5,7 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
*** ChibiOS/RT test suite
***
-*** Kernel: 2.1.4unstable
+*** Kernel: 2.1.6unstable
*** GCC Version: 4.5.1
*** Architecture: ARM7
*** Core Variant: ARM7TDMI
@@ -114,11 +114,11 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 89745 threads/S
+--- Score : 88089 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 128237 threads/S
+--- Score : 126542 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
@@ -126,7 +126,7 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 276080 ctxswc/S
+--- Score : 276084 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
diff --git a/docs/reports/LPC2148-48-THUMB.txt b/docs/reports/LPC2148-48-THUMB.txt
index 9fcee16af..199f592f4 100644
--- a/docs/reports/LPC2148-48-THUMB.txt
+++ b/docs/reports/LPC2148-48-THUMB.txt
@@ -5,7 +5,7 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
*** ChibiOS/RT test suite
***
-*** Kernel: 2.1.4unstable
+*** Kernel: 2.1.6unstable
*** GCC Version: 4.5.1
*** Architecture: ARM7
*** Core Variant: ARM7TDMI
@@ -98,7 +98,7 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 106223 msgs/S, 212446 ctxswc/S
+--- Score : 106224 msgs/S, 212448 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
@@ -114,11 +114,11 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 71990 threads/S
+--- Score : 70297 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 110394 threads/S
+--- Score : 109135 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)