diff options
Diffstat (limited to 'demos/STM32')
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/chconf.h | 2 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h | 2 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h | 24 |
3 files changed, 17 insertions, 11 deletions
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/chconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/chconf.h index 1a1d8b293..6ce63df18 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/chconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/chconf.h @@ -71,7 +71,7 @@ * The value one is not valid, timeouts are rounded up to
* this value.
*/
-#define CH_CFG_ST_TIMEDELTA 2
+#define CH_CFG_ST_TIMEDELTA 0
/** @} */
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h index 5aec384f3..fc148a68e 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h @@ -34,7 +34,7 @@ * @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
-#define HAL_USE_PAL TRUE
+#define HAL_USE_PAL FALSE
#endif
/**
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h index a8e697763..f79c6c189 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h @@ -37,32 +37,38 @@ * General settings.
*/
#define STM32_NO_INIT FALSE
-#define STM32_HCLK_ENFORCED_VALUE STM32_HSICLK
+#define STM32_SYS_CK_ENFORCED_VALUE STM32_HSICLK
/*
* PWR system settings.
* Reading STM32 Reference Manual is required.
- * Constants are taken from the ST header.
+ * Register constants are taken from the ST header.
*/
-#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
+#define STM32_VOS STM32_VOS_SCALE1
+#define STM32_PWR_CR1 (PWR_CR1_PVDEN | \
+ PWR_CR1_SVOS_1 | \
+ PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN)
-#define STM32_PWR_CR3 (PWR_CR3_SCUEN | PWR_CR3_LDOEN)
+#define STM32_PWR_CR3 (PWR_CR3_SCUEN | \
+ PWR_CR3_LDOEN | \
+ PWR_CR3_USBREGEN | \
+ PWR_CR3_USB33DEN)
#define STM32_PWR_CPUCR 0
-#define STM32_PWR_D3CR (PWR_D3CR_VOS_0)
/*
* Clock tree static settings.
* Reading STM32 Reference Manual is required.
*/
#define STM32_HSI_ENABLED TRUE
-#define STM32_LSI_ENABLED FALSE
-#define STM32_CSI_ENABLED FALSE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_CSI_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_HSIDIV STM32_HSIDIV_DIV1
#define STM32_RTCPRE_VALUE 8
#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
+#define STM32_PLLCFGR_MASK ~0
#define STM32_PLL1_ENABLED TRUE
#define STM32_PLL1_DIVM_VALUE 4
#define STM32_PLL1_DIVN_VALUE 400
@@ -86,9 +92,9 @@ #define STM32_PLL3_DIVR_VALUE 8
#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
-#define STM32_MCO1PRE 4
+#define STM32_MCO1PRE_VALUE 4
#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
-#define STM32_MCO2PRE 4
+#define STM32_MCO2PRE_VALUE 4
/*
* Core clocks dynamic settings (can be changed at runtime).
|