1 files changed, 185 insertions, 0 deletions
diff --git a/demos/SPC5/RT-SPC563M-EVB/UDE/stm_xpc563m64_minimodule_debug_jtag.cfg b/demos/SPC5/RT-SPC563M-EVB/UDE/stm_xpc563m64_minimodule_debug_jtag.cfg
new file mode 100644
index 000000000..b43d92891
--- /dev/null
+++ b/demos/SPC5/RT-SPC563M-EVB/UDE/stm_xpc563m64_minimodule_debug_jtag.cfg
@@ -0,0 +1,185 @@
+[Main]
+Signature=UDE_TARGINFO_2.0
+Description=STM XPC563M Mini Module with SPC563M64 1.5M (Jtag)
+Description1=MMU preinitialized, memory mapping 1:1, VLE enabled for SRAM and Flash
+Description2=PLL set for 80MHz
+Description3=FLASH programming prepared but not enabled
+Description4=Write Filter for BAM Module
+MCUs=Controller0
+Architecture=PowerPC
+Vendor=STM
+Board=XPC563M Mini Module
+
+[Controller0]
+Family=PowerPC
+Type=SPC563M64
+Enabled=1
+IntClock=80000
+MemDevs=BAMWriteFilter
+ExtClock=12000
+
+[Controller0.Core]
+Protocol=PPCJTAG
+Enabled=1
+
+[Controller0.Core.LoadedAddOn]
+UDEMemtool=1
+
+[Controller0.Core.PpcJtagTargIntf]
+PortType=FTDI
+ResetWaitTime=50
+MaxJtagClk=1000
+DoSramInit=1
+UseNexus=1
+AdaptiveJtagPhaseShift=1
+ConnOption=Reset
+ChangeJtagClk=-1
+HaltAfterReset=1
+SimioAddr=g_JtagSimioAccess
+FreezeTimers=1
+InvalidTlbOnReset=1
+InvalidateCache=0
+ForceCacheFlush=0
+IgnoreLockedLines=0
+ExecInitCmds=1
+JtagTapNumber=0
+JtagNumOfTaps=1
+JtagNumIrBefore=0
+JtagNumIrAfter=0
+
+SimioAddr=g_JtagSimioAccess
+
+FlushCache=0
+AllowMmuSetup=1
+UseExtReset=1
+HandleWdtBug=0
+ForceEndOfReset=0
+CommDevSel=PortType=USB,Type=FTDI
+JtagViaPod=1
+TargetPort=Default
+ChangeMsr=0
+ChangeMsrValue=0x0
+ExecOnStartCmds=0
+ExecOnHaltCmds=0
+EnableProgramTimeMeasurement=0
+UseHwResetMode=1
+HandleNexusAccessBug=0
+DoNotEnableTrapSwBrp=0
+AllowResetOnCheck=0
+BootPasswd0=0xFEEDFACE
+BootPasswd1=0xCAFEBEEF
+BootPasswd2=0xFFFFFFFF
+BootPasswd3=0xFFFFFFFF
+BootPasswd4=0xFFFFFFFF
+BootPasswd5=0xFFFFFFFF
+BootPasswd6=0xFFFFFFFF
+BootPasswd7=0xFFFFFFFF
+JtagIoType=Jtag
+ExecOnHaltCmdsWhileHalted=0
+TimerForPTM=Default
+AllowBreakOnUpdateBreakpoints=0
+ClearDebugStatusOnHalt=1
+HwResetMode=Execute
+UseMasterNexusIfResetState=1
+UseLocalAddressTranslation=1
+Use64BitNexus=0
+InitSramOnlyWhenNotInitialized=0
+DisableE2EECC=0
+AllowHarrForUpdateDebugRegs=0
+UseCore0ForNexusMemoryAccessWhileRunning=0
+
+[Controller0.BAMWriteFilter]
+Description=BAM WriteAccess Filter
+Range0Start=0xFFFFC000
+Range0Size=0x4000
+Enabled=1
+Handler=AccessFilter
+Mode=ReadOnly
+
+[Controller0.PFLASH0]
+Enabled=1
+EnableMemtoolByDefault=1
+
+[Controller0.PFLASH1]
+Enabled=1
+EnableMemtoolByDefault=1
+
+[Controller0.PFLASH2]
+Enabled=1
+EnableMemtoolByDefault=1
+
+[Controller0.Core.PpcJtagTargIntf.InitScript]
+
+// TLB invalidate
+SETSPR 0x3F4 0x2 0xFFFFFFFF
+// select TLB 1
+SETSPR 0x274 0x10000108 0xFFFFFFFF
+
+// programm peripheral B modules
+// TLB 1, entry 0
+SETSPR 0x270 0x10000000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number FFF00000, I,G
+SETSPR 0x272 0xFFF0000A 0xFFFFFFFF
+// real page FFF00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xFFF0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm internal Flash, no cache because of flash
+// TLB 1, entry 1
+SETSPR 0x270 0x10010000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=16MB
+SETSPR 0x271 0xC0000700 0xFFFFFFFF
+// effective page number 00000000
+SETSPR 0x272 0x28 0xFFFFFFFF
+// real page 00000000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0x3F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm internal SRAM
+// TLB 1, entry 2
+SETSPR 0x270 0x10020000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=256k
+SETSPR 0x271 0xC0000400 0xFFFFFFFF
+// effective page number 40000000, I
+SETSPR 0x272 0x40000028 0xFFFFFFFF
+// real page 0x40000028, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0x4000003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm peripheral A modules
+// TLB 1, entry 4
+SETSPR 0x270 0x10030000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number C3F00000, I
+SETSPR 0x272 0xC3F0000A 0xFFFFFFFF
+// real page C3F00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xC3F0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// setup IVOPR
+// points to internal memory at 0x40000000
+SETSPR 0x3F 0x40000000 0xFFFFFFFF
+// MMU data error vector offset
+SETSPR 0x19D 0x0 0xFFFFFFFF
+// MMU instruction error vector offset
+
+// setup clock to 80MHz
+//SET FMPLL_SYNCR 0x28000000 0xFFFFFFFF
+//WAIT 0x5
+
+// disable watchdog
+SET SWT_CR 0xFF00000A
+
+// set NEXUS priority to above cpu instruction for runtime access
+//SET XBAR_MPR3 0x321
+
+[Controller0.Core.PpcJtagTargIntf.OnStartScript]
+
+[Controller0.Core.PpcJtagTargIntf.OnHaltScript]