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-rw-r--r--demos/ARMCM3-STM32F103-FATFS-GCC/board.c85
1 files changed, 6 insertions, 79 deletions
diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c
index bc384a544..58be4d77f 100644
--- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c
+++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c
@@ -17,35 +17,8 @@
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <ch.h>
-#include <pal.h>
-#include <serial.h>
-#include <spi.h>
-#include <mmc_spi.h>
-#include <stm32_dma.h>
-#include <nvic.h>
-
-#include "board.h"
-
-#define AIRCR_VECTKEY 0x05FA0000
-
-/*
- * Digital I/O ports static configuration as defined in @p board.h.
- */
-static const STM32GPIOConfig pal_config =
-{
- {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
- {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
- {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
- {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
-#if !defined(STM32F10X_LD)
- {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
-#endif
-#if defined(STM32F10X_HD)
- {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
- {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
-#endif
-};
+#include "ch.h"
+#include "hal.h"
/*
* Early initialization code.
@@ -54,39 +27,7 @@ static const STM32GPIOConfig pal_config =
*/
void hwinit0(void) {
- /*
- * Clocks and PLL initialization.
- */
- // HSI setup.
- RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION;
- while (!(RCC->CR & RCC_CR_HSIRDY))
- ; // Waits until HSI stable, it should already be.
- // HSE setup.
- RCC->CR |= RCC_CR_HSEON;
- while (!(RCC->CR & RCC_CR_HSERDY))
- ; // Waits until HSE stable.
- // PLL setup.
- RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
- RCC->CR |= RCC_CR_PLLON;
- while (!(RCC->CR & RCC_CR_PLLRDY))
- ; // Waits until PLL stable.
- // Clock sources.
- RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 |
- RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 |
- RCC_CFGR_MCO_NOCLOCK | USBPREBITS;
-
- /*
- * Flash setup and final clock selection.
- */
- FLASH->ACR = FLASHBITS; // Flash wait states depending on clock.
- RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock.
- while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL)
- ;
-
- /*
- * I/O ports initialization as specified in board.h.
- */
- palInit(&pal_config);
+ stm32_clock_init();
}
/*
@@ -98,27 +39,13 @@ void hwinit1(void) {
/*
* NVIC/SCB initialization.
- * Note: PRIGROUP 4:0 (4:4).
- */
- SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1;
- NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL);
- NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK);
- NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV);
-
- /*
- * SysTick initialization.
*/
- SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
- SysTick->VAL = 0;
- SysTick->CTRL = SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT;
+ stm32_nvic_init();
/*
- * Other subsystems initialization.
+ * HAL initialization.
*/
- dmaInit();
- sdInit();
- spiInit();
- mmcInit();
+ halInit();
/*
* ChibiOS/RT initialization.