diff options
| -rw-r--r-- | os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R5xI.ld | 85 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx+/platform.mk | 32 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx+/stm32_isr.c | 255 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx+/stm32_isr.h | 152 |
4 files changed, 524 insertions, 0 deletions
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R5xI.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R5xI.ld new file mode 100644 index 000000000..d934b380f --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32L4R5xI.ld @@ -0,0 +1,85 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L4R5xI memory setup.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 2M
+ flash1 : org = 0x00000000, len = 0
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 640k /* SRAM1+SRAM2+SRAM3 */
+ ram1 : org = 0x20000000, len = 192k /* SRAM1 */
+ ram2 : org = 0x00000000, len = 64k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 384k /* SRAM3 */
+ ram4 : org = 0x10000000, len = 64k /* SRAM2 alias */
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/os/hal/ports/STM32/STM32L4xx+/platform.mk b/os/hal/ports/STM32/STM32L4xx+/platform.mk new file mode 100644 index 000000000..20ae83867 --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx+/platform.mk @@ -0,0 +1,32 @@ +# Required platform files.
+PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
+
+# Required include directories.
+PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx+
+
+# Optional platform files.
+ifeq ($(USE_SMART_BUILD),yes)
+
+# Configuration files directory
+ifeq ($(CONFDIR),)
+ CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define"))
+
+else
+endif
+
+# Drivers compatible with the platform.
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC += $(PLATFORMINC)
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c new file mode 100644 index 000000000..d087d8374 --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c @@ -0,0 +1,255 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx+/stm32_isr.h
+ * @brief STM32L4xx+ ISR handler code.
+ *
+ * @addtogroup SRM32L4xxp_ISR
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+#define exti_serve_irq(pr, channel) { \
+ \
+ if ((pr) & (1U << (channel))) { \
+ _pal_isr_code(channel); \
+ } \
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
+#if !defined(STM32_DISABLE_EXTI0_HANDLER)
+/**
+ * @brief EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 0);
+ EXTI->PR1 = pr;
+
+ exti_serve_irq(pr, 0);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI1_HANDLER)
+/**
+ * @brief EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 1);
+ EXTI->PR1 = pr;
+
+ exti_serve_irq(pr, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI2_HANDLER)
+/**
+ * @brief EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 2);
+ EXTI->PR1 = pr;
+
+ exti_serve_irq(pr, 2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI3_HANDLER)
+/**
+ * @brief EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 3);
+ EXTI->PR1 = pr;
+
+ exti_serve_irq(pr, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI4_HANDLER)
+/**
+ * @brief EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & (1U << 4);
+ EXTI->PR1 = pr;
+
+ exti_serve_irq(pr, 4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
+/**
+ * @brief EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
+ EXTI->PR1 = pr;
+
+ exti_serve_irq(pr, 5);
+ exti_serve_irq(pr, 6);
+ exti_serve_irq(pr, 7);
+ exti_serve_irq(pr, 8);
+ exti_serve_irq(pr, 9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
+/**
+ * @brief EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR1;
+ pr &= EXTI->IMR1 & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI->PR1 = pr;
+
+ exti_serve_irq(pr, 10);
+ exti_serve_irq(pr, 11);
+ exti_serve_irq(pr, 12);
+ exti_serve_irq(pr, 13);
+ exti_serve_irq(pr, 14);
+ exti_serve_irq(pr, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables IRQ sources.
+ *
+ * @notapi
+ */
+void irqInit(void) {
+
+#if HAL_USE_PAL
+ nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);
+ nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);
+ nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);
+ nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);
+ nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);
+ nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
+ nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Disables IRQ sources.
+ *
+ * @notapi
+ */
+void irqDeinit(void) {
+
+#if HAL_USE_PAL
+ nvicDisableVector(EXTI0_IRQn);
+ nvicDisableVector(EXTI1_IRQn);
+ nvicDisableVector(EXTI2_IRQn);
+ nvicDisableVector(EXTI3_IRQn);
+ nvicDisableVector(EXTI4_IRQn);
+ nvicDisableVector(EXTI9_5_IRQn);
+ nvicDisableVector(EXTI15_10_IRQn);
+#endif
+}
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h new file mode 100644 index 000000000..85c9f6fe4 --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h @@ -0,0 +1,152 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L4xx+/stm32_isr.h
+ * @brief STM32L4xx+ ISR handler header.
+ *
+ * @addtogroup SRM32L4xxp_ISR
+ * @{
+ */
+
+#ifndef STM32_ISR_H
+#define STM32_ISR_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI0_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI1 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI1_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI2 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI2_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI3 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI3_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI4 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI4_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI9..5 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI5_9_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI15..10 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI10_15_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI16-EXTI35..38 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI1635_38_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI1635_38_IRQ_PRIORIT 6
+#endif
+
+/**
+ * @brief EXTI18 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI18_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI19 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI19_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI20 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI20_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI20_PRIORITY 6
+#endif
+
+/**
+ * @brief EXTI21..22 interrupt priority level setting.
+ */
+#if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_IRQ_EXTI21_22_PRIORITY 6
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void irqInit(void);
+ void irqDeinit(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ISR_H */
+
+/** @} */
|