4 files changed, 65 insertions, 23 deletions
diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj
index f1c299a59..db526ff1b 100644
--- a/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj
+++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj
@@ -361,7 +361,7 @@
               <MiscControls>--cpreproc</MiscControls>
               <Define></Define>
               <Undefine></Undefine>
-              <IncludePath>..\..\..\boards\EA_LPCXPRESSO_BB_1114;..\..\..\os\ports\RVCT\ARMCMx\LPC11xx</IncludePath>
+              <IncludePath>..\;..\..\..\boards\EA_LPCXPRESSO_BB_1114;..\..\..\os\ports\RVCT\ARMCMx\LPC11xx</IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
diff --git a/docs/reports/LPC1114-48-RVCT.txt b/docs/reports/LPC1114-48-RVCT.txt
index 53953ee84..143522f39 100644
--- a/docs/reports/LPC1114-48-RVCT.txt
+++ b/docs/reports/LPC1114-48-RVCT.txt
@@ -6,9 +6,11 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation].
 
 *** ChibiOS/RT test suite
 ***
-*** Kernel:       2.3.0unstable
+*** Kernel:       2.3.4unstable
+*** Compiler:     RVCT
 *** Architecture: ARMv6-M
 *** Core Variant: Cortex-M0
+*** Port Info:    Preemption through NMI
 *** Platform:     LPC11xx
 *** Test Board:   Embedded Artists LPCXpresso Base Board + LPC1114
 
@@ -90,7 +92,7 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation].
 ----------------------------------------------------------------------------
 --- Test Case 9.3 (Dynamic APIs, registry and references)
 --- Result: SUCCESS
----------------------------------------------------------------------------
+----------------------------------------------------------------------------
 --- Test Case 10.1 (Queues, input queues)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
@@ -98,55 +100,55 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation].
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.1 (Benchmark, messages #1)
---- Score : 121347 msgs/S, 242694 ctxswc/S
+--- Score : 120730 msgs/S, 241460 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.2 (Benchmark, messages #2)
---- Score : 102162 msgs/S, 204324 ctxswc/S
+--- Score : 103037 msgs/S, 206074 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.3 (Benchmark, messages #3)
---- Score : 102162 msgs/S, 204324 ctxswc/S
+--- Score : 103037 msgs/S, 206074 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.4 (Benchmark, context switch)
---- Score : 377584 ctxswc/S
+--- Score : 383632 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 78768 threads/S
+--- Score : 79025 threads/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 112764 threads/S
+--- Score : 112230 threads/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 33088 reschedules/S, 198528 ctxswc/S
+--- Score : 33692 reschedules/S, 202152 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 249336 ctxswc/S
+--- Score : 236968 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 270084 bytes/S
+--- Score : 360780 bytes/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 303522 timers/S
+--- Score : 311418 timers/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 603212 wait+signal/S
+--- Score : 599396 wait+signal/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 372744 lock+unlock/S
+--- Score : 371284 lock+unlock/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.13 (Benchmark, RAM footprint)
---- System: 360 bytes
+--- System: 368 bytes
 --- Thread: 68 bytes
 --- Timer : 20 bytes
 --- Semaph: 12 bytes
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h
index bff8c4fe4..347588bbb 100644
--- a/os/ports/RVCT/ARMCMx/chcore_v6m.h
+++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h
@@ -45,6 +45,15 @@
 /* Port configurable parameters.                                             */
 /*===========================================================================*/
 
+/**
+ * @brief   Alternate preemption method.
+ * @details Activating this option will make the Kernel use the PendSV
+ *          handler for preemption instead of the NMI handler.
+ */
+#ifndef CORTEX_ALTERNATE_SWITCH
+#define CORTEX_ALTERNATE_SWITCH         FALSE
+#endif
+
 /*===========================================================================*/
 /* Port derived parameters.                                                  */
 /*===========================================================================*/
@@ -72,6 +81,15 @@
 #define CH_CORE_VARIANT_NAME            "Cortex-M1"
 #endif
 
+/**
+ * @brief   Port-specific information string.
+ */
+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
+#define CH_PORT_INFO                    "Preemption through NMI"
+#else
+#define CH_PORT_INFO                    "Preemption through PendSV"
+#endif
+
 /*===========================================================================*/
 /* Port implementation part.                                                 */
 /*===========================================================================*/
diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
index d3239575c..725189996 100644
--- a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
+++ b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
@@ -19,12 +19,11 @@
 */
 
 /*
- * Imports the Cortex-Mx parameters header and performs the same calculations
- * done in chcore.h.
+ * Imports the Cortex-Mx configuration headers.
  */
-#include "cmparams.h"
-
-#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
+#define _FROM_ASM_
+#include "chconf.h"
+#include "chcore.h"
 
 EXTCTX_SIZE     EQU     32
 CONTEXT_OFFSET  EQU     12
@@ -78,6 +77,7 @@ _port_thread_start PROC
  * The NMI vector is used for exception mode re-entering after a context
  * switch.
  */
+#if !CORTEX_ALTERNATE_SWITCH
                 EXPORT  NMIVector
 NMIVector       PROC
                 mrs     r3, PSP
@@ -86,6 +86,22 @@ NMIVector       PROC
                 cpsie   i
                 bx      lr
                 ENDP
+#endif
+
+/*
+ * NMI vector.
+ * The NMI vector is used for exception mode re-entering after a context
+ * switch.
+ */
+#if CORTEX_ALTERNATE_SWITCH
+                EXPORT  PendSVVector
+PendSVVector       PROC
+                mrs     r3, PSP
+                adds    r3, r3, #32
+                msr     PSP, r3
+                bx      lr
+                ENDP
+#endif
 
 /*
  * Post-IRQ switch code.
@@ -94,11 +110,17 @@ NMIVector       PROC
                 EXPORT  _port_switch_from_isr
 _port_switch_from_isr PROC
                 bl      chSchDoRescheduleI
+                ldr     r2, =SCB_ICSR
                 movs    r3, #128
+#if CORTEX_ALTERNATE_SWITCH
+                lsls    r3, r3, #20
+                str     r3, [r2, #0]
+                cpsie   i
+#else
                 lsls    r3, r3, #24
-                ldr     r2, =SCB_ICSR
                 str     r3, [r2, #0]
-_waitnmi        b       _waitnmi
+#endif
+waithere        b       waithere
                 ENDP
 
 /*