diff options
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 29 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h | 7 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt | 26 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c | 587 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h | 399 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c | 346 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h | 71 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv3/driver.mk | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv3/notes.txt | 12 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c | 547 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h | 590 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/platform.mk | 2 | ||||
| -rw-r--r-- | readme.txt | 3 | ||||
| -rw-r--r-- | testhal/STM32/multi/SPI/debug/STM32-SPI (Select ELF file)(OpenOCD, Flash and Run).launch | 104 |
15 files changed, 370 insertions, 2357 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index 3b8e5769d..f6ede4a6a 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -50,11 +50,6 @@ #define STM32_DMA2_STREAMS_MASK (((1U << STM32_DMA2_NUM_CHANNELS) - \
1U) << STM32_DMA1_NUM_CHANNELS)
-/**
- * @brief Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE 0x00000000U
-
#if STM32_DMA_SUPPORTS_CSELR == TRUE
#if defined(DMA1_CSELR)
@@ -118,7 +113,7 @@ #define DMA2_CH6_VARIANT 0
#define DMA2_CH7_VARIANT 0
-#endif /* !defined(DMA1_CSELR) */
+#endif /* !(STM32_DMA_SUPPORTS_DMAMUX == TRUE) */
/*
* Default ISR collision masks.
@@ -495,7 +490,7 @@ void dmaInit(void) { dma.allocated_mask = 0U;
dma.isr_mask = 0U;
for (i = 0; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].channel->CCR = 0U;
+ _stm32_dma_streams[i].channel->CCR = STM32_DMA_CCR_RESET_VALUE;
dma.streams[i].func = NULL;
}
DMA1->IFCR = 0xFFFFFFFFU;
@@ -547,7 +542,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, }
else if (id == STM32_DMA_STREAM_ID_ANY) {
startid = 0U;
- endid = STM32_DMA1_NUM_CHANNELS + STM32_DMA2_NUM_CHANNELS - 1U;
+ endid = STM32_DMA_STREAMS - 1U;
}
else if (id == STM32_DMA_STREAM_ID_ANY_DMA1) {
startid = 0U;
@@ -556,7 +551,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, #if STM32_DMA2_NUM_CHANNELS > 0
else if (id == STM32_DMA_STREAM_ID_ANY_DMA2) {
startid = 7U;
- endid = STM32_DMA1_NUM_CHANNELS + STM32_DMA2_NUM_CHANNELS - 1U;
+ endid = STM32_DMA_STREAMS - 1U;
}
#endif
else {
@@ -571,22 +566,21 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, /* Installs the DMA handler.*/
dma.streams[i].func = func;
dma.streams[i].param = param;
+ dma.allocated_mask |= mask;
/* Enabling DMA clocks required by the current streams set.*/
- if (((STM32_DMA1_STREAMS_MASK & dma.allocated_mask) == 0U) &&
- ((STM32_DMA1_STREAMS_MASK & mask) != 0U)){
+ if ((STM32_DMA1_STREAMS_MASK & mask) != 0U) {
rccEnableDMA1(true);
}
#if STM32_DMA2_NUM_CHANNELS > 0
- if (((STM32_DMA2_STREAMS_MASK & dma.allocated_mask) == 0U) &&
- ((STM32_DMA2_STREAMS_MASK & mask) != 0U)){
+ if ((STM32_DMA2_STREAMS_MASK & mask) != 0U) {
rccEnableDMA2(true);
}
#endif
-#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(rccEnableDMAMUX)
/* Enabling DMAMUX if present.*/
- if (dma.allocated_mask == 0U) {
+ if (dma.allocated_mask != 0U) {
rccEnableDMAMUX(true);
}
#endif
@@ -600,9 +594,6 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id, dma.isr_mask |= mask;
}
- /* Marks the stream as allocated.*/
- dma.allocated_mask |= mask;
-
/* Putting the stream in a known state.*/
dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
@@ -690,7 +681,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { }
#endif
-#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(rccDisableDMAMUX)
/* Shutting down DMAMUX if present.*/
if (dma.allocated_mask == 0U) {
rccDisableDMAMUX();
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h index 4fe24c631..3316f19f7 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h @@ -124,9 +124,9 @@ * @name Special stream identifiers
* @{
*/
-#define STM32_DMA_STREAM_ID_ANY 16
-#define STM32_DMA_STREAM_ID_ANY_DMA1 17
-#define STM32_DMA_STREAM_ID_ANY_DMA2 18
+#define STM32_DMA_STREAM_ID_ANY STM32_DMA_STREAMS
+#define STM32_DMA_STREAM_ID_ANY_DMA1 (STM32_DMA_STREAM_ID_ANY + 1)
+#define STM32_DMA_STREAM_ID_ANY_DMA2 (STM32_DMA_STREAM_ID_ANY_DMA1 + 1)
/** @} */
/**
@@ -162,6 +162,7 @@ * @name CR register constants common to all DMA types
* @{
*/
+#define STM32_DMA_CCR_RESET_VALUE 0x00000000U
#define STM32_DMA_CR_EN DMA_CCR_EN
#define STM32_DMA_CR_TEIE DMA_CCR_TEIE
#define STM32_DMA_CR_HTIE DMA_CCR_HTIE
diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk b/os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk deleted file mode 100644 index 6080cec58..000000000 --- a/os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk +++ /dev/null @@ -1,2 +0,0 @@ -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
-PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1
diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt b/os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt deleted file mode 100644 index dc4663890..000000000 --- a/os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt +++ /dev/null @@ -1,26 +0,0 @@ -STM32 DMAv1 driver.
-
-Driver capability:
-
-- The driver supports the STM32 traditional DMA controller in the following
- configurations: 5ch, 7ch, 7ch+5ch, 7ch+7ch.
-- Support for automatic the channel selection through the CSELR register.
-- For devices without CSELR register it is possible to select channels but
- the SYSCFG CFGR register is not configured, the user has to configure it
- before starting the DMA driver.
-- The driver supports shared ISR handlers with a quirk: the IRQ priority is
- established by the first allocated channel among the channels sharing the
- ISR.
-
-The file registry must export:
-
-STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other
- drivers use it to enable checks on DMA
- channels. Probably will be removed in the
- future.
-STM32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register.
-STM32_DMA_SUPPORTS_DMAMUX - TRUE if the DMA is riven by a DMAMUX.
-STM32_DMAn_NUM_CHANNELS - Number of channels in DMAs "n" (1..2).
-STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x" (1..7). If the macro
- is not exported then the ISR is not declared.
-STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x" (1..7).
diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c deleted file mode 100644 index c1e0d623c..000000000 --- a/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c +++ /dev/null @@ -1,587 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DMAv1_MUX/stm32_dma.c
- * @brief DMA helper driver code.
- *
- * @addtogroup STM32_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- * shared resource, this driver allows to allocate and free DMA
- * streams at runtime in order to allow all the other device
- * drivers to coordinate the access to the resource.
- * @note The DMA ISR handlers are all declared into this module because
- * sharing, the various device drivers can associate a callback to
- * ISRs when allocating streams.
- * @{
- */
-
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
- has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/**
- * @brief Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK ((1U << STM32_DMA1_NUM_CHANNELS) - 1U)
-
-/**
- * @brief Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK (((1U << STM32_DMA2_NUM_CHANNELS) - 1U) << 8U)
-
-/**
- * @brief Mask of all DMA streams.
- */
-#define STM32_DMA_STREAMS_MASK (STM32_DMA1_STREAMS_MASK | STM32_DMA2_STREAMS_MASK)
-
-/**
- * @brief Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE 0x00000000U
-
-/*
- * Default ISR collision masks.
- */
-#if !defined(DMA1_CH1_CMASK)
-#define DMA1_CH1_CMASK 0x00000001U
-#endif
-
-#if !defined(DMA1_CH2_CMASK)
-#define DMA1_CH2_CMASK 0x00000002U
-#endif
-
-#if !defined(DMA1_CH3_CMASK)
-#define DMA1_CH3_CMASK 0x00000004U
-#endif
-
-#if !defined(DMA1_CH4_CMASK)
-#define DMA1_CH4_CMASK 0x00000008U
-#endif
-
-#if !defined(DMA1_CH5_CMASK)
-#define DMA1_CH5_CMASK 0x00000010U
-#endif
-
-#if !defined(DMA1_CH6_CMASK)
-#define DMA1_CH6_CMASK 0x00000020U
-#endif
-
-#if !defined(DMA1_CH7_CMASK)
-#define DMA1_CH7_CMASK 0x00000040U
-#endif
-
-#if !defined(DMA2_CH1_CMASK)
-#define DMA2_CH1_CMASK 0x00000080U
-#endif
-
-#if !defined(DMA2_CH2_CMASK)
-#define DMA2_CH2_CMASK 0x00000100U
-#endif
-
-#if !defined(DMA2_CH3_CMASK)
-#define DMA2_CH3_CMASK 0x00000200U
-#endif
-
-#if !defined(DMA2_CH4_CMASK)
-#define DMA2_CH4_CMASK 0x00000400U
-#endif
-
-#if !defined(DMA2_CH5_CMASK)
-#define DMA2_CH5_CMASK 0x00000800U
-#endif
-
-#if !defined(DMA2_CH6_CMASK)
-#define DMA2_CH6_CMASK 0x00001000U
-#endif
-
-#if !defined(DMA2_CH7_CMASK)
-#define DMA2_CH7_CMASK 0x00002000U
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- * identifier and the involved physical registers.
- * @note Don't use this array directly, use the appropriate wrapper macros
- * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1, DMA1_Channel1, DMA1_CH1_CMASK, DMAMUX1_Channel0, 0, 0, STM32_DMA1_CH1_NUMBER},
- {DMA1, DMA1_Channel2, DMA1_CH2_CMASK, DMAMUX1_Channel1, 4, 1, STM32_DMA1_CH2_NUMBER},
- {DMA1, DMA1_Channel3, DMA1_CH3_CMASK, DMAMUX1_Channel2, 8, 2, STM32_DMA1_CH3_NUMBER},
- {DMA1, DMA1_Channel4, DMA1_CH4_CMASK, DMAMUX1_Channel3, 12, 3, STM32_DMA1_CH4_NUMBER},
- {DMA1, DMA1_Channel5, DMA1_CH5_CMASK, DMAMUX1_Channel4, 16, 4, STM32_DMA1_CH5_NUMBER},
-#if STM32_DMA1_NUM_CHANNELS > 5
- {DMA1, DMA1_Channel6, DMA1_CH6_CMASK, DMAMUX1_Channel5, 20, 5, STM32_DMA1_CH6_NUMBER},
-#endif
-#if STM32_DMA1_NUM_CHANNELS > 6
- {DMA1, DMA1_Channel7, DMA1_CH7_CMASK, DMAMUX1_Channel6, 24, 6, STM32_DMA1_CH7_NUMBER},
-#endif
-#if STM32_DMA2_NUM_CHANNELS > 0
- {DMA2, DMA2_Channel1, DMA2_CH1_CMASK, DMAMUX1_Channel7, 0, 7, STM32_DMA2_CH1_NUMBER},
- {DMA2, DMA2_Channel2, DMA2_CH2_CMASK, DMAMUX1_Channel8, 4, 8, STM32_DMA2_CH2_NUMBER},
- {DMA2, DMA2_Channel3, DMA2_CH3_CMASK, DMAMUX1_Channel9, 8, 9, STM32_DMA2_CH3_NUMBER},
- {DMA2, DMA2_Channel4, DMA2_CH4_CMASK, DMAMUX1_Channel10, 12, 10, STM32_DMA2_CH4_NUMBER},
- {DMA2, DMA2_Channel5, DMA2_CH5_CMASK, DMAMUX1_Channel11, 16, 11, STM32_DMA2_CH5_NUMBER},
-#endif
-#if STM32_DMA2_NUM_CHANNELS > 5
- {DMA2, DMA2_Channel6, DMA2_CH6_CMASK, DMAMUX1_Channel12, 20, 12, STM32_DMA2_CH6_NUMBER},
-#endif
-#if STM32_DMA2_NUM_CHANNELS > 6
- {DMA2, DMA2_Channel7, DMA2_CH7_CMASK, DMAMUX1_Channel13, 24, 13, STM32_DMA2_CH7_NUMBER},
-#endif
-};
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Global DMA-related data structures.
- */
-static struct {
- /**
- * @brief Mask of the allocated streams.
- */
- uint32_t allocated_mask;
- /**
- * @brief Mask of the enabled streams ISRs.
- */
- uint32_t isr_mask;
- /**
- * @brief DMA IRQ redirectors.
- */
- struct {
- /**
- * @brief DMA callback function.
- */
- stm32_dmaisr_t func;
- /**
- * @brief DMA callback parameter.
- */
- void *param;
- } streams[STM32_DMA_STREAMS];
-} dma;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if defined(STM32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA1 stream 1 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA1_STREAM1);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA1 stream 2 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA1_STREAM2);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA1 stream 3 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA1_STREAM3);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA1 stream 4 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA1_STREAM4);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA1_CH5_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA1 stream 5 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA1_STREAM5);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA1_CH6_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA1 stream 6 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA1_STREAM6);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA1_CH7_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA1 stream 7 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA1_STREAM7);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 1 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA2_STREAM1);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 2 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA2_STREAM2);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 3 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA2_STREAM3);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 4 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA2_STREAM4);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 5 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA2_STREAM5);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA2_CH6_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 6 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA2_STREAM6);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if defined(STM32_DMA2_CH7_HANDLER) || defined(__DOXYGEN__)
-/**
- * @brief DMA2 stream 7 shared ISR.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
-
- OSAL_IRQ_PROLOGUE();
-
- dmaServeInterrupt(STM32_DMA2_STREAM7);
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
- int i;
-
- dma.streams_mask = 0U;
- dma.isr_mask = 0U;
- for (i = 0; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].channel->CCR = STM32_DMA_CCR_RESET_VALUE;
- }
- DMA1->IFCR = 0xFFFFFFFFU;
-#if STM32_DMA2_NUM_CHANNELS > 0
- DMA2->IFCR = 0xFFFFFFFFU;
-#endif
-}
-
-/**
- * @brief Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- * The function also enables the IRQ vector associated to the stream
- * and initializes its priority.
- * @pre The stream must not be already in use or an error is returned.
- * @post The stream is allocated and the default ISR handler redirected
- * to the specified function.
- * @post The stream ISR vector is enabled and its priority configured.
- * @post The stream must be freed using @p dmaStreamRelease() before it can
- * be reused with another peripheral.
- * @post The stream is in its post-reset state.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] priority IRQ priority for the DMA stream
- * @param[in] func handling function pointer, can be @p NULL
- * @param[in] param a parameter to be passed to the handling function
- * @return The allocated @p stm32_dma_stream_t object.
- * @retval NULL no stream available.
- *
- * @special
- */
-const stm32_dma_stream_t *dmaStreamAllocate(uint32_t priority,
- stm32_dmaisr_t func,
- void *param) {
-
- /* Checks if the stream is already taken.*/
- if ((dma.streams_mask & (1U << dmastp->selfindex)) != 0U)
- return true;
-
- /* Installs the DMA handler.*/
- _stm32_dma_isr_redir[dmastp->selfindex].dma_func = func;
- _stm32_dma_isr_redir[dmastp->selfindex].dma_param = param;
-
- /* Enabling DMA clocks required by the current streams set.*/
- if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
- rccEnableDMA1(true);
- }
-#if STM32_DMA2_NUM_CHANNELS > 0
- if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
- rccEnableDMA2(true);
- }
-#endif
-
-#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
- /* Enabling DMAMUX if present.*/
- if (dma.streams_mask == 0U) {
- rccEnableDMAMUX(true);
- }
-#endif
-
- /* Putting the stream in a safe state.*/
- dmaStreamDisable(dmastp);
- dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
- /* Enables the associated IRQ vector if not already enabled and if a
- callback is defined.*/
- if (func != NULL) {
- if ((dma.isr_mask & dmastp->cmask) == 0U) {
- nvicEnableVector(dmastp->vector, priority);
- }
- dma.isr_mask |= (1U << dmastp->selfindex);
- }
-
- /* Marks the stream as allocated.*/
- dma.streams_mask |= (1U << dmastp->selfindex);
-
- return false;
-}
-
-/**
- * @brief Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- * Trying to release a unallocated stream is an illegal operation
- * and is trapped if assertions are enabled.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post The stream is again available.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
- osalDbgCheck(dmastp != NULL);
-
- /* Check if the streams is not taken.*/
- osalDbgAssert((dma.streams_mask & (1 << dmastp->selfindex)) != 0U,
- "not allocated");
-
- /* Marks the stream as not allocated.*/
- dma.streams_mask &= ~(1U << dmastp->selfindex);
- dma.isr_mask &= ~(1U << dmastp->selfindex);
-
- /* Disables the associated IRQ vector if it is no more in use.*/
- if ((dma.streams_mask & dmastp->cmask) == 0U) {
- nvicDisableVector(dmastp->vector);
- }
-
- /* Removes the DMA handler.*/
- _stm32_dma_isr_redir[dmastp->selfindex].dma_func = NULL;
- _stm32_dma_isr_redir[dmastp->selfindex].dma_param = NULL;
-
- /* Shutting down clocks that are no more required, if any.*/
- if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
- rccDisableDMA1();
- }
-#if STM32_DMA2_NUM_CHANNELS > 0
- if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
- rccDisableDMA2();
- }
-#endif
-
-#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
- /* Shutting down DMAMUX if present.*/
- if (dma.streams_mask == 0U) {
- rccDisableDMAMUX();
- }
-#endif
-}
-
-#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
-/**
- * @brief Associates a peripheral request to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a @p stm32_dma_stream_t structure
- * @param[in] per peripheral identifier
- *
- * @special
- */
-void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) {
-
- osalDbgCheck(per < 256U);
-
- dmastp->mux->CCR = per;
-}
-#endif
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h deleted file mode 100644 index b7cc3b999..000000000 --- a/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h +++ /dev/null @@ -1,399 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DMAv1_MUX/stm32_dma.h
- * @brief DMA helper driver header.
- * @note This driver uses the new naming convention used for the STM32F2xx
- * so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32_DMA
- * @{
- */
-
-#ifndef STM32_DMA_H
-#define STM32_DMA_H
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief DMA capability.
- * @details if @p TRUE then the DMA is able of burst transfers, FIFOs,
- * scatter gather and other advanced features.
- */
-#define STM32_DMA_ADVANCED FALSE
-
-/**
- * @brief Total number of DMA streams.
- * @details This is the total number of streams among all the DMA units.
- */
-#define STM32_DMA_STREAMS (STM32_DMA1_NUM_CHANNELS + \
- STM32_DMA2_NUM_CHANNELS)
-
-/**
- * @brief Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK 0x0E
-
-/**
- * @brief From stream number to shift factor in @p ISR and @p IFCR registers.
- */
-#define STM32_DMA_ISR_SHIFT(stream) (((stream) - 1U) * 4U)
-
-/**
- * @brief Checks if a DMA priority is within the valid range.
- * @param[in] prio DMA priority
- *
- * @retval The check result.
- * @retval false invalid DMA priority.
- * @retval true correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
-
-/**
- * @brief Checks if a DMA channel is within the valid range.
- *
- * @param[in] ch DMA channel
- * @retval The check result.
- * @retval FALSE invalid DMA channel.
- * @retval TRUE correct DMA channel.
- */
-#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && ((ch) < STM32_DMA_STREAMS))
-
-/**
- * @name CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN DMA_CCR_EN
-#define STM32_DMA_CR_TEIE DMA_CCR_TEIE
-#define STM32_DMA_CR_HTIE DMA_CCR_HTIE
-#define STM32_DMA_CR_TCIE DMA_CCR_TCIE
-#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M 0U
-#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR
-#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM
-#define STM32_DMA_CR_CIRC DMA_CCR_CIRC
-#define STM32_DMA_CR_PINC DMA_CCR_PINC
-#define STM32_DMA_CR_MINC DMA_CCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE 0U
-#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE 0U
-#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
- STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK DMA_CCR_PL
-#define STM32_DMA_CR_PL(n) ((n) << 12U)
-/** @} */
-
-/**
- * @name Request line selector macro
- * @{
- */
-#define STM32_DMA_CR_CHSEL_MASK 0U
-#define STM32_DMA_CR_CHSEL(n) 0U
-/** @} */
-
-/**
- * @name CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE 0U /**< @brief Ignored by normal DMA. */
-/** @} */
-
-/**
- * @name Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF 0U
-#define STM32_DMA_ISR_DMEIF 0U
-#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !defined(STM32_DMA_SUPPORTS_DMAMUX)
-#error "STM32_DMA_SUPPORTS_DMAMUX not defined in registry"
-#endif
-
-#if STM32_DMA_SUPPORTS_DMAMUX == FALSE
-#error "this driver requires a DMAMUX unit"
-#else
-#include "stm32_dmamux.h"
-#endif
-
-#if !defined(STM32_DMA1_NUM_CHANNELS)
-#error "STM32_DMA1_NUM_CHANNELS not defined in registry"
-#endif
-
-#if !defined(STM32_DMA2_NUM_CHANNELS)
-#error "STM32_DMA2_NUM_CHANNELS not defined in registry"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a DMA callback.
- *
- * @param[in] p parameter for the registered function
- * @param[in] flags pre-shifted content of the ISR register, the bits
- * are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/**
- * @brief Type of a DMA stream descriptor structure.
- */
-typedef struct {
- DMA_TypeDef *dma ; /**< @brief Associated DMA. */
- DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
- uint32_t cmask; /**< @brief Mask of streams sharing
- the same ISR. */
- DMAMUX_Channel_TypeDef *mux; /**< @brief Associated DMA mux. */
- uint8_t shift; /**< @brief Bit offset in ISR, IFCR
- and CSELR registers. */
- uint8_t selfindex; /**< @brief Index to self in array. */
- uint8_t vector; /**< @brief Associated IRQ vector. */
-} stm32_dma_stream_t;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Associates a peripheral data register to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] addr value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) { \
- (dmastp)->channel->CPAR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Associates a memory destination to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] addr value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) { \
- (dmastp)->channel->CMAR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Sets the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] size value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) { \
- (dmastp)->channel->CNDTR = (uint32_t)(size); \
-}
-
-/**
- * @brief Returns the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @return The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief Programs the stream mode settings.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) { \
- (dmastp)->channel->CCR = (uint32_t)(mode); \
-}
-
-/**
- * @brief DMA stream enable.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) { \
- (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
-}
-
-/**
- * @brief DMA stream disable.
- * @details The function disables the specified stream and then clears any
- * pending interrupt.
- * @note This function can be invoked in both ISR or thread context.
- * @note Interrupts enabling flags are set to zero after this call, see
- * bug 3607518.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) { \
- (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \
- dmaStreamClearInterrupt(dmastp); \
-}
-
-/**
- * @brief DMA stream interrupt sources clear.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) { \
- (dmastp)->dma->IFCR = STM32_DMA_ISR_MASK << (dmastp)->shift; \
-}
-
-/**
- * @brief Starts a memory to memory operation using the specified stream.
- * @note The default transfer data mode is "byte to byte" but it can be
- * changed by specifying extra options in the @p mode parameter.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CCR register, this value
- * is implicitly ORed with:
- * - @p STM32_DMA_CR_MINC
- * - @p STM32_DMA_CR_PINC
- * - @p STM32_DMA_CR_DIR_M2M
- * - @p STM32_DMA_CR_EN
- * .
- * @param[in] src source address
- * @param[in] dst destination address
- * @param[in] n number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
- dmaStreamSetPeripheral(dmastp, src); \
- dmaStreamSetMemory0(dmastp, dst); \
- dmaStreamSetTransactionSize(dmastp, n); \
- dmaStreamSetMode(dmastp, (mode) | \
- STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
- STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
-}
-
-/**
- * @brief Polled wait for DMA transfer end.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) { \
- while ((dmastp)->channel->CNDTR > 0U) \
- ; \
- dmaStreamDisable(dmastp); \
-}
-
-/**
- * @brief Serves a DMA IRQ.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- */
-#define dmaServeInterrupt(dmastp) { \
- uint32_t flags; \
- uint32_t idx = (dmastp)->selfindex; \
- \
- flags = ((dmastp)->dma->ISR >> (dmastp)->shift) & STM32_DMA_ISR_MASK; \
- if (flags & (dmastp)->channel->CCR) { \
- (dmastp)->dma->IFCR = flags << (dmastp)->shift; \
- if (_stm32_dma_isr_redir[idx].dma_func) { \
- _stm32_dma_isr_redir[idx].dma_func(_stm32_dma_isr_redir[idx].dma_param, flags); \
- } \
- } \
-}
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void dmaInit(void);
- const stm32_dma_stream_t *dmaStreamAllocate(uint32_t priority,
- stm32_dmaisr_t func,
- void *param);
- void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
- void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_DMA_H */
-
-/** @} */
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c index 2d4f001c4..c048036a8 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c @@ -40,15 +40,56 @@ /*===========================================================================*/
/**
- * @brief Mask of the DMA1 streams in @p dma_streams_mask.
+ * @brief Mask of the DMA1 streams in @p dma.allocated_mask.
*/
#define STM32_DMA1_STREAMS_MASK 0x000000FFU
/**
- * @brief Mask of the DMA2 streams in @p dma_streams_mask.
+ * @brief Mask of the DMA2 streams in @p dma.allocated_mask.
*/
#define STM32_DMA2_STREAMS_MASK 0x0000FF00U
+
+#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
+
+#define DMA1_CH0_VARIANT DMAMUX1_Channel0
+#define DMA1_CH1_VARIANT DMAMUX1_Channel1
+#define DMA1_CH2_VARIANT DMAMUX1_Channel2
+#define DMA1_CH3_VARIANT DMAMUX1_Channel3
+#define DMA1_CH4_VARIANT DMAMUX1_Channel4
+#define DMA1_CH5_VARIANT DMAMUX1_Channel5
+#define DMA1_CH6_VARIANT DMAMUX1_Channel6
+#define DMA1_CH7_VARIANT DMAMUX1_Channel7
+#define DMA2_CH0_VARIANT DMAMUX1_Channel8
+#define DMA2_CH1_VARIANT DMAMUX1_Channel9
+#define DMA2_CH2_VARIANT DMAMUX1_Channel10
+#define DMA2_CH3_VARIANT DMAMUX1_Channel11
+#define DMA2_CH4_VARIANT DMAMUX1_Channel12
+#define DMA2_CH5_VARIANT DMAMUX1_Channel13
+#define DMA2_CH6_VARIANT DMAMUX1_Channel14
+#define DMA2_CH7_VARIANT DMAMUX1_Channel15
+
+#else /* !(STM32_DMA_SUPPORTS_DMAMUX == TRUE) */
+
+#define DMA1_CH0_VARIANT 0
+#define DMA1_CH1_VARIANT 0
+#define DMA1_CH2_VARIANT 0
+#define DMA1_CH3_VARIANT 0
+#define DMA1_CH4_VARIANT 0
+#define DMA1_CH5_VARIANT 0
+#define DMA1_CH6_VARIANT 0
+#define DMA1_CH7_VARIANT 0
+#define DMA2_CH0_VARIANT 0
+#define DMA2_CH1_VARIANT 0
+#define DMA2_CH2_VARIANT 0
+#define DMA2_CH3_VARIANT 0
+#define DMA2_CH4_VARIANT 0
+#define DMA2_CH5_VARIANT 0
+#define DMA2_CH6_VARIANT 0
+#define DMA2_CH7_VARIANT 0
+
+#endif /* !(STM32_DMA_SUPPORTS_DMAMUX == TRUE) */
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -61,22 +102,22 @@ * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1_Stream0, &DMA1->LIFCR, 0, 0, STM32_DMA1_CH0_NUMBER},
- {DMA1_Stream1, &DMA1->LIFCR, 6, 1, STM32_DMA1_CH1_NUMBER},
- {DMA1_Stream2, &DMA1->LIFCR, 16, 2, STM32_DMA1_CH2_NUMBER},
- {DMA1_Stream3, &DMA1->LIFCR, 22, 3, STM32_DMA1_CH3_NUMBER},
- {DMA1_Stream4, &DMA1->HIFCR, 0, 4, STM32_DMA1_CH4_NUMBER},
- {DMA1_Stream5, &DMA1->HIFCR, 6, 5, STM32_DMA1_CH5_NUMBER},
- {DMA1_Stream6, &DMA1->HIFCR, 16, 6, STM32_DMA1_CH6_NUMBER},
- {DMA1_Stream7, &DMA1->HIFCR, 22, 7, STM32_DMA1_CH7_NUMBER},
- {DMA2_Stream0, &DMA2->LIFCR, 0, 8, STM32_DMA2_CH0_NUMBER},
- {DMA2_Stream1, &DMA2->LIFCR, 6, 9, STM32_DMA2_CH1_NUMBER},
- {DMA2_Stream2, &DMA2->LIFCR, 16, 10, STM32_DMA2_CH2_NUMBER},
- {DMA2_Stream3, &DMA2->LIFCR, 22, 11, STM32_DMA2_CH3_NUMBER},
- {DMA2_Stream4, &DMA2->HIFCR, 0, 12, STM32_DMA2_CH4_NUMBER},
- {DMA2_Stream5, &DMA2->HIFCR, 6, 13, STM32_DMA2_CH5_NUMBER},
- {DMA2_Stream6, &DMA2->HIFCR, 16, 14, STM32_DMA2_CH6_NUMBER},
- {DMA2_Stream7, &DMA2->HIFCR, 22, 15, STM32_DMA2_CH7_NUMBER},
+ {DMA1_Stream0, &DMA1->LIFCR, DMA1_CH0_VARIANT, 0, 0, STM32_DMA1_CH0_NUMBER},
+ {DMA1_Stream1, &DMA1->LIFCR, DMA1_CH1_VARIANT, 6, 1, STM32_DMA1_CH1_NUMBER},
+ {DMA1_Stream2, &DMA1->LIFCR, DMA1_CH2_VARIANT, 16, 2, STM32_DMA1_CH2_NUMBER},
+ {DMA1_Stream3, &DMA1->LIFCR, DMA1_CH3_VARIANT, 22, 3, STM32_DMA1_CH3_NUMBER},
+ {DMA1_Stream4, &DMA1->HIFCR, DMA1_CH4_VARIANT, 0, 4, STM32_DMA1_CH4_NUMBER},
+ {DMA1_Stream5, &DMA1->HIFCR, DMA1_CH5_VARIANT, 6, 5, STM32_DMA1_CH5_NUMBER},
+ {DMA1_Stream6, &DMA1->HIFCR, DMA1_CH6_VARIANT, 16, 6, STM32_DMA1_CH6_NUMBER},
+ {DMA1_Stream7, &DMA1->HIFCR, DMA1_CH7_VARIANT, 22, 7, STM32_DMA1_CH7_NUMBER},
+ {DMA2_Stream0, &DMA2->LIFCR, DMA2_CH0_VARIANT, 0, 8, STM32_DMA2_CH0_NUMBER},
+ {DMA2_Stream1, &DMA2->LIFCR, DMA2_CH1_VARIANT, 6, 9, STM32_DMA2_CH1_NUMBER},
+ {DMA2_Stream2, &DMA2->LIFCR, DMA2_CH2_VARIANT, 16, 10, STM32_DMA2_CH2_NUMBER},
+ {DMA2_Stream3, &DMA2->LIFCR, DMA2_CH3_VARIANT, 22, 11, STM32_DMA2_CH3_NUMBER},
+ {DMA2_Stream4, &DMA2->HIFCR, DMA2_CH4_VARIANT, 0, 12, STM32_DMA2_CH4_NUMBER},
+ {DMA2_Stream5, &DMA2->HIFCR, DMA2_CH5_VARIANT, 6, 13, STM32_DMA2_CH5_NUMBER},
+ {DMA2_Stream6, &DMA2->HIFCR, DMA2_CH6_VARIANT, 16, 14, STM32_DMA2_CH6_NUMBER},
+ {DMA2_Stream7, &DMA2->HIFCR, DMA2_CH7_VARIANT, 22, 15, STM32_DMA2_CH7_NUMBER},
};
/*===========================================================================*/
@@ -84,22 +125,27 @@ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { /*===========================================================================*/
/**
- * @brief DMA ISR redirector type.
- */
-typedef struct {
- stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
- void *dma_param; /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief DMA IRQ redirectors.
+ * @brief Global DMA-related data structures.
*/
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+static struct {
+ /**
+ * @brief Mask of the allocated streams.
+ */
+ uint32_t allocated_mask;
+ /**
+ * @brief DMA IRQ redirectors.
+ */
+ struct {
+ /**
+ * @brief DMA callback function.
+ */
+ stm32_dmaisr_t func;
+ /**
+ * @brief DMA callback parameter.
+ */
+ void *param;
+ } streams[STM32_DMA_STREAMS];
+} dma;
/*===========================================================================*/
/* Driver local functions. */
@@ -121,8 +167,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH0_HANDLER) { flags = (DMA1->LISR >> 0U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 0U;
- if (dma_isr_redir[0].dma_func)
- dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+ if (dma.streams[0].func)
+ dma.streams[0].func(dma.streams[0].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -139,8 +185,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) { flags = (DMA1->LISR >> 6U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 6U;
- if (dma_isr_redir[1].dma_func)
- dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+ if (dma.streams[1].func)
+ dma.streams[1].func(dma.streams[1].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -157,8 +203,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) { flags = (DMA1->LISR >> 16U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 16U;
- if (dma_isr_redir[2].dma_func)
- dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+ if (dma.streams[2].func)
+ dma.streams[2].func(dma.streams[2].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -175,8 +221,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) { flags = (DMA1->LISR >> 22U) & STM32_DMA_ISR_MASK;
DMA1->LIFCR = flags << 22U;
- if (dma_isr_redir[3].dma_func)
- dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+ if (dma.streams[3].func)
+ dma.streams[3].func(dma.streams[3].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -193,8 +239,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) { flags = (DMA1->HISR >> 0U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 0U;
- if (dma_isr_redir[4].dma_func)
- dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+ if (dma.streams[4].func)
+ dma.streams[4].func(dma.streams[4].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -211,8 +257,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) { flags = (DMA1->HISR >> 6U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 6U;
- if (dma_isr_redir[5].dma_func)
- dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+ if (dma.streams[5].func)
+ dma.streams[5].func(dma.streams[5].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -229,8 +275,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) { flags = (DMA1->HISR >> 16U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 16U;
- if (dma_isr_redir[6].dma_func)
- dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+ if (dma.streams[6].func)
+ dma.streams[6].func(dma.streams[6].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -247,8 +293,8 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) { flags = (DMA1->HISR >> 22U) & STM32_DMA_ISR_MASK;
DMA1->HIFCR = flags << 22U;
- if (dma_isr_redir[7].dma_func)
- dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
+ if (dma.streams[7].func)
+ dma.streams[7].func(dma.streams[7].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -265,8 +311,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH0_HANDLER) { flags = (DMA2->LISR >> 0U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 0U;
- if (dma_isr_redir[8].dma_func)
- dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
+ if (dma.streams[8].func)
+ dma.streams[8].func(dma.streams[8].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -283,8 +329,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) { flags = (DMA2->LISR >> 6U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 6U;
- if (dma_isr_redir[9].dma_func)
- dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
+ if (dma.streams[9].func)
+ dma.streams[9].func(dma.streams[9].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -301,8 +347,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) { flags = (DMA2->LISR >> 16U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 16U;
- if (dma_isr_redir[10].dma_func)
- dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+ if (dma.streams[10].func)
+ dma.streams[10].func(dma.streams[10].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -319,8 +365,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) { flags = (DMA2->LISR >> 22U) & STM32_DMA_ISR_MASK;
DMA2->LIFCR = flags << 22U;
- if (dma_isr_redir[11].dma_func)
- dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+ if (dma.streams[11].func)
+ dma.streams[11].func(dma.streams[11].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -337,8 +383,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) { flags = (DMA2->HISR >> 0U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 0U;
- if (dma_isr_redir[12].dma_func)
- dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
+ if (dma.streams[12].func)
+ dma.streams[12].func(dma.streams[12].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -355,8 +401,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) { flags = (DMA2->HISR >> 6U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 6U;
- if (dma_isr_redir[13].dma_func)
- dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
+ if (dma.streams[13].func)
+ dma.streams[13].func(dma.streams[13].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -373,8 +419,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) { flags = (DMA2->HISR >> 16U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 16U;
- if (dma_isr_redir[14].dma_func)
- dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
+ if (dma.streams[14].func)
+ dma.streams[14].func(dma.streams[14].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -391,8 +437,8 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) { flags = (DMA2->HISR >> 22U) & STM32_DMA_ISR_MASK;
DMA2->HIFCR = flags << 22U;
- if (dma_isr_redir[15].dma_func)
- dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
+ if (dma.streams[15].func)
+ dma.streams[15].func(dma.streams[15].param, flags);
OSAL_IRQ_EPILOGUE();
}
@@ -409,10 +455,10 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) { void dmaInit(void) {
unsigned i;
- dma_streams_mask = 0U;
+ dma.allocated_mask = 0U;
for (i = 0U; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].stream->CR = 0U;
- dma_isr_redir[i].dma_func = NULL;
+ _stm32_dma_streams[i].stream->CR = STM32_DMA_CR_RESET_VALUE;
+ dma.streams[i].func = NULL;
}
DMA1->LIFCR = 0xFFFFFFFFU;
DMA1->HIFCR = 0xFFFFFFFFU;
@@ -432,6 +478,105 @@ void dmaInit(void) { * @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
+ *
+ * @param[in] id numeric identifiers of a specific stream or:
+ * - @p STM32_DMA_STREAM_ID_ANY for any stream.
+ * - @p STM32_DMA_STREAM_ID_ANY_DMA1 for any stream
+ * on DMA1.
+ * - @p STM32_DMA_STREAM_ID_ANY_DMA2 for any stream
+ * on DMA2.
+ * .
+ * @param[in] priority IRQ priority for the DMA stream
+ * @param[in] func handling function pointer, can be @p NULL
+ * @param[in] param a parameter to be passed to the handling function
+ * @return Pointer to the allocated @p stm32_dma_stream_t
+ * structure.
+ * @retval NULL if a/the stream is not available.
+ *
+ * @iclass
+ */
+const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param) {
+ uint32_t i, startid, endid;
+
+ osalDbgCheckClassI();
+
+ if (id < STM32_DMA_STREAMS) {
+ startid = id;
+ endid = id;
+ }
+ else if (id == STM32_DMA_STREAM_ID_ANY) {
+ startid = 0U;
+ endid = STM32_DMA_STREAMS - 1U;
+ }
+ else if (id == STM32_DMA_STREAM_ID_ANY_DMA1) {
+ startid = 0U;
+ endid = (STM32_DMA_STREAMS / 2U) - 1U;
+ }
+ else if (id == STM32_DMA_STREAM_ID_ANY_DMA2) {
+ startid = (STM32_DMA_STREAMS / 2U) - 1U;
+ endid = STM32_DMA_STREAMS - 1U;
+ }
+ else {
+ osalDbgCheck(false);
+ }
+
+ for (i = startid; i <= endid; i++) {
+ uint32_t mask = (1U << i);
+ if ((dma.allocated_mask & mask) == 0U) {
+ const stm32_dma_stream_t *dmastp = STM32_DMA_STREAM(i);
+
+ /* Installs the DMA handler.*/
+ dma.streams[i].func = func;
+ dma.streams[i].param = param;
+ dma.allocated_mask |= mask;
+
+ /* Enabling DMA clocks required by the current streams set.*/
+ if ((STM32_DMA1_STREAMS_MASK & mask) != 0U) {
+ rccEnableDMA1(true);
+ }
+ if ((STM32_DMA2_STREAMS_MASK & mask) != 0U) {
+ rccEnableDMA2(true);
+ }
+
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(rccEnableDMAMUX)
+ /* Enabling DMAMUX if present.*/
+ if (dma.allocated_mask != 0U) {
+ rccEnableDMAMUX(true);
+ }
+#endif
+
+ /* Putting the stream in a safe state.*/
+ dmaStreamDisable(dmastp);
+ dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
+ dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
+
+ /* Enables the associated IRQ vector if a callback is defined.*/
+ if (func != NULL) {
+ nvicEnableVector(dmastp->vector, priority);
+ }
+
+ return dmastp;
+ }
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ * The function also enables the IRQ vector associated to the stream
+ * and initializes its priority.
+ * @pre The stream must not be already in use or an error is returned.
+ * @post The stream is allocated and the default ISR handler redirected
+ * to the specified function.
+ * @post The stream ISR vector is enabled and its priority configured.
+ * @post The stream must be freed using @p dmaStreamRelease() before it can
+ * be reused with another peripheral.
+ * @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
@@ -443,42 +588,14 @@ void dmaInit(void) { * @retval true error, stream already taken.
*
* @special
+ * @deprecated
*/
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
uint32_t priority,
stm32_dmaisr_t func,
void *param) {
- osalDbgCheck(dmastp != NULL);
-
- /* Checks if the stream is already taken.*/
- if ((dma_streams_mask & (1U << dmastp->selfindex)) != 0U)
- return true;
-
- /* Marks the stream as allocated.*/
- dma_isr_redir[dmastp->selfindex].dma_func = func;
- dma_isr_redir[dmastp->selfindex].dma_param = param;
- dma_streams_mask |= (1U << dmastp->selfindex);
-
- /* Enabling DMA clocks required by the current streams set.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {
- rccEnableDMA1(true);
- }
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) {
- rccEnableDMA2(true);
- }
-
- /* Putting the stream in a safe state.*/
- dmaStreamDisable(dmastp);
- dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
- dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
-
- /* Enables the associated IRQ vector if a callback is defined.*/
- if (func != NULL) {
- nvicEnableVector(dmastp->vector, priority);
- }
-
- return false;
+ return dmaStreamAllocI(dmastp->selfindex, priority, func, param) == NULL;
}
/**
@@ -499,23 +616,48 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { osalDbgCheck(dmastp != NULL);
/* Check if the streams is not taken.*/
- osalDbgAssert((dma_streams_mask & (1U << dmastp->selfindex)) != 0U,
+ osalDbgAssert((dma.allocated_mask & (1U << dmastp->selfindex)) != 0U,
"not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/
- dma_streams_mask &= ~(1U << dmastp->selfindex);
+ dma.allocated_mask &= ~(1U << dmastp->selfindex);
/* Shutting down clocks that are no more required, if any.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
+ if ((dma.allocated_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
rccDisableDMA1();
}
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
+ if ((dma.allocated_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
rccDisableDMA2();
}
+
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(rccDisableDMAMUX)
+ /* Shutting down DMAMUX if present.*/
+ if (dma.allocated_mask == 0U) {
+ rccDisableDMAMUX();
+ }
+#endif
+}
+
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief Associates a peripheral request to a DMA stream.
+ * @note This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp pointer to a @p stm32_dma_stream_t structure
+ * @param[in] per peripheral identifier
+ *
+ * @special
+ */
+void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) {
+
+ osalDbgCheck(per < 256U);
+
+ dmastp->mux->CCR = per;
}
+#endif
#endif /* STM32_DMA_REQUIRED */
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h index c4059a06c..d331709b6 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h @@ -68,6 +68,17 @@ #define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
/**
+ * @brief Checks if a DMA channel is within the valid range.
+ *
+ * @param[in] ch DMA channel
+ * @retval The check result.
+ * @retval FALSE invalid DMA channel.
+ * @retval TRUE correct DMA channel.
+ */
+#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && \
+ ((ch) <= STM32_DMA_STREAMS))
+
+/**
* @brief Returns an unique numeric identifier for a DMA stream.
*
* @param[in] dma the DMA unit number
@@ -99,6 +110,15 @@ #define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
/**
+ * @name Special stream identifiers
+ * @{
+ */
+#define STM32_DMA_STREAM_ID_ANY STM32_DMA_STREAMS
+#define STM32_DMA_STREAM_ID_ANY_DMA1 (STM32_DMA_STREAM_ID_ANY + 1)
+#define STM32_DMA_STREAM_ID_ANY_DMA2 (STM32_DMA_STREAM_ID_ANY_DMA1 + 1)
+/** @} */
+
+/**
* @name DMA streams identifiers
* @{
*/
@@ -161,7 +181,7 @@ /** @} */
/**
- * @name CR register constants only found in STM32F2xx/STM32F4xx
+ * @name CR register constants only found in DMAv2
* @{
*/
#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
@@ -170,21 +190,26 @@ #define STM32_DMA_CR_DBM DMA_SxCR_DBM
#define STM32_DMA_CR_CT DMA_SxCR_CT
#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST
-#define STM32_DMA_CR_PBURST_SINGLE 0
+#define STM32_DMA_CR_PBURST_SINGLE 0U
#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0
#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1
#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST
-#define STM32_DMA_CR_MBURST_SINGLE 0
+#define STM32_DMA_CR_MBURST_SINGLE 0U
#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0
#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
+#if (STM32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(__DOXYGEN__)
#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL
#define STM32_DMA_CR_CHSEL(n) ((n) << 25U)
+#else
+#define STM32_DMA_CR_CHSEL_MASK 0U
+#define STM32_DMA_CR_CHSEL(n) 0U
+#endif
/** @} */
/**
- * @name FCR register constants only found in STM32F2xx/STM32F4xx
+ * @name FCR register constants only found in DMAv2
* @{
*/
#define STM32_DMA_FCR_RESET_VALUE 0x00000021U
@@ -356,31 +381,40 @@ #error "STM32_DMA2_CH7_NUMBER missing in registry"
#endif
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
+#include "stm32_dmamux.h"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
+ * @brief STM32 DMA ISR function type.
+ *
+ * @param[in] p parameter for the registered function
+ * @param[in] flags pre-shifted content of the xISR register, the bits
+ * are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/**
* @brief STM32 DMA stream descriptor structure.
*/
typedef struct {
DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
- uint8_t ishift; /**< @brief Bits offset in xIFCR
+#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
+ DMAMUX_Channel_TypeDef *mux; /**< @brief Associated DMA mux. */
+#else
+ uint8_t dummy; /**< @brief Filler. */
+#endif
+ uint8_t shift; /**< @brief Bits offset in xIFCR
register. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_dma_stream_t;
-/**
- * @brief STM32 DMA ISR function type.
- *
- * @param[in] p parameter for the registered function
- * @param[in] flags pre-shifted content of the xISR register, the bits
- * are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
@@ -538,7 +572,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
- *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
+ *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->shift; \
}
/**
@@ -612,11 +646,18 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; extern "C" {
#endif
void dmaInit(void);
+ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
+ uint32_t priority,
+ stm32_dmaisr_t func,
+ void *param);
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
uint32_t priority,
stm32_dmaisr_t func,
void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
+ void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);
+#endif
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/STM32/LLD/DMAv3/driver.mk b/os/hal/ports/STM32/LLD/DMAv3/driver.mk deleted file mode 100644 index fc51a08e4..000000000 --- a/os/hal/ports/STM32/LLD/DMAv3/driver.mk +++ /dev/null @@ -1,2 +0,0 @@ -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c
-PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv3
diff --git a/os/hal/ports/STM32/LLD/DMAv3/notes.txt b/os/hal/ports/STM32/LLD/DMAv3/notes.txt deleted file mode 100644 index 9004cd3f1..000000000 --- a/os/hal/ports/STM32/LLD/DMAv3/notes.txt +++ /dev/null @@ -1,12 +0,0 @@ -STM32 DMAv3 driver.
-
-Driver capability:
-
-- The driver supports the STM32 enhanced DMA controller found on H7 sub-family.
-- Support for cache flushing and invalidation.
-
-The file registry must export:
-
-STM32_HAS_DMAx - Support for DMA unit "x" (1..2).
-STM32_DMAx_CHn_HANDLER - Vector name for channel "n" (0..7).
-STM32_DMAx_CHn_NUMBER - Vector number for channel "n" (0..7).
diff --git a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c deleted file mode 100644 index c3fc1401b..000000000 --- a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.c +++ /dev/null @@ -1,547 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DMAv3/stm32_dma.c
- * @brief Enhanced DMA helper driver code.
- *
- * @addtogroup STM32_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- * shared resource, this driver allows to allocate and free DMA
- * streams at runtime in order to allow all the other device
- * drivers to coordinate the access to the resource.
- * @note The DMA ISR handlers are all declared into this module because
- * sharing, the various device drivers can associate a callback to
- * ISRs when allocating streams.
- * @{
- */
-
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
- has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/**
- * @brief Mask of the DMA1 streams in @p dma.streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK 0x000000FFU
-
-/**
- * @brief Mask of the DMA2 streams in @p dma.streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK 0x0000FF00U
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- * identifier and the involved physical registers.
- * @note Don't use this array directly, use the appropriate wrapper macros
- * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1_Stream0, &DMA1->LIFCR, 0, DMAMUX1_Channel0, 0, STM32_DMA1_CH0_NUMBER},
- {DMA1_Stream1, &DMA1->LIFCR, 6, DMAMUX1_Channel1, 1, STM32_DMA1_CH1_NUMBER},
- {DMA1_Stream2, &DMA1->LIFCR, 16, DMAMUX1_Channel2, 2, STM32_DMA1_CH2_NUMBER},
- {DMA1_Stream3, &DMA1->LIFCR, 22, DMAMUX1_Channel3, 3, STM32_DMA1_CH3_NUMBER},
- {DMA1_Stream4, &DMA1->HIFCR, 0, DMAMUX1_Channel4, 4, STM32_DMA1_CH4_NUMBER},
- {DMA1_Stream5, &DMA1->HIFCR, 6, DMAMUX1_Channel5, 5, STM32_DMA1_CH5_NUMBER},
- {DMA1_Stream6, &DMA1->HIFCR, 16, DMAMUX1_Channel6, 6, STM32_DMA1_CH6_NUMBER},
- {DMA1_Stream7, &DMA1->HIFCR, 22, DMAMUX1_Channel7, 7, STM32_DMA1_CH7_NUMBER},
- {DMA2_Stream0, &DMA2->LIFCR, 0, DMAMUX1_Channel8, 8, STM32_DMA2_CH0_NUMBER},
- {DMA2_Stream1, &DMA2->LIFCR, 6, DMAMUX1_Channel9, 9, STM32_DMA2_CH1_NUMBER},
- {DMA2_Stream2, &DMA2->LIFCR, 16, DMAMUX1_Channel10, 10, STM32_DMA2_CH2_NUMBER},
- {DMA2_Stream3, &DMA2->LIFCR, 22, DMAMUX1_Channel11, 11, STM32_DMA2_CH3_NUMBER},
- {DMA2_Stream4, &DMA2->HIFCR, 0, DMAMUX1_Channel12, 12, STM32_DMA2_CH4_NUMBER},
- {DMA2_Stream5, &DMA2->HIFCR, 6, DMAMUX1_Channel13, 13, STM32_DMA2_CH5_NUMBER},
- {DMA2_Stream6, &DMA2->HIFCR, 16, DMAMUX1_Channel14, 14, STM32_DMA2_CH6_NUMBER},
- {DMA2_Stream7, &DMA2->HIFCR, 22, DMAMUX1_Channel15, 15, STM32_DMA2_CH7_NUMBER}
-};
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief DMA ISR redirector type.
- */
-typedef struct {
- stm32_dmaisr_t func; /**< @brief DMA callback function. */
- void *param; /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief DMA driver base structure.
- */
-static struct {
- /**
- * @brief Mask of the allocated streams.
- */
- uint32_t streams_mask;
- /**
- * @brief DMA IRQ redirectors.
- */
- dma_isr_redir_t isr_redir[STM32_DMA_STREAMS];
-} dma;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief DMA1 stream 0 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH0_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 0U) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 0U;
- if (dma.isr_redir[0].func)
- dma.isr_redir[0].func(dma.isr_redir[0].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 6U) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 6U;
- if (dma.isr_redir[1].func)
- dma.isr_redir[1].func(dma.isr_redir[1].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 16U) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 16U;
- if (dma.isr_redir[2].func)
- dma.isr_redir[2].func(dma.isr_redir[2].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 22U) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 22U;
- if (dma.isr_redir[3].func)
- dma.isr_redir[3].func(dma.isr_redir[3].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 0U) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 0U;
- if (dma.isr_redir[4].func)
- dma.isr_redir[4].func(dma.isr_redir[4].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 6U) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 6U;
- if (dma.isr_redir[5].func)
- dma.isr_redir[5].func(dma.isr_redir[5].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 16U) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 16U;
- if (dma.isr_redir[6].func)
- dma.isr_redir[6].func(dma.isr_redir[6].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 22U) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 22U;
- if (dma.isr_redir[7].func)
- dma.isr_redir[7].func(dma.isr_redir[7].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 0 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH0_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 0U) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 0U;
- if (dma.isr_redir[8].func)
- dma.isr_redir[8].func(dma.isr_redir[8].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 6U) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 6U;
- if (dma.isr_redir[9].func)
- dma.isr_redir[9].func(dma.isr_redir[9].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 16U) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 16U;
- if (dma.isr_redir[10].func)
- dma.isr_redir[10].func(dma.isr_redir[10].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 22U) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 22U;
- if (dma.isr_redir[11].func)
- dma.isr_redir[11].func(dma.isr_redir[11].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 0U) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 0U;
- if (dma.isr_redir[12].func)
- dma.isr_redir[12].func(dma.isr_redir[12].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 6U) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 6U;
- if (dma.isr_redir[13].func)
- dma.isr_redir[13].func(dma.isr_redir[13].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 6 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 16U) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 16U;
- if (dma.isr_redir[14].func)
- dma.isr_redir[14].func(dma.isr_redir[14].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 7 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 22U) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 22U;
- if (dma.isr_redir[15].func)
- dma.isr_redir[15].func(dma.isr_redir[15].param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
- unsigned i;
-
- dma.streams_mask = 0U;
- for (i = 0U; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].stream->CR = 0U;
- dma.isr_redir[i].func = NULL;
- dma.isr_redir[i].param = NULL;
- }
- DMA1->LIFCR = 0xFFFFFFFFU;
- DMA1->HIFCR = 0xFFFFFFFFU;
- DMA2->LIFCR = 0xFFFFFFFFU;
- DMA2->HIFCR = 0xFFFFFFFFU;
-}
-
-/**
- * @brief Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- * The function also enables the IRQ vector associated to the stream
- * and initializes its priority.
- * @pre The stream must not be already in use or an error is returned.
- * @post The stream is allocated and the default ISR handler redirected
- * to the specified function.
- * @post The stream ISR vector is enabled and its priority configured.
- * @post The stream must be freed using @p dmaStreamRelease() before it can
- * be reused with another peripheral.
- * @post The stream is in its post-reset state.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] priority IRQ priority for the DMA stream
- * @param[in] func handling function pointer, can be @p NULL
- * @param[in] param a parameter to be passed to the handling function
- * @return The operation status.
- * @retval false no error, stream taken.
- * @retval true error, stream already taken.
- *
- * @special
- */
-bool dmaStreamAllocate(const stm32_dma_stream_t *stp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param) {
-
- osalDbgCheck(stp != NULL);
-
- /* Checks if the stream is already taken.*/
- if ((dma.streams_mask & (1U << stp->selfindex)) != 0U)
- return true;
-
- /* Marks the stream as allocated.*/
- dma.isr_redir[stp->selfindex].func = func;
- dma.isr_redir[stp->selfindex].param = param;
- dma.streams_mask |= (1U << stp->selfindex);
-
- /* Enabling DMA clocks required by the current streams set.*/
- if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {
- rccEnableDMA1(true);
- }
- if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) != 0U) {
- rccEnableDMA2(true);
- }
-
- /* Putting the stream in a safe state.*/
- dmaStreamDisable(stp);
- stp->stream->CR = STM32_DMA_CR_RESET_VALUE;
- stp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
-
- /* Enables the associated IRQ vector if a callback is defined.*/
- if (func != NULL) {
- nvicEnableVector(stp->vector, priority);
- }
-
- return false;
-}
-
-/**
- * @brief Associates a peripheral request to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] per peripheral identifier
- *
- * @special
- */
-void dmaSetRequestSource(const stm32_dma_stream_t *stp, uint32_t per) {
-
- osalDbgCheck(per < 256U);
-
- stp->mux->CCR = per;
-}
-
-/**
- * @brief Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- * Trying to release a unallocated stream is an illegal operation
- * and is trapped if assertions are enabled.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post The stream is again available.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *stp) {
-
- osalDbgCheck(stp != NULL);
-
- /* Check if the streams is not taken.*/
- osalDbgAssert((dma.streams_mask & (1U << stp->selfindex)) != 0U,
- "not allocated");
-
- /* Disables the associated IRQ vector.*/
- nvicDisableVector(stp->vector);
-
- /* Marks the stream as not allocated.*/
- dma.streams_mask &= ~(1U << stp->selfindex);
-
- /* Clearing associated handler and parameter.*/
- dma.isr_redir->func = NULL;
- dma.isr_redir->param = NULL;
-
- /* Shutting down clocks that are no more required, if any.*/
- if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
- rccDisableDMA1();
- }
- if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
- rccDisableDMA2();
- }
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h deleted file mode 100644 index 1d4106b17..000000000 --- a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h +++ /dev/null @@ -1,590 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DMAv3/stm32_dma.h
- * @brief Enhanced-DMA helper driver header.
- *
- * @addtogroup STM32_DMA
- * @{
- */
-
-#ifndef STM32_DMA_H
-#define STM32_DMA_H
-
-#include "stm32_dmamux.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief DMA capability.
- * @details if @p TRUE then the DMA is able of burst transfers, FIFOs,
- * scatter gather and other advanced features.
- */
-#define STM32_DMA_ADVANCED TRUE
-
-/**
- * @brief Total number of DMA streams.
- * @details This is the total number of streams among all the DMA units.
- */
-#define STM32_DMA_STREAMS 16U
-
-/**
- * @brief Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK 0x3DU
-
-/**
- * @brief Checks if a DMA priority is within the valid range.
- *
- * @param[in] prio DMA priority
- * @retval The check result.
- * @retval FALSE invalid DMA priority.
- * @retval TRUE correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
-
-/**
- * @brief Checks if a DMA channel is within the valid range.
- *
- * @param[in] ch DMA channel
- * @retval The check result.
- * @retval FALSE invalid DMA channel.
- * @retval TRUE correct DMA channel.
- */
-#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && ((ch) <= 15U))
-
-/**
- * @name DMA streams identifiers
- * @{
- */
-/**
- * @brief Returns a pointer to a @p stm32_dma_stream_t structure.
- *
- * @param[in] id the stream numeric identifier
- * @return A pointer to the stm32_dma_stream_t constant structure
- * associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6)
-#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11)
-#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12)
-#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13)
-#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14)
-#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15)
-/** @} */
-
-/**
- * @name CR register constants
- * @{
- */
-#define STM32_DMA_CR_RESET_VALUE 0x00000000U
-#define STM32_DMA_CR_EN DMA_SxCR_EN
-#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
-#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
-#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE
-#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE
-#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL
-#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR_Msk
-#define STM32_DMA_CR_DIR_P2M 0
-#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0
-#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1
-#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC
-#define STM32_DMA_CR_PINC DMA_SxCR_PINC
-#define STM32_DMA_CR_MINC DMA_SxCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE_Msk
-#define STM32_DMA_CR_PSIZE_BYTE 0
-#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE_Msk
-#define STM32_DMA_CR_MSIZE_BYTE 0
-#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
- STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS
-#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL_Msk
-#define STM32_DMA_CR_PL(n) ((n) << 16U)
-#define STM32_DMA_CR_DBM DMA_SxCR_DBM
-#define STM32_DMA_CR_CT DMA_SxCR_CT
-#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST_Msk
-#define STM32_DMA_CR_PBURST_SINGLE 0
-#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0
-#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1
-#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
-#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST_Msk
-#define STM32_DMA_CR_MBURST_SINGLE 0
-#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0
-#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
-#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
-/** @} */
-
-/**
- * @name FCR register constants
- * @{
- */
-#define STM32_DMA_FCR_RESET_VALUE 0x00000021U
-#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH_Msk
-#define STM32_DMA_FCR_FTH_1Q 0
-#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0
-#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1
-#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
-#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS
-#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
-#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS_Msk
-/** @} */
-
-/**
- * @name Status flags passed to the ISR callbacks
- */
-#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0
-#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0
-#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0
-#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0
-#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !defined(STM32_DMA_SUPPORTS_DMAMUX)
-#error "STM32_DMA_SUPPORTS_DMAMUX not defined in registry"
-#endif
-
-#if !defined(STM32_HAS_DMA1)
-#error "STM32_HAS_DMA1 missing in registry"
-#endif
-
-#if !defined(STM32_HAS_DMA2)
-#error "STM32_HAS_DMA2 missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH0_HANDLER)
-#error "STM32_DMA1_CH0_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH1_HANDLER)
-#error "STM32_DMA1_CH1_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH2_HANDLER)
-#error "STM32_DMA1_CH2_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH3_HANDLER)
-#error "STM32_DMA1_CH3_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH4_HANDLER)
-#error "STM32_DMA1_CH4_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH5_HANDLER)
-#error "STM32_DMA1_CH5_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH6_HANDLER)
-#error "STM32_DMA1_CH6_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH7_HANDLER)
-#error "STM32_DMA1_CH7_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH0_HANDLER)
-#error "STM32_DMA2_CH0_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH1_HANDLER)
-#error "STM32_DMA2_CH1_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH2_HANDLER)
-#error "STM32_DMA2_CH2_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH3_HANDLER)
-#error "STM32_DMA2_CH3_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH4_HANDLER)
-#error "STM32_DMA2_CH4_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH5_HANDLER)
-#error "STM32_DMA2_CH5_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH6_HANDLER)
-#error "STM32_DMA2_CH6_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH7_HANDLER)
-#error "STM32_DMA2_CH7_HANDLER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH0_NUMBER)
-#error "STM32_DMA1_CH0_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH1_NUMBER)
-#error "STM32_DMA1_CH1_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH2_NUMBER)
-#error "STM32_DMA1_CH2_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH3_NUMBER)
-#error "STM32_DMA1_CH3_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH4_NUMBER)
-#error "STM32_DMA1_CH4_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH5_NUMBER)
-#error "STM32_DMA1_CH5_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH6_NUMBER)
-#error "STM32_DMA1_CH6_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA1_CH7_NUMBER)
-#error "STM32_DMA1_CH7_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH0_NUMBER)
-#error "STM32_DMA2_CH0_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH1_NUMBER)
-#error "STM32_DMA2_CH1_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH2_NUMBER)
-#error "STM32_DMA2_CH2_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH3_NUMBER)
-#error "STM32_DMA2_CH3_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH4_NUMBER)
-#error "STM32_DMA2_CH4_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH5_NUMBER)
-#error "STM32_DMA2_CH5_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH6_NUMBER)
-#error "STM32_DMA2_CH6_NUMBER missing in registry"
-#endif
-
-#if !defined(STM32_DMA2_CH7_NUMBER)
-#error "STM32_DMA2_CH7_NUMBER missing in registry"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA stream descriptor structure.
- */
-typedef struct {
- DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
- volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
- uint8_t ishift; /**< @brief Bits offset in xIFCR
- register. */
- DMAMUX_Channel_TypeDef *mux; /**< @brief Associated DMA mux. */
- uint8_t selfindex; /**< @brief Index to self in array. */
- uint8_t vector; /**< @brief Associated IRQ vector. */
-} stm32_dma_stream_t;
-
-/**
- * @brief STM32 DMA ISR function type.
- *
- * @param[in] p parameter for the registered function
- * @param[in] flags pre-shifted content of the xISR register, the bits
- * are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Associates a peripheral data register to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] addr value to be written in the PAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(stp, addr) { \
- (stp)->stream->PAR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Associates a memory destination to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] addr value to be written in the M0AR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(stp, addr) { \
- (stp)->stream->M0AR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Associates an alternate memory destination to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] addr value to be written in the M1AR register
- *
- * @special
- */
-#define dmaStreamSetMemory1(stp, addr) { \
- (stp)->stream->M1AR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Sets the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] size value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(stp, size) { \
- (stp)->stream->NDTR = (uint32_t)(size); \
-}
-
-/**
- * @brief Returns the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @return The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(stp) ((size_t)((stp)->stream->NDTR))
-
-/**
- * @brief Programs the stream mode settings.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CR register
- *
- * @special
- */
-#define dmaStreamSetMode(stp, mode) { \
- (stp)->stream->CR = (uint32_t)(mode); \
-}
-
-/**
- * @brief Programs the stream FIFO settings.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] mode value to be written in the FCR register
- *
- * @special
- */
-#define dmaStreamSetFIFO(stp, mode) { \
- (stp)->stream->FCR = (uint32_t)(mode); \
-}
-
-/**
- * @brief DMA stream enable.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(stp) { \
- (stp)->stream->CR |= STM32_DMA_CR_EN; \
-}
-
-/**
- * @brief DMA stream disable.
- * @details The function disables the specified stream, waits for the disable
- * operation to complete and then clears any pending interrupt.
- * @note This function can be invoked in both ISR or thread context.
- * @note Interrupts enabling flags are set to zero after this call, see
- * bug 3607518.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(stp) { \
- (stp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
- STM32_DMA_CR_EN); \
- while (((stp)->stream->CR & STM32_DMA_CR_EN) != 0) \
- ; \
- dmaStreamClearInterrupt(stp); \
-}
-
-/**
- * @brief DMA stream interrupt sources clear.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(stp) { \
- *(stp)->ifcr = STM32_DMA_ISR_MASK << (stp)->ishift; \
-}
-
-/**
- * @brief Starts a memory to memory operation using the specified stream.
- * @note The default transfer data mode is "byte to byte" but it can be
- * changed by specifying extra options in the @p mode parameter.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CCR register, this value
- * is implicitly ORed with:
- * - @p STM32_DMA_CR_MINC
- * - @p STM32_DMA_CR_PINC
- * - @p STM32_DMA_CR_DIR_M2M
- * - @p STM32_DMA_CR_EN
- * .
- * @param[in] src source address
- * @param[in] dst destination address
- * @param[in] n number of data units to copy
- */
-#define dmaStartMemCopy(stp, mode, src, dst, n) { \
- dmaStreamSetPeripheral(stp, src); \
- dmaStreamSetMemory0(stp, dst); \
- dmaStreamSetTransactionSize(stp, n); \
- dmaStreamSetMode(stp, (mode) | \
- STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
- STM32_DMA_CR_DIR_M2M); \
- dmaStreamEnable(stp); \
-}
-
-/**
- * @brief Polled wait for DMA transfer end.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(stp) { \
- (stp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE); \
- while ((stp)->stream->CR & STM32_DMA_CR_EN) \
- ; \
- dmaStreamClearInterrupt(stp); \
-}
-
-/**
- * @brief DMA stream current target.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] stp pointer to a @p stm32_dma_stream_t structure
- * @return Current memory target index.
- *
- * @special
- */
-#define dmaStreamGetCurrentTarget(stp) \
- (((stp)->stream->CR >> DMA_SxCR_CT_Pos) & 1U)
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void dmaInit(void);
- bool dmaStreamAllocate(const stm32_dma_stream_t *stp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param);
- void dmaSetRequestSource(const stm32_dma_stream_t *stp, uint32_t per);
- void dmaStreamRelease(const stm32_dma_stream_t *stp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_DMA_H */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32H7xx/platform.mk b/os/hal/ports/STM32/STM32H7xx/platform.mk index e7595a12b..890b8999a 100644 --- a/os/hal/ports/STM32/STM32H7xx/platform.mk +++ b/os/hal/ports/STM32/STM32H7xx/platform.mk @@ -24,7 +24,7 @@ endif include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv4/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/BDMAv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CRYPv1/driver.mk
-include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv3/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
diff --git a/readme.txt b/readme.txt index a6bc2486b..bf13b4221 100644 --- a/readme.txt +++ b/readme.txt @@ -75,6 +75,9 @@ *****************************************************************************
*** Next ***
+- NEW: Both DMAv1 and DMAv2 have been reworked to support DMAMUX, DMAv3 has
+ been removed. In addition, both drivers are now able to support dynamic
+ channel allocation.
- NEW: The callback of drivers with circular buffers (ADC, DAC, I2S, SPI) has
been simplified, no parameters. A driver function xxxIsBufferComplete()
has been added to determine if it is the half buffer callback or the
diff --git a/testhal/STM32/multi/SPI/debug/STM32-SPI (Select ELF file)(OpenOCD, Flash and Run).launch b/testhal/STM32/multi/SPI/debug/STM32-SPI (Select ELF file)(OpenOCD, Flash and Run).launch index 5aea45b0e..ceedfb2a7 100644 --- a/testhal/STM32/multi/SPI/debug/STM32-SPI (Select ELF file)(OpenOCD, Flash and Run).launch +++ b/testhal/STM32/multi/SPI/debug/STM32-SPI (Select ELF file)(OpenOCD, Flash and Run).launch @@ -1,52 +1,52 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
-<stringAttribute key="bad_container_name" value="\STM32-SPI\debug"/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
-<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
-<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
-<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="xPSR-(format)" val="4"/></contentList>"/>
-<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
-<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList> <memoryBlockExpressionItem> <expression text="0x40021004"/> </memoryBlockExpressionItem> </memoryBlockExpressionList> "/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${selected_resource_loc}"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32-SPI"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/STM32-SPI"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
-<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
-</listAttribute>
-</launchConfiguration>
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType"> +<stringAttribute key="bad_container_name" value="\STM32-SPI\debug"/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/> +<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/> +<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> +<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="xPSR-(format)" val="4"/></contentList>"/> +<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList> <memoryBlockExpressionItem> <expression text="0x40021004"/> </memoryBlockExpressionItem> </memoryBlockExpressionList> "/> +<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${selected_resource_loc}"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32-SPI"/> +<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> +<listEntry value="/STM32-SPI"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> +<listEntry value="4"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.ui.favoriteGroups"> +<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/> +</listAttribute> +</launchConfiguration> |