diff options
| -rw-r--r-- | os/hal/platforms/SAM4L/hal_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/platforms/SAM4L/hal_lld.h | 102 |
2 files changed, 104 insertions, 0 deletions
diff --git a/os/hal/platforms/SAM4L/hal_lld.c b/os/hal/platforms/SAM4L/hal_lld.c index fbbaebcf8..745da4686 100644 --- a/os/hal/platforms/SAM4L/hal_lld.c +++ b/os/hal/platforms/SAM4L/hal_lld.c @@ -55,6 +55,7 @@ void sam4l_clock_init(void) {
+#if SAM_NO_INIT
#if SAM_USE_PICOCACHE
/* Enable the PicoCache.*/
sysclk_enable_peripheral_clock(HCACHE);
@@ -63,6 +64,7 @@ void sam4l_clock_init(void) { ;
#endif
+#endif /* SAM_NO_INIT */
}
/**
diff --git a/os/hal/platforms/SAM4L/hal_lld.h b/os/hal/platforms/SAM4L/hal_lld.h index fb78792b9..52e1fd2ec 100644 --- a/os/hal/platforms/SAM4L/hal_lld.h +++ b/os/hal/platforms/SAM4L/hal_lld.h @@ -45,10 +45,112 @@ */
#define PLATFORM_NAME "SAM4L Series"
+/**
+ * @name MCCTRL register bits definitions
+ * @{
+ */
+#define SAM_MCSEL_MASK (7 << 0) /**< MCSEL bits mask. */
+#define SAM_MCSEL_RCSYS (0 << 0) /**< System RC oscillator. */
+#define SAM_MCSEL_OSC0 (1 << 0) /**< Oscillator 0. */
+#define SAM_MCSEL_PLL (2 << 0) /**< PLL. */
+#define SAM_MCSEL_DFLL (3 << 0) /**< DFLL. */
+#define SAM_MCSEL_RC80M (4 << 0) /**< 80 MHz RC oscillator. */
+#define SAM_MCSEL_RCFAST (5 << 0) /**< 4/8/12 MHz RC oscillator. */
+#define SAM_MCSEL_RC1M (6 << 0) /**< 1 MHz RC oscillator. */
+/** @} */
+
+/**
+ * @name CPUSEL register bits definitions
+ * @{
+ */
+#define SAM_CPUSEL_MASK (7 << 0) /**< CPUSEL bits mask. */
+#define SAM_CPUSEL_DIV1 0
+#define SAM_CPUSEL_DIV2 (SAM_CPUDIV | 0)
+#define SAM_CPUSEL_DIV4 (SAM_CPUDIV | 1)
+#define SAM_CPUSEL_DIV8 (SAM_CPUDIV | 2)
+#define SAM_CPUSEL_DIV16 (SAM_CPUDIV | 3)
+#define SAM_CPUSEL_DIV32 (SAM_CPUDIV | 4)
+#define SAM_CPUSEL_DIV64 (SAM_CPUDIV | 5)
+#define SAM_CPUSEL_DIV128 (SAM_CPUDIV | 6)
+#define SAM_CPUSEL_DIV256 (SAM_CPUDIV | 7)
+#define SAM_CPUDIV (1 << 7) /**< CPUDIV bit. */
+
+/**
+ * @name PBx registers bits definitions
+ * @{
+ */
+#define SAM_PBSEL_MASK (7 << 0) /**< PBSEL bits mask. */
+#define SAM_PBSEL_DIV1 0
+#define SAM_PBSEL_DIV2 (SAM_CPUDIV | 0)
+#define SAM_PBSEL_DIV4 (SAM_CPUDIV | 1)
+#define SAM_PBSEL_DIV8 (SAM_CPUDIV | 2)
+#define SAM_PBSEL_DIV16 (SAM_CPUDIV | 3)
+#define SAM_PBSEL_DIV32 (SAM_CPUDIV | 4)
+#define SAM_PBSEL_DIV64 (SAM_CPUDIV | 5)
+#define SAM_PBSEL_DIV128 (SAM_CPUDIV | 6)
+#define SAM_PBSEL_DIV256 (SAM_CPUDIV | 7)
+#define SAM_PBDIV (1 << 7) /**< PBDIV bit. */
+/** @} */
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the clock initialization in the HAL.
+ */
+#if !defined(SAM_NO_INIT) || defined(__DOXYGEN__)
+#define SAM_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCCTRL register settings.
+ */
+#if !defined(SAM_MCCTRL_MCSEL) || defined(__DOXYGEN__)
+#define SAM_MCCTRL_MCSEL SAM_MCSEL_PLL
+#endif
+
+/**
+ * @brief CPUSEL register settings.
+ */
+#if !defined(SAM_CPUSEL) || defined(__DOXYGEN__)
+#define SAM_CPUSEL SAM_CPUSEL_DIV1
+#endif
+
+/**
+ * @brief PBASEL register settings.
+ */
+#if !defined(SAM_PBASEL) || defined(__DOXYGEN__)
+#define SAM_PBASEL SAM_PBSEL_DIV1
+#endif
+
+/**
+ * @brief PBBSEL register settings.
+ */
+#if !defined(SAM_PBBSEL) || defined(__DOXYGEN__)
+#define SAM_PBBSEL SAM_PBSEL_DIV1
+#endif
+
+/**
+ * @brief PBCSEL register settings.
+ */
+#if !defined(SAM_PBCSEL) || defined(__DOXYGEN__)
+#define SAM_PBCSEL SAM_PBSEL_DIV1
+#endif
+
+/**
+ * @brief PBDSEL register settings.
+ */
+#if !defined(SAM_PBDSEL) || defined(__DOXYGEN__)
+#define SAM_PBDSEL SAM_PBSEL_DIV1
+#endif
+
+/** @} */
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
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