diff options
| -rw-r--r-- | demos/PPC-SPC560P-GCC/mcuconf.h | 9 | ||||
| -rw-r--r-- | docs/reports/SPC560P50-64.txt | 22 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/hal_lld.c | 10 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/hal_lld.h | 219 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/spc560p_registry.h | 2 |
5 files changed, 243 insertions, 19 deletions
diff --git a/demos/PPC-SPC560P-GCC/mcuconf.h b/demos/PPC-SPC560P-GCC/mcuconf.h index 4fc37eff4..a36f0461f 100644 --- a/demos/PPC-SPC560P-GCC/mcuconf.h +++ b/demos/PPC-SPC560P-GCC/mcuconf.h @@ -30,6 +30,14 @@ */
#define SPC5_NO_INIT FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
+#define SPC5_DISABLE_WATCHDOG TRUE
+#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
+#define SPC5_MCONTROL_DIVIDER_VALUE 2
+#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2
+#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
+#define SPC5_SP_CLK_DIVIDER_VALUE 2
+#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1
+#define SPC5_FR_CLK_DIVIDER_VALUE 2
#define SPC5_FMPLL0_IDF_VALUE 5
#define SPC5_FMPLL0_NDIV_VALUE 32
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
@@ -135,6 +143,7 @@ #define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#define SPC5_PIT0_IRQ_PRIORITY 4
+#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
/*
* SERIAL driver system settings.
diff --git a/docs/reports/SPC560P50-64.txt b/docs/reports/SPC560P50-64.txt index e78b803a2..67aad3cd3 100644 --- a/docs/reports/SPC560P50-64.txt +++ b/docs/reports/SPC560P50-64.txt @@ -6,7 +6,7 @@ Settings: SYSCLK=64 *** ChibiOS/RT test suite
***
*** Kernel: 2.5.2unstable
-*** Compiled: Feb 15 2013 - 16:26:30
+*** Compiled: Feb 19 2013 - 15:18:24
*** Compiler: GCC 4.6.3 build on 2013-01-07
*** Architecture: Power Architecture
*** Core Variant: e200z0
@@ -100,15 +100,15 @@ Settings: SYSCLK=64 --- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 200705 msgs/S, 401410 ctxswc/S
+--- Score : 200701 msgs/S, 401402 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
---- Score : 167518 msgs/S, 335036 ctxswc/S
+--- Score : 167517 msgs/S, 335034 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 167518 msgs/S, 335036 ctxswc/S
+--- Score : 167519 msgs/S, 335038 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
@@ -116,15 +116,15 @@ Settings: SYSCLK=64 --- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 132967 threads/S
+--- Score : 132691 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 189949 threads/S
+--- Score : 189383 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 51971 reschedules/S, 311826 ctxswc/S
+--- Score : 52143 reschedules/S, 312858 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
@@ -132,19 +132,19 @@ Settings: SYSCLK=64 --- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 619256 bytes/S
+--- Score : 619280 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 802792 timers/S
+--- Score : 792852 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 818244 wait+signal/S
+--- Score : 850984 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 643052 lock+unlock/S
+--- Score : 649592 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c index ef7c4806a..505b777de 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.c +++ b/os/hal/platforms/SPC560Pxx/hal_lld.c @@ -140,6 +140,16 @@ void spc_clock_init(void) { CGM.OSC_CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
+ /* Setting the various dividers and source selectors.*/
+ CGM.AC0DC.R = SPC5_CGM_AC0_DC0;
+ CGM.AC0SC.R = SPC5_AUX0CLK_SRC;
+ CGM.AC1DC.R = SPC5_CGM_AC1_DC0;
+ CGM.AC1SC.R = SPC5_AUX1CLK_SRC;
+ CGM.AC2DC.R = SPC5_CGM_AC2_DC0;
+ CGM.AC2SC.R = SPC5_AUX2CLK_SRC;
+ CGM.AC3DC.R = SPC5_CGM_AC3_DC0;
+ CGM.AC3SC.R = SPC5_AUX3CLK_SRC;
+
/* Enables the XOSC in order to check its functionality before proceeding
with the initialization.*/
/* ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON | \
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h index 2d652b90a..4dd5c5f98 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.h +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -115,6 +115,18 @@ /** @} */
/**
+ * @name Clock selectors used in the various GCM SC registers
+ * @{
+ */
+#define SPC5_CGM_SS_MASK (15U << 24)
+#define SPC5_CGM_SS_IRC (0U << 24)
+#define SPC5_CGM_SS_XOSC (2U << 24)
+#define SPC5_CGM_SS_FMPLL0 (4U << 24)
+#define SPC5_CGM_SS_FMPLL1 (5U << 24)
+#define SPC5_CGM_SS_FMPLL1_1D1 (8U << 24)
+/** @} */
+
+/**
* @name ME_GS register bits definitions
* @{
*/
@@ -220,14 +232,14 @@ * @brief Disables the clocks initialization in the HAL.
*/
#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
-#define SPC5_NO_INIT FALSE
+#define SPC5_NO_INIT FALSE
#endif
/**
* @brief Disables the overclock checks.
*/
#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
-#define SPC5_ALLOW_OVERCLOCK FALSE
+#define SPC5_ALLOW_OVERCLOCK FALSE
#endif
/**
@@ -242,7 +254,7 @@ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_IDF_VALUE 5
+#define SPC5_FMPLL0_IDF_VALUE 5
#endif
/**
@@ -250,7 +262,7 @@ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_NDIV_VALUE 32
+#define SPC5_FMPLL0_NDIV_VALUE 32
#endif
/**
@@ -258,7 +270,7 @@ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
#endif
/**
@@ -266,7 +278,7 @@ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/
#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_IDF_VALUE 5
+#define SPC5_FMPLL1_IDF_VALUE 5
#endif
/**
@@ -274,7 +286,7 @@ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/
#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_NDIV_VALUE 60
+#define SPC5_FMPLL1_NDIV_VALUE 60
#endif
/**
@@ -282,7 +294,68 @@ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
*/
#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
-#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief AUX0 clock source.
+ */
+#if !defined(SPC5_AUX0CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief Motor Control clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_MCONTROL_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_MCONTROL_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX1 clock source.
+ * @note Not configurable, always selects FMPLL1.
+ */
+#if !defined(SPC5_AUX1CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX1CLK_SRC 0
+#endif
+
+/**
+ * @brief FMPLL1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_FMPLL1_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX2 clock source.
+ */
+#if !defined(SPC5_AUX2CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief SP clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_SP_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_SP_CLK_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX3 clock source.
+ */
+#if !defined(SPC5_AUX3CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief FR clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_FR_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FR_CLK_DIVIDER_VALUE 2
#endif
/**
@@ -709,6 +782,136 @@ #error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
#endif
+/**
+ * @brief AUX0 clock point.
+ */
+#if (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
+#define SPC5_AUX0_CLK SPC5_FMPLL_SRC_IRC
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_XOSC
+#define SPC5_AUX0_CLK SPC5_FMPLL_SRC_XOSC
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL0
+#define SPC5_AUX0_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX0_CLK SPC5_FMPLL1_CLK
+#else
+#error "invalid SPC5_AUX0CLK_SRC value specified"
+#endif
+
+/* Check on the AUX0 divider 0 settings.*/
+#if SPC5_MCONTROL_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC0_DC0 0
+#elif (SPC5_MCONTROL_DIVIDER_VALUE >= 1) && (SPC5_MCONTROL_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC0_DC0 ((0x80U | (SPC5_MCONTROL_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_MCONTROL_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief Motor Control clock point.
+ */
+#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_MCONTROL_CLK (SPC5_AUX0_CLK / SPC5_MCONTROL_DIVIDER_VALUE)
+#else
+#define SPC5_MCONTROL_CLK 0
+#endif
+
+/**
+ * @brief AUX1 clock point.
+ */
+#if (SPC5_AUX1CLK_SRC == 0) || defined(__DOXYGEN__)
+#define SPC5_AUX1_CLK SPC5_FMPLL1_CLK
+#else
+#error "invalid SPC5_AUX1CLK_SRC value specified"
+#endif
+
+/* Check on the AUX1 divider 0 settings.*/
+#if SPC5_FMPLL1_CLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC1_DC0 0
+#elif (SPC5_FMPLL1_CLK_DIVIDER_VALUE >= 1) && (SPC5_FMPLL1_CLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC1_DC0 ((0x80U | (SPC5_FMPLL1_CLK_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_FMPLL1_CLK_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief FMPLL1 clock point.
+ */
+#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_FMPLL1_DIV_CLK (SPC5_AUX1_CLK / SPC5_FMPLL1_CLK_DIVIDER_VALUE)
+#else
+#define SPC5_FMPLL1_DIV_CLK 0
+#endif
+
+/**
+ * @brief AUX2 clock point.
+ */
+#if (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
+#define SPC5_AUX2_CLK SPC5_FMPLL_SRC_IRC
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_XOSC
+#define SPC5_AUX2_CLK SPC5_FMPLL_SRC_XOSC
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL0
+#define SPC5_AUX2_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX2_CLK SPC5_FMPLL1_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
+#define SPC5_AUX2_CLK SPC5_FMPLL1_1D1_CLK
+#else
+#error "invalid SPC5_AUX2CLK_SRC value specified"
+#endif
+
+/* Check on the AUX2 divider 0 settings.*/
+#if SPC5_SP_CLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC2_DC0 0
+#elif (SPC5_SP_CLK_DIVIDER_VALUE >= 1) && (SPC5_SP_CLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC2_DC0 ((0x80U | (SPC5_SP_CLK_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_SP_CLK_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief SP clock point.
+ */
+#if (SPC5_SP_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_SP_CLK (SPC5_AUX2_CLK / SPC5_SP_CLK_DIVIDER_VALUE)
+#else
+#define SPC5_SP_CLK 0
+#endif
+
+/**
+ * @brief AUX3 clock point.
+ */
+#if (SPC5_AUX3CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
+#define SPC5_AUX3_CLK SPC5_FMPLL_SRC_IRC
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_XOSC
+#define SPC5_AUX3_CLK SPC5_FMPLL_SRC_XOSC
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL0
+#define SPC5_AUX3_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX3_CLK SPC5_FMPLL1_CLK
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
+#define SPC5_AUX3_CLK SPC5_FMPLL1_1D1_CLK
+#else
+#error "invalid SPC5_AUX3CLK_SRC value specified"
+#endif
+
+/* Check on the AUX3 divider 0 settings.*/
+#if SPC5_FR_CLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC3_DC0 0
+#elif (SPC5_FR_CLK_DIVIDER_VALUE >= 1) && (SPC5_FR_CLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC3_DC0 ((0x80U | (SPC5_FR_CLK_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_FR_CLK_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief FR clock point.
+ */
+#if (SPC5_FR_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_FR_CLK (SPC5_AUX3_CLK / SPC5_FR_CLK_DIVIDER_VALUE)
+#else
+#define SPC5_FR_CLK 0
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index a4c962879..576db76f5 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -40,6 +40,7 @@ #define SPC5_LINFLEX0_RXI_NUMBER 79
#define SPC5_LINFLEX0_TXI_NUMBER 80
#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / 1)
#define SPC5_HAS_LINFLEX1 TRUE
#define SPC5_LINFLEX1_PCTL 49
@@ -49,6 +50,7 @@ #define SPC5_LINFLEX1_RXI_NUMBER 99
#define SPC5_LINFLEX1_TXI_NUMBER 100
#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / 1)
#define SPC5_HAS_LINFLEX2 FALSE
|