aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch2
-rw-r--r--os/hal/ports/STM32/STM32H7xx/platform.mk2
-rw-r--r--os/hal/ports/STM32/STM32H7xx/stm32_isr.c46
3 files changed, 25 insertions, 25 deletions
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
index fa9261ad2..c69b25933 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
@@ -33,7 +33,7 @@
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;r3-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r2-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ICSCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRRCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCKSELR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED3-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP1R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP2R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED4-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIER-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIFR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CICR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED5-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BDCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED6-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;GCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED7-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3AMR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED8-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED9-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED10-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR3-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;RESERVED10-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED9-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED8-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3AMR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED7-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;GCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED6-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BDCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED5-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CICR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIFR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIER-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED4-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP2R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP1R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED3-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCKSELR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRRCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ICSCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r3-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r2-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR3-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x0&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x11087000&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
diff --git a/os/hal/ports/STM32/STM32H7xx/platform.mk b/os/hal/ports/STM32/STM32H7xx/platform.mk
index 6f8969233..fbe8dfe69 100644
--- a/os/hal/ports/STM32/STM32H7xx/platform.mk
+++ b/os/hal/ports/STM32/STM32H7xx/platform.mk
@@ -1,7 +1,7 @@
# Required platform files.
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/stm32_isr.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/hal_lld.c
-# $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/stm32_isr.c \
# Required include directories.
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_isr.c b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c
index 005466142..95ae09e2e 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_isr.c
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c
@@ -63,9 +63,9 @@ OSAL_IRQ_HANDLER(Vector58) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (1U << 0);
- EXTI->PR = pr;
+ pr = EXTI_D1->PR1;
+ pr &= EXTI_D1->IMR1 & (1U << 0);
+ EXTI_D1->PR1 = pr;
exti_serve_irq(pr, 0);
@@ -84,9 +84,9 @@ OSAL_IRQ_HANDLER(Vector5C) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (1U << 1);
- EXTI->PR = pr;
+ pr = EXTI_D1->PR1;
+ pr &= EXTI_D1->IMR1 & (1U << 1);
+ EXTI_D1->PR1 = pr;
exti_serve_irq(pr, 1);
@@ -105,9 +105,9 @@ OSAL_IRQ_HANDLER(Vector60) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (1U << 2);
- EXTI->PR = pr;
+ pr = EXTI_D1->PR1;
+ pr &= EXTI_D1->IMR1 & (1U << 2);
+ EXTI_D1->PR1 = pr;
exti_serve_irq(pr, 2);
@@ -126,9 +126,9 @@ OSAL_IRQ_HANDLER(Vector64) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (1U << 3);
- EXTI->PR = pr;
+ pr = EXTI_D1->PR1;
+ pr &= EXTI_D1->IMR1 & (1U << 3);
+ EXTI_D1->PR1 = pr;
exti_serve_irq(pr, 3);
@@ -147,9 +147,9 @@ OSAL_IRQ_HANDLER(Vector68) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & (1U << 4);
- EXTI->PR = pr;
+ pr = EXTI_D1->PR1;
+ pr &= EXTI_D1->IMR1 & (1U << 4);
+ EXTI_D1->PR1 = pr;
exti_serve_irq(pr, 4);
@@ -168,10 +168,10 @@ OSAL_IRQ_HANDLER(Vector9C) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
- (1U << 9));
- EXTI->PR = pr;
+ pr = EXTI_D1->PR1;
+ pr &= EXTI_D1->IMR1 & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) |
+ (1U << 9));
+ EXTI_D1->PR1 = pr;
exti_serve_irq(pr, 5);
exti_serve_irq(pr, 6);
@@ -194,10 +194,10 @@ OSAL_IRQ_HANDLER(VectorE0) {
OSAL_IRQ_PROLOGUE();
- pr = EXTI->PR;
- pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
- (1U << 14) | (1U << 15));
- EXTI->PR = pr;
+ pr = EXTI_D1->PR1;
+ pr &= EXTI_D1->IMR1 & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
+ (1U << 14) | (1U << 15));
+ EXTI_D1->PR1 = pr;
exti_serve_irq(pr, 10);
exti_serve_irq(pr, 11);