diff options
20 files changed, 1122 insertions, 0 deletions
diff --git a/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h b/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h index 6cf75522e..1f64ba63c 100644 --- a/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h +++ b/demos/STM32/NIL-STM32F051-DISCOVERY/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h index 167038e23..01f3b6890 100644 --- a/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32F030R8-NUCLEO/mcuconf.h @@ -104,6 +104,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/demos/STM32/RT-STM32F031K6-NUCLEO32/mcuconf.h b/demos/STM32/RT-STM32F031K6-NUCLEO32/mcuconf.h index aab10219b..796844730 100644 --- a/demos/STM32/RT-STM32F031K6-NUCLEO32/mcuconf.h +++ b/demos/STM32/RT-STM32F031K6-NUCLEO32/mcuconf.h @@ -104,6 +104,18 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/demos/STM32/RT-STM32F042K6-NUCLEO32/mcuconf.h b/demos/STM32/RT-STM32F042K6-NUCLEO32/mcuconf.h index c29f07510..62486d29d 100644 --- a/demos/STM32/RT-STM32F042K6-NUCLEO32/mcuconf.h +++ b/demos/STM32/RT-STM32F042K6-NUCLEO32/mcuconf.h @@ -104,6 +104,18 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h index 6cf75522e..1f64ba63c 100644 --- a/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F051-DISCOVERY/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h index cb4117dc1..6c4701d64 100644 --- a/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F072-DISCOVERY/mcuconf.h @@ -115,6 +115,44 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/demos/STM32/RT-STM32F072RB-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F072RB-NUCLEO/mcuconf.h index b7cc3a9af..c04bba45f 100644 --- a/demos/STM32/RT-STM32F072RB-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32F072RB-NUCLEO/mcuconf.h @@ -107,6 +107,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h index 439037864..d95036926 100644 --- a/demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32F091RC-NUCLEO/mcuconf.h @@ -107,6 +107,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c b/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c new file mode 100644 index 000000000..b81004a2c --- /dev/null +++ b/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c @@ -0,0 +1,457 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file i2s_lld.c
+ * @brief STM32 I2S subsystem low level driver source.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define I2S1_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \
+ STM32_SPI1_RX_DMA_CHN)
+
+#define I2S1_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \
+ STM32_SPI1_TX_DMA_CHN)
+
+#define I2S2_RX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \
+ STM32_SPI2_RX_DMA_CHN)
+
+#define I2S2_TX_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \
+ STM32_SPI2_TX_DMA_CHN)
+
+/*
+ * Static I2S settings for I2S1.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
+
+/*
+ * Static I2S settings for I2S2.
+ */
+#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE)
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG 0
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
+#endif
+#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
+#endif
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
+ SPI_I2SCFGR_I2SCFG_0)
+#endif
+#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SP3_MODE) */
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief I2S1 driver identifier.*/
+#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__)
+I2SDriver I2SD1;
+#endif
+
+/** @brief I2S2 driver identifier.*/
+#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__)
+I2SDriver I2SD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \
+ STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared end-of-rx service routine.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+ (void)i2sp;
+
+ /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_I2S_DMA_ERROR_HOOK(i2sp);
+ }
+#endif
+
+ /* Callbacks handling, note it is portable code defined in the high
+ level driver.*/
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _i2s_isr_full_code(i2sp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _i2s_isr_half_code(i2sp);
+ }
+}
+#endif
+
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared end-of-tx service routine.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ */
+static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
+
+ (void)i2sp;
+
+ /* DMA errors handling.*/
+#if defined(STM32_I2S_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_I2S_DMA_ERROR_HOOK(i2sp);
+ }
+#endif
+
+ /* Callbacks handling, note it is portable code defined in the high
+ level driver.*/
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _i2s_isr_full_code(i2sp);
+ }
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _i2s_isr_half_code(i2sp);
+ }
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2S driver initialization.
+ *
+ * @notapi
+ */
+void i2s_lld_init(void) {
+
+#if STM32_I2S_USE_SPI1
+ i2sObjectInit(&I2SD1);
+ I2SD1.spi = SPI1;
+ I2SD1.cfg = STM32_I2S1_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+ I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM);
+ I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD1.dmarx = NULL;
+ I2SD1.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+ I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM);
+ I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD1.dmatx = NULL;
+ I2SD1.txdmamode = 0;
+#endif
+#endif
+
+#if STM32_I2S_USE_SPI2
+ i2sObjectInit(&I2SD2);
+ I2SD2.spi = SPI2;
+ I2SD2.cfg = STM32_I2S2_CFGR_CFG;
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+ I2SD2.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI2_RX_DMA_STREAM);
+ I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD2.dmarx = NULL;
+ I2SD2.rxdmamode = 0;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+ I2SD2.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI2_TX_DMA_STREAM);
+ I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_HWORD |
+ STM32_DMA_CR_MSIZE_HWORD |
+ STM32_DMA_CR_DIR_M2P |
+ STM32_DMA_CR_MINC |
+ STM32_DMA_CR_CIRC |
+ STM32_DMA_CR_HTIE |
+ STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE |
+ STM32_DMA_CR_TEIE;
+#else
+ I2SD2.dmatx = NULL;
+ I2SD2.txdmamode = 0;
+#endif
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start(I2SDriver *i2sp) {
+
+ /* If in stopped state then enables the SPI and DMA clocks.*/
+ if (i2sp->state == I2S_STOP) {
+
+#if STM32_I2S_USE_SPI1
+ if (&I2SD1 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI1(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ /* CRs settings are done here because those never changes until
+ the driver is stopped.*/
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+#if STM32_I2S_USE_SPI2
+ if (&I2SD2 == i2sp) {
+ bool b;
+
+ /* Enabling I2S unit clock.*/
+ rccEnableSPI2(FALSE);
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
+ b = dmaStreamAllocate(i2sp->dmarx,
+ STM32_I2S_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
+#endif
+#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+ b = dmaStreamAllocate(i2sp->dmatx,
+ STM32_I2S_SPI2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
+ (void *)i2sp);
+ osalDbgAssert(!b, "stream already allocated");
+
+ i2sp->spi->CR1 = 0;
+ i2sp->spi->CR2 = SPI_CR2_TXDMAEN;
+#endif
+ }
+#endif
+ }
+
+ /* I2S (re)configuration.*/
+ i2sp->spi->I2SPR = i2sp->config->i2spr;
+ i2sp->spi->I2SCFGR = i2sp->config->i2scfgr | i2sp->cfg | SPI_I2SCFGR_I2SMOD;
+}
+
+/**
+ * @brief Deactivates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop(I2SDriver *i2sp) {
+
+ /* If in ready state then disables the SPI clock.*/
+ if (i2sp->state == I2S_READY) {
+
+ /* SPI disable.*/
+ i2sp->spi->CR2 = 0;
+ if (NULL != i2sp->dmarx)
+ dmaStreamRelease(i2sp->dmarx);
+ if (NULL != i2sp->dmatx)
+ dmaStreamRelease(i2sp->dmatx);
+
+#if STM32_I2S_USE_SPI1
+ if (&I2SD1 == i2sp)
+ rccDisableSPI1(FALSE);
+#endif
+#if STM32_I2S_USE_SPI2
+ if (&I2SD2 == i2sp)
+ rccDisableSPI2(FALSE);
+#endif
+ }
+}
+
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start_exchange(I2SDriver *i2sp) {
+ size_t size = i2sp->config->size;
+
+ /* In 32 bit modes the DMA has to perform double operations because fetches
+ are always performed using 16 bit accesses.
+ DATLEN CHLEN SIZE
+ 00 (16) 0 (16) 16
+ 00 (16) 1 (32) 16
+ 01 (24) X 32
+ 10 (32) X 32
+ 11 (NA) X NA
+ */
+ if ((i2sp->config->i2scfgr & SPI_I2SCFGR_DATLEN) != 0)
+ size *= 2;
+
+ /* RX DMA setup.*/
+ if (NULL != i2sp->dmarx) {
+ dmaStreamSetMode(i2sp->dmarx, i2sp->rxdmamode);
+ dmaStreamSetPeripheral(i2sp->dmarx, &i2sp->spi->DR);
+ dmaStreamSetMemory0(i2sp->dmarx, i2sp->config->rx_buffer);
+ dmaStreamSetTransactionSize(i2sp->dmarx, size);
+ dmaStreamEnable(i2sp->dmarx);
+ }
+
+ /* TX DMA setup.*/
+ if (NULL != i2sp->dmatx) {
+ dmaStreamSetMode(i2sp->dmatx, i2sp->txdmamode);
+ dmaStreamSetPeripheral(i2sp->dmatx, &i2sp->spi->DR);
+ dmaStreamSetMemory0(i2sp->dmatx, i2sp->config->tx_buffer);
+ dmaStreamSetTransactionSize(i2sp->dmatx, size);
+ dmaStreamEnable(i2sp->dmatx);
+ }
+
+ /* Starting transfer.*/
+ i2sp->spi->I2SCFGR |= SPI_I2SCFGR_I2SE;
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop_exchange(I2SDriver *i2sp) {
+
+ /* Stop TX DMA, if enabled.*/
+ if (NULL != i2sp->dmatx) {
+ dmaStreamDisable(i2sp->dmatx);
+
+ /* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
+ to wait for TXE = 1 and BSY = 0.*/
+ while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
+ ;
+ }
+
+ /* Stop SPI/I2S peripheral.*/
+ i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
+
+ /* Stop RX DMA, if enabled.*/
+ if (NULL != i2sp->dmarx)
+ dmaStreamDisable(i2sp->dmarx);
+}
+
+#endif /* HAL_USE_I2S */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h b/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h new file mode 100644 index 000000000..df88ed9b9 --- /dev/null +++ b/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.h @@ -0,0 +1,351 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file i2s_lld.h
+ * @brief STM32 I2S subsystem low level driver header.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef _I2S_LLD_H_
+#define _I2S_LLD_H_
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Static I2S modes
+ * @{
+ */
+#define STM32_I2S_MODE_SLAVE 0
+#define STM32_I2S_MODE_MASTER 1
+#define STM32_I2S_MODE_RX 2
+#define STM32_I2S_MODE_TX 4
+#define STM32_I2S_MODE_RXTX (STM32_I2S_MODE_RX | \
+ STM32_I2S_MODE_TX)
+/** @} */
+
+/**
+ * @name Mode checks
+ * @{
+ */
+#define STM32_I2S_IS_MASTER(mode) ((mode) & STM32_I2S_MODE_MASTER)
+#define STM32_I2S_RX_ENABLED(mode) ((mode) & STM32_I2S_MODE_RX)
+#define STM32_I2S_TX_ENABLED(mode) ((mode) & STM32_I2S_MODE_TX)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief I2S1 driver enable switch.
+ * @details If set to @p TRUE the support for I2S1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI1 FALSE
+#endif
+
+/**
+ * @brief I2S2 driver enable switch.
+ * @details If set to @p TRUE the support for I2S2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_SPI2 FALSE
+#endif
+
+/**
+ * @brief I2S1 mode.
+ */
+#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S2 mode.
+ */
+#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#endif
+
+/**
+ * @brief I2S1 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief I2S2 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief I2S1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S DMA error hook.
+ */
+#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
+#error "I2S1 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \
+ STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
+#error "I2S2 RX and TX mode not supported in this driver implementation"
+#endif
+
+#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2
+#error "SPI2 not present in the selected device"
+#endif
+
+#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2
+#error "I2S driver activated but no SPI peripheral assigned"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI2"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI1"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to SPI2"
+#endif
+
+/* The following checks are only required when there is a DMA able to
+ reassign streams to different channels.*/
+#if STM32_ADVANCED_DMA
+/* Check on the presence of the DMA streams settings in mcuconf.h.*/
+#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI1_TX_DMA_STREAM))
+#error "SPI1 DMA streams not defined"
+#endif
+
+#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \
+ !defined(STM32_I2S_SPI2_TX_DMA_STREAM))
+#error "SPI2 DMA streams not defined"
+#endif
+
+/* Check on the validity of the assigned DMA channels.*/
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 RX"
+#endif
+
+#if STM32_I2S_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI1 TX"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 RX"
+#endif
+
+#if STM32_I2S_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
+#error "invalid DMA stream associated to SPI2 TX"
+#endif
+#endif /* STM32_ADVANCED_DMA */
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an I2S driver.
+ */
+typedef struct I2SDriver I2SDriver;
+
+/**
+ * @brief I2S notification callback type.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] offset offset in buffers of the data to read/write
+ * @param[in] n number of samples to read/write
+ */
+typedef void (*i2scallback_t)(I2SDriver *i2sp, size_t offset, size_t n);
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Transmission buffer pointer.
+ * @note Can be @p NULL if TX is not required.
+ */
+ const void *tx_buffer;
+ /**
+ * @brief Receive buffer pointer.
+ * @note Can be @p NULL if RX is not required.
+ */
+ void *rx_buffer;
+ /**
+ * @brief TX and RX buffers size as number of samples.
+ */
+ size_t size;
+ /**
+ * @brief Callback function called during streaming.
+ */
+ i2scallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Configuration of the I2SCFGR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S configuration, the following bits must not be
+ * specified because handled directly by the driver:
+ * - I2SMOD
+ * - I2SE
+ * - I2SCFG
+ * .
+ */
+ int16_t i2scfgr;
+ /**
+ * @brief Configuration of the I2SPR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S clock setup.
+ */
+ int16_t i2spr;
+} I2SConfig;
+
+/**
+ * @brief Structure representing an I2S driver.
+ */
+struct I2SDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2sstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2SConfig *config;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the SPIx registers block.
+ */
+ SPI_TypeDef *spi;
+ /**
+ * @brief Calculated part of the I2SCFGR register.
+ */
+ uint16_t cfg;
+ /**
+ * @brief Receive DMA stream or @p NULL.
+ */
+ const stm32_dma_stream_t *dmarx;
+ /**
+ * @brief Transmit DMA stream or @p NULL.
+ */
+ const stm32_dma_stream_t *dmatx;
+ /**
+ * @brief RX DMA mode bit mask.
+ */
+ uint32_t rxdmamode;
+ /**
+ * @brief TX DMA mode bit mask.
+ */
+ uint32_t txdmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD1;
+#endif
+
+#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2s_lld_init(void);
+ void i2s_lld_start(I2SDriver *i2sp);
+ void i2s_lld_stop(I2SDriver *i2sp);
+ void i2s_lld_start_exchange(I2SDriver *i2sp);
+ void i2s_lld_stop_exchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S */
+
+#endif /* _I2S_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index 2cbeab8cf..78918b19c 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -28,6 +28,9 @@ endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c
endif
+ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c
+endif
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c
endif
@@ -61,6 +64,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
diff --git a/readme.txt b/readme.txt index 16ee96e32..215858285 100644 --- a/readme.txt +++ b/readme.txt @@ -73,6 +73,7 @@ *****************************************************************************
*** 3.1.0 ***
+- HAL: Added I2S driver for STM32 SPIv2 peripheral.
- HAL: Added demos and board files for ST's Nucleo32 boards (F031, F042, F303).
- HAL: Added "lines" handling to PAL driver, lines are identifiers of both
ports and pins encoded in a single value. Added a set of macros
diff --git a/testhal/STM32/STM32F0xx/ADC/mcuconf.h b/testhal/STM32/STM32F0xx/ADC/mcuconf.h index 5eb9fe01d..8c7d02cc8 100644 --- a/testhal/STM32/STM32F0xx/ADC/mcuconf.h +++ b/testhal/STM32/STM32F0xx/ADC/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/testhal/STM32/STM32F0xx/CAN/mcuconf.h b/testhal/STM32/STM32F0xx/CAN/mcuconf.h index 481927aa6..2aafb6c0c 100644 --- a/testhal/STM32/STM32F0xx/CAN/mcuconf.h +++ b/testhal/STM32/STM32F0xx/CAN/mcuconf.h @@ -115,6 +115,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/testhal/STM32/STM32F0xx/EXT/mcuconf.h b/testhal/STM32/STM32F0xx/EXT/mcuconf.h index 98aeadc05..ca6f88189 100644 --- a/testhal/STM32/STM32F0xx/EXT/mcuconf.h +++ b/testhal/STM32/STM32F0xx/EXT/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h index b918f8275..0fd378df9 100644 --- a/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32/STM32F0xx/IRQ_STORM/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h b/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h index be2b64928..92d837cd5 100644 --- a/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32/STM32F0xx/PWM-ICU/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/testhal/STM32/STM32F0xx/SPI/mcuconf.h b/testhal/STM32/STM32F0xx/SPI/mcuconf.h index 05a934710..3a28db991 100644 --- a/testhal/STM32/STM32F0xx/SPI/mcuconf.h +++ b/testhal/STM32/STM32F0xx/SPI/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/testhal/STM32/STM32F0xx/UART/mcuconf.h b/testhal/STM32/STM32F0xx/UART/mcuconf.h index 13568f1cf..2045c8dbd 100644 --- a/testhal/STM32/STM32F0xx/UART/mcuconf.h +++ b/testhal/STM32/STM32F0xx/UART/mcuconf.h @@ -109,6 +109,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
diff --git a/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h b/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h index c0ef22c93..becbed310 100644 --- a/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h +++ b/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h @@ -115,6 +115,25 @@ #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI1 FALSE
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
+ STM32_I2S_MODE_RX)
+#define STM32_I2S_SPI1_IRQ_PRIORITY 2
+#define STM32_I2S_SPI2_IRQ_PRIORITY 2
+#define STM32_I2S_SPI1_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
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