diff options
-rw-r--r-- | os/hal/platforms/SPC56ELxx/platform.mk | 2 | ||||
-rw-r--r-- | os/hal/platforms/SPC56ELxx/spc56el_registry.h | 38 | ||||
-rw-r--r-- | testhal/SPC560Pxx/SPI/main.c | 2 | ||||
-rw-r--r-- | testhal/SPC56ELxx/SPI/.project | 2 | ||||
-rw-r--r-- | testhal/SPC56ELxx/SPI/Makefile | 2 | ||||
-rw-r--r-- | testhal/SPC56ELxx/SPI/main.c | 2 | ||||
-rw-r--r-- | testhal/SPC56ELxx/SPI/mcuconf.h | 53 |
7 files changed, 97 insertions, 4 deletions
diff --git a/os/hal/platforms/SPC56ELxx/platform.mk b/os/hal/platforms/SPC56ELxx/platform.mk index 267b25664..07f558c7c 100644 --- a/os/hal/platforms/SPC56ELxx/platform.mk +++ b/os/hal/platforms/SPC56ELxx/platform.mk @@ -1,5 +1,6 @@ # List of all the SPC56ELxx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c \
@@ -8,6 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx/hal_lld.c \ # Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1 \
diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h index fcbd3d3d8..83fdab87c 100644 --- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h +++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h @@ -38,6 +38,44 @@ #define SPC5_EDMA_NCHANNELS 16
#define SPC5_EDMA_HAS_MUX TRUE
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_HAS_DSPI3 FALSE
+#define SPC5_HAS_DSPI4 FALSE
+#define SPC5_DSPI_FIFO_DEPTH 5
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+#define SPC5_DSPI2_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
+#define SPC5_DSPI2_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
+
/* LINFlex attributes.*/
#define SPC5_HAS_LINFLEX0 TRUE
#define SPC5_LINFLEX0_PCTL 48
diff --git a/testhal/SPC560Pxx/SPI/main.c b/testhal/SPC560Pxx/SPI/main.c index 5be1f0e17..1178c7377 100644 --- a/testhal/SPC560Pxx/SPI/main.c +++ b/testhal/SPC560Pxx/SPI/main.c @@ -111,7 +111,7 @@ int main(void) { for (i = 0; i < sizeof(txbuf); i++)
txbuf[i] = (uint8_t)i;
- /* Starting driver for test, DSPI_B I/O pins setup.*/
+ /* Starting driver for test, DSPI_1 I/O pins setup.*/
spiStart(&SPID1, &ls_spicfg);
SIU.PCR[37].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */
SIU.PCR[38].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
diff --git a/testhal/SPC56ELxx/SPI/.project b/testhal/SPC56ELxx/SPI/.project index 3029087d0..c5157f21e 100644 --- a/testhal/SPC56ELxx/SPI/.project +++ b/testhal/SPC56ELxx/SPI/.project @@ -27,7 +27,7 @@ <link>
<name>board</name>
<type>2</type>
- <locationURI>CHIBIOS/boards/ST_EVB_SPC560P</locationURI>
+ <locationURI>CHIBIOS/boards/ST_EVB_SPC56EL</locationURI>
</link>
<link>
<name>os</name>
diff --git a/testhal/SPC56ELxx/SPI/Makefile b/testhal/SPC56ELxx/SPI/Makefile index ea777f395..afc709b93 100644 --- a/testhal/SPC56ELxx/SPI/Makefile +++ b/testhal/SPC56ELxx/SPI/Makefile @@ -59,7 +59,7 @@ include $(CHIBIOS)/os/kernel/kernel.mk #include $(CHIBIOS)/test/test.mk
# Define linker script file here
-LDSCRIPT= $(PORTLD)/SPC56EL70_LSM.ld
+LDSCRIPT= $(PORTLD)/SPC56EL60_LSM.ld
# C sources here.
CSRC = $(PORTSRC) \
diff --git a/testhal/SPC56ELxx/SPI/main.c b/testhal/SPC56ELxx/SPI/main.c index 5be1f0e17..06ef48689 100644 --- a/testhal/SPC56ELxx/SPI/main.c +++ b/testhal/SPC56ELxx/SPI/main.c @@ -111,7 +111,7 @@ int main(void) { for (i = 0; i < sizeof(txbuf); i++)
txbuf[i] = (uint8_t)i;
- /* Starting driver for test, DSPI_B I/O pins setup.*/
+ /* Starting driver for test, DSPI_0 I/O pins setup.*/
spiStart(&SPID1, &ls_spicfg);
SIU.PCR[37].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */
SIU.PCR[38].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
diff --git a/testhal/SPC56ELxx/SPI/mcuconf.h b/testhal/SPC56ELxx/SPI/mcuconf.h index 435c18e86..922e4efc6 100644 --- a/testhal/SPC56ELxx/SPI/mcuconf.h +++ b/testhal/SPC56ELxx/SPI/mcuconf.h @@ -217,3 +217,56 @@ SPC5_ME_PCTL_LP(2))
#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 TRUE
+#define SPC5_SPI_USE_DSPI1 TRUE
+#define SPC5_SPI_USE_DSPI2 TRUE
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_DMA_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_PRIO 10
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
|