diff options
| -rw-r--r-- | boards/GENERIC_SPC560B/board.c | 73 | ||||
| -rw-r--r-- | boards/GENERIC_SPC560B/board.h | 72 | ||||
| -rw-r--r-- | boards/GENERIC_SPC560B/board.mk | 5 | ||||
| -rw-r--r-- | boards/GENERIC_SPC560P/board.c | 8 | ||||
| -rw-r--r-- | boards/GENERIC_SPC560P/board.h | 2 | ||||
| -rw-r--r-- | demos/PPC-SPC560B-GCC/.cproject | 51 | ||||
| -rw-r--r-- | demos/PPC-SPC560B-GCC/.project | 43 | ||||
| -rw-r--r-- | demos/PPC-SPC560B-GCC/Makefile | 163 | ||||
| -rw-r--r-- | demos/PPC-SPC560B-GCC/chconf.h | 535 | ||||
| -rw-r--r-- | demos/PPC-SPC560B-GCC/halconf.h | 342 | ||||
| -rw-r--r-- | demos/PPC-SPC560B-GCC/main.c | 203 | ||||
| -rw-r--r-- | demos/PPC-SPC560B-GCC/mcuconf.h | 159 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/hal_lld.c | 253 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/hal_lld.h | 735 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/platform.mk | 9 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/spc560bc_registry.h | 73 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/spc560p_registry.h | 10 |
17 files changed, 2726 insertions, 10 deletions
diff --git a/boards/GENERIC_SPC560B/board.c b/boards/GENERIC_SPC560B/board.c new file mode 100644 index 000000000..bdcddbf2a --- /dev/null +++ b/boards/GENERIC_SPC560B/board.c @@ -0,0 +1,73 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* Initial setup of all defined pads, the list is terminated by a {0, 0}.*/
+static const spc_siu_init_t spc_siu_init[] = {
+ {PCR(PB, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
+ {PCR(PB, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
+ {PCR(PD, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PD, PD_BUTTON2), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PD, PD_BUTTON3), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PD, PD_BUTTON4), PAL_LOW, PAL_MODE_INPUT},
+ {PCR(PD, PD_LED1), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PD, PD_LED2), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PD, PD_LED3), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {PCR(PD, PD_LED4), PAL_HIGH, PAL_MODE_OUTPUT_PUSHPULL},
+ {0, 0, 0}
+};
+
+/* Initialization array for the PSMI registers.*/
+static const uint8_t spc_padsels_init[SPC5_SIU_NUM_PADSELS] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0
+};
+
+/**
+ * @brief PAL setup.
+ */
+const PALConfig pal_default_config =
+{
+ PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
+ spc_siu_init,
+ spc_padsels_init
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ spc560bc_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
diff --git a/boards/GENERIC_SPC560B/board.h b/boards/GENERIC_SPC560B/board.h new file mode 100644 index 000000000..afaaab95d --- /dev/null +++ b/boards/GENERIC_SPC560B/board.h @@ -0,0 +1,72 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic SPC560Pxx proto board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_GENERIC_SPC560BC
+#define BOARD_NAME "Generic SPC560B/C"
+
+/*
+ * Board frequencies.
+ */
+#if !defined(SPC5_XOSC_CLK)
+#define SPC5_XOSC_CLK 40000000
+#endif
+
+/*
+ * I/O definitions.
+ */
+#define PB_LIN0_TDX 2
+#define PB_LIN0_RDX 3
+
+#define PD_BUTTON1 0
+#define PD_BUTTON2 1
+#define PD_BUTTON3 2
+#define PD_BUTTON4 3
+
+#define PD_LED1 4
+#define PD_LED2 5
+#define PD_LED3 6
+#define PD_LED4 7
+
+/*
+ * Support macros.
+ */
+#define PCR(port, pin) (((port) * 16) + (pin))
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/GENERIC_SPC560B/board.mk b/boards/GENERIC_SPC560B/board.mk new file mode 100644 index 000000000..26a9dc606 --- /dev/null +++ b/boards/GENERIC_SPC560B/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/GENERIC_SPC560B/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/GENERIC_SPC560B
diff --git a/boards/GENERIC_SPC560P/board.c b/boards/GENERIC_SPC560P/board.c index 23154bf8d..caa317ec5 100644 --- a/boards/GENERIC_SPC560P/board.c +++ b/boards/GENERIC_SPC560P/board.c @@ -23,7 +23,7 @@ #if HAL_USE_PAL || defined(__DOXYGEN__)
/* Initial setup of all defined pads, the list is terminated by a {0, 0}.*/
-static const spc560p_siu_init_t spc560p_siu_init[] = {
+static const spc_siu_init_t spc_siu_init[] = {
{PCR(PB, PB_LIN0_TDX), PAL_HIGH, PAL_MODE_OUTPUT_ALTERNATE(1)},
{PCR(PB, PB_LIN0_RDX), PAL_HIGH, PAL_MODE_INPUT},
{PCR(PD, PD_BUTTON1), PAL_LOW, PAL_MODE_INPUT},
@@ -38,7 +38,7 @@ static const spc560p_siu_init_t spc560p_siu_init[] = { };
/* Initialization array for the PSMI registers.*/
-static const uint8_t spc560p_padsels_init[SPC5_SIU_NUM_PADSELS] = {
+static const uint8_t spc_padsels_init[SPC5_SIU_NUM_PADSELS] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0
@@ -50,8 +50,8 @@ static const uint8_t spc560p_padsels_init[SPC5_SIU_NUM_PADSELS] = { const PALConfig pal_default_config =
{
PAL_MODE_UNCONNECTED, /* Default mode for all undefined pads. */
- spc560p_siu_init,
- spc560p_padsels_init
+ spc_siu_init,
+ spc_padsels_init
};
#endif
diff --git a/boards/GENERIC_SPC560P/board.h b/boards/GENERIC_SPC560P/board.h index 60edcddec..48a49efc2 100644 --- a/boards/GENERIC_SPC560P/board.h +++ b/boards/GENERIC_SPC560P/board.h @@ -34,7 +34,7 @@ /*
* Board frequencies.
*/
-#if !defined(SPC560P_XOSC_CLK)
+#if !defined(SPC5_XOSC_CLK)
#define SPC5_XOSC_CLK 40000000
#endif
diff --git a/demos/PPC-SPC560B-GCC/.cproject b/demos/PPC-SPC560B-GCC/.cproject new file mode 100644 index 000000000..e19c57021 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/.cproject @@ -0,0 +1,51 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="0.778696284">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.778696284" moduleId="org.eclipse.cdt.core.settings" name="Default">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.778696284" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="0.778696284." name="/" resourcePath="">
+ <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.703039574" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+ <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.703039574.698750103" name=""/>
+ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.1125760427" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.libs.1133430474" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.2011970588" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.602168709" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1522568014" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.43131549" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1510705071" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.955603873" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="PPC-SPC560B-GCC.null.1435802540" name="PPC-SPC560B-GCC"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="0.778696284">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>
diff --git a/demos/PPC-SPC560B-GCC/.project b/demos/PPC-SPC560B-GCC/.project new file mode 100644 index 000000000..4b947d3ed --- /dev/null +++ b/demos/PPC-SPC560B-GCC/.project @@ -0,0 +1,43 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>PPC-SPC560B-GCC</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>board</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/boards/GENERIC_SPC560P</locationURI>
+ </link>
+ <link>
+ <name>os</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os</locationURI>
+ </link>
+ <link>
+ <name>test</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/test</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/demos/PPC-SPC560B-GCC/Makefile b/demos/PPC-SPC560B-GCC/Makefile new file mode 100644 index 000000000..62303fdd1 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/Makefile @@ -0,0 +1,163 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data.
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = no
+endif
+
+# If enabled, this option allows to compile the application in VLE mode.
+ifeq ($(USE_VLE),)
+ USE_VLE = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files
+CHIBIOS = ../..
+include $(CHIBIOS)/boards/GENERIC_SPC560P/board.mk
+include $(CHIBIOS)/os/hal/platforms/SPC560Pxx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Pxx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/test/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/SPC560P44.ld
+
+# C sources here.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/os/various/evtimer.c \
+ $(CHIBIOS)/os/various/shell.c \
+ $(CHIBIOS)/os/various/chprintf.c \
+ main.c
+
+# C++ sources here.
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames
+MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames
+
+#TRGT = powerpc-eabi-
+TRGT = ppc-vle-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk
diff --git a/demos/PPC-SPC560B-GCC/chconf.h b/demos/PPC-SPC560B-GCC/chconf.h new file mode 100644 index 000000000..b1f2cd62c --- /dev/null +++ b/demos/PPC-SPC560B-GCC/chconf.h @@ -0,0 +1,535 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread automatically. The application has
+ * then the responsibility to do one of the following:
+ * - Spawn a custom idle thread at priority @p IDLEPRIO.
+ * - Change the main() thread priority to @p IDLEPRIO then enter
+ * an endless loop. In this scenario the @p main() thread acts as
+ * the idle thread.
+ * .
+ * @note Unless an idle thread is spawned the @p main() thread must not
+ * enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE FALSE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS FALSE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+#endif
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() { \
+ /* System tick event code here.*/ \
+}
+#endif
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/PPC-SPC560B-GCC/halconf.h b/demos/PPC-SPC560B-GCC/halconf.h new file mode 100644 index 000000000..c9b3ad25a --- /dev/null +++ b/demos/PPC-SPC560B-GCC/halconf.h @@ -0,0 +1,342 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM FALSE
+#endif
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Block size for MMC transfers.
+ */
+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
+#define MMC_SECTOR_SIZE 512
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/**
+ * @brief Number of positive insertion queries before generating the
+ * insertion event.
+ */
+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
+#define MMC_POLLING_INTERVAL 10
+#endif
+
+/**
+ * @brief Interval, in milliseconds, between insertion queries.
+ */
+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
+#define MMC_POLLING_DELAY 10
+#endif
+
+/**
+ * @brief Uses the SPI polled API for small data transfers.
+ * @details Polled transfers usually improve performance because it
+ * saves two context switches and interrupt servicing. Note
+ * that this option has no effect on large transfers which
+ * are always performed using DMAs/IRQs.
+ */
+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
+#define MMC_USE_SPI_POLLING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/PPC-SPC560B-GCC/main.c b/demos/PPC-SPC560B-GCC/main.c new file mode 100644 index 000000000..b296da222 --- /dev/null +++ b/demos/PPC-SPC560B-GCC/main.c @@ -0,0 +1,203 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+#include "shell.h"
+#include "chprintf.h"
+
+#define SHELL_WA_SIZE THD_WA_SIZE(1024)
+#define TEST_WA_SIZE THD_WA_SIZE(256)
+
+static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
+ size_t n, size;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: mem\r\n");
+ return;
+ }
+ n = chHeapStatus(NULL, &size);
+ chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus());
+ chprintf(chp, "heap fragments : %u\r\n", n);
+ chprintf(chp, "heap free total : %u bytes\r\n", size);
+}
+
+static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
+ static const char *states[] = {THD_STATE_NAMES};
+ Thread *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: threads\r\n");
+ return;
+ }
+ chprintf(chp, " addr stack prio refs state time\r\n");
+ tp = chRegFirstThread();
+ do {
+ chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n",
+ (uint32_t)tp, (uint32_t)tp->p_ctx.sp,
+ (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
+ states[tp->p_state], (uint32_t)tp->p_time);
+ tp = chRegNextThread(tp);
+ } while (tp != NULL);
+}
+
+static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
+ Thread *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: test\r\n");
+ return;
+ }
+ tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(),
+ TestThread, chp);
+ if (tp == NULL) {
+ chprintf(chp, "out of memory\r\n");
+ return;
+ }
+ chThdWait(tp);
+}
+
+static const ShellCommand commands[] = {
+ {"mem", cmd_mem},
+ {"threads", cmd_threads},
+ {"test", cmd_test},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+ (BaseSequentialStream *)&SD1,
+ commands
+};
+
+/*
+ * LEDs blinker thread, times are in milliseconds.
+ */
+static WORKING_AREA(waThread1, 128);
+static msg_t Thread1(void *arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+
+ while (TRUE) {
+ unsigned i;
+
+ for (i = 0; i < 4; i++) {
+ palClearPad(PD, PD_LED1);
+ chThdSleepMilliseconds(100);
+ palClearPad(PD, PD_LED2);
+ chThdSleepMilliseconds(100);
+ palClearPad(PD, PD_LED3);
+ chThdSleepMilliseconds(100);
+ palClearPad(PD, PD_LED4);
+ chThdSleepMilliseconds(100);
+ palSetPad(PD, PD_LED1);
+ chThdSleepMilliseconds(100);
+ palSetPad(PD, PD_LED2);
+ chThdSleepMilliseconds(100);
+ palSetPad(PD, PD_LED3);
+ chThdSleepMilliseconds(100);
+ palSetPad(PD, PD_LED4);
+ chThdSleepMilliseconds(300);
+ }
+
+ for (i = 0; i < 4; i++) {
+ palTogglePort(PD, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) |
+ PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4));
+ chThdSleepMilliseconds(500);
+ palTogglePort(PD, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) |
+ PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4));
+ chThdSleepMilliseconds(500);
+ }
+
+ for (i = 0; i < 4; i++) {
+ palTogglePad(PD, PD_LED1);
+ chThdSleepMilliseconds(250);
+ palTogglePad(PD, PD_LED1);
+ palTogglePad(PD, PD_LED2);
+ chThdSleepMilliseconds(250);
+ palTogglePad(PD, PD_LED2);
+ palTogglePad(PD, PD_LED3);
+ chThdSleepMilliseconds(250);
+ palTogglePad(PD, PD_LED3);
+ palTogglePad(PD, PD_LED4);
+ chThdSleepMilliseconds(250);
+ palTogglePad(PD, PD_LED4);
+ }
+
+ for (i = 0; i < 4; i++) {
+ palClearPort(PD, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED3));
+ palSetPort(PD, PAL_PORT_BIT(PD_LED2) | PAL_PORT_BIT(PD_LED4));
+ chThdSleepMilliseconds(500);
+ palClearPort(PD, PAL_PORT_BIT(PD_LED2) | PAL_PORT_BIT(PD_LED4));
+ palSetPort(PD, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED3));
+ chThdSleepMilliseconds(500);
+ }
+
+ palSetPort(PD, PAL_PORT_BIT(PD_LED1) | PAL_PORT_BIT(PD_LED2) |
+ PAL_PORT_BIT(PD_LED3) | PAL_PORT_BIT(PD_LED4));
+ }
+ return 0;
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ Thread *shelltp = NULL;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the serial driver 1 using the driver default configuration.
+ */
+ sdStart(&SD1, NULL);
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity.
+ */
+ while (TRUE) {
+
+ if (!shelltp)
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+ else if (chThdTerminated(shelltp)) {
+ chThdRelease(shelltp); /* Recovers memory of the previous shell. */
+ shelltp = NULL; /* Triggers spawning of a new shell. */
+ }
+ chThdSleepMilliseconds(1000);
+ }
+ return 0;
+}
diff --git a/demos/PPC-SPC560B-GCC/mcuconf.h b/demos/PPC-SPC560B-GCC/mcuconf.h new file mode 100644 index 000000000..9b1adfc1e --- /dev/null +++ b/demos/PPC-SPC560B-GCC/mcuconf.h @@ -0,0 +1,159 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * SPC560B/Cxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ */
+
+#define SPC560BCxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT FALSE
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#define SPC5_FMPLL0_IDF_VALUE 5
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_FMPLL1_IDF_VALUE 5
+#define SPC5_FMPLL1_NDIV_VALUE 60
+#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#define SPC5_PIT3_IRQ_PRIORITY 4
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 TRUE
+#define SPC5_SERIAL_USE_LINFLEX1 TRUE
+#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
+#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
+#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c new file mode 100644 index 000000000..6aba28b56 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/hal_lld.c @@ -0,0 +1,253 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560BCxx/hal_lld.c
+ * @brief SPC560B/Cxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief PIT channel 3 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(vector127) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ /* Resets the PIT channel 3 IRQ flag.*/
+ PIT.CH[3].TFLG.R = 1;
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ extern void _vectors(void);
+ uint32_t reg;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPC560PSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED)
+ chSysHalt();
+
+ /* INTC initialization, software vector mode, 4 bytes vectors, starting
+ at priority 0.*/
+ INTC.MCR.R = 0;
+ INTC.CPR.R = 0;
+ INTC.IACKR.R = (uint32_t)_vectors;
+
+ /* PIT channel 3 initialization for Kernel ticks, the PIT is configured
+ to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
+ modes.*/
+ INTC.PSR[127].R = SPC5_PIT3_IRQ_PRIORITY;
+ halSPC560PSetPeripheralClockMode(92,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+ reg = halSPC560PGetSystemClock() / CH_FREQUENCY - 1;
+ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
+ PIT.CH[3].LDVAL.R = reg;
+ PIT.CH[3].CVAL.R = reg;
+ PIT.CH[3].TFLG.R = 1; /* Interrupt flag cleared. */
+ PIT.CH[3].TCTRL.R = 3; /* Timer active, interrupt enabled. */
+}
+
+/**
+ * @brief SPC560Pxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc560p_clock_init(void) {
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.S_RC)
+ ;
+
+#if !SPC5_NO_INIT
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a xtal then the
+ bypass must be activated.*/
+ CGM.OSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_ENABLE_XOSC */
+
+ /* Initialization of the FMPLLs settings.*/
+ CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
+ ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL0_NDIV_VALUE << 16);
+ CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */
+ CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
+ (SPC5_FMPLL1_IDF_VALUE << 26) |
+ (SPC5_FMPLL1_NDIV_VALUE << 16);
+ CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */
+
+ /* Run modes initialization.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPC560PSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED)
+ chSysHalt();
+
+ /* CFLASH settings calculated for a maximum clock of 64MHz.*/
+ CFLASH.PFCR0.B.BK0_APC = 2;
+ CFLASH.PFCR0.B.BK0_RWSC = 2;
+ CFLASH.PFCR1.B.BK1_APC = 2;
+ CFLASH.PFCR1.B.BK1_RWSC = 2;
+
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval CH_SUCCESS if the switch operation has been completed.
+ * @retval CH_FAILED if the switch operation failed.
+ */
+bool_t halSPC560PSetRunMode(spc560prunmode_t mode) {
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits the transition process to start.*/
+ while (!ME.GS.B.S_MTRANS)
+ ;
+
+ /* Waits the transition process to end.*/
+ while (ME.GS.B.S_MTRANS)
+ ;
+
+ /* Verifies that the mode has been effectively switched.*/
+ if (ME.GS.B.S_CURRENTMODE != mode)
+ return CH_FAILED;
+
+ return CH_SUCCESS;
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGET_MODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPC560PGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.S_SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL1:
+ return SPC5_FMPLL1_CLK;
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h new file mode 100644 index 000000000..a09821f34 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/hal_lld.h @@ -0,0 +1,735 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560BCxx/hal_lld.h
+ * @brief SPC560B/Cxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "xpc560p.h"
+#include "spc560p_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "SPC560Pxx Chassis and Safety"
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 40000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 16000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 64000000
+
+/**
+ * @brief Maximum FMPLL1 output clock frequency.
+ */
+#define SPC5_FMPLL1_CLK_MAX 120000000
+
+/**
+ * @brief Maximum FMPLL1 1D1 output clock frequency.
+ */
+#define SPC5_FMPLL1_1D1_CLK_MAX 80000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/
+/** @} */
+
+/**
+ * @name FMPLL_CR register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL1 (5U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_TEST (2U << 0)
+#define SPC5_ME_ME_SAFE (4U << 0)
+#define SPC5_ME_ME_DRUN (8U << 0)
+#define SPC5_ME_ME_RUN0 (16U << 0)
+#define SPC5_ME_ME_RUN1 (32U << 0)
+#define SPC5_ME_ME_RUN2 (64U << 0)
+#define SPC5_ME_ME_RUN3 (128U << 0)
+#define SPC5_ME_ME_HALT0 (256U << 0)
+#define SPC5_ME_ME_STOP0 (1024U << 0)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_PLL1ON (1U << 7)
+#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
+#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
+#define SPC5_ME_MC_CFLAON_PD (1U << 16)
+#define SPC5_ME_MC_CFLAON_LP (2U << 16)
+#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
+#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
+#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
+#define SPC5_ME_MC_DFLAON_PD (1U << 18)
+#define SPC5_ME_MC_DFLAON_LP (2U << 18)
+#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_TEST (1U << 1)
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 5
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief FMPLL1 IDF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_IDF_VALUE 5
+#endif
+
+/**
+ * @brief FMPLL1 NDIV divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_NDIV_VALUE 60
+#endif
+
+/**
+ * @brief FMPLL1 ODF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0)
+#endif
+
+/**
+ * @brief TEST mode settings.
+ */
+#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief PIT channel 3 IRQ priority.
+ * @note This PIT channel is allocated permanently for system tick
+ * generation.
+ */
+#if !defined(SPC5_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT3_IRQ_PRIORITY 4
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+/* Check on SPC5_FMPLL1_IDF_VALUE.*/
+#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL1_NDIV_VALUE.*/
+#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL1_ODF.*/
+#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL1_ODF_VALUE 2
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL1_ODF_VALUE 4
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL1_ODF_VALUE 8
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL1_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL1_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL1_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL1_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
+
+/* Check on FMPLL1 VCO output.*/
+#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL1_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL1_CLK clock point.
+ */
+#define SPC5_FMPLL1_CLK \
+ (SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE)
+
+/* Check on SPC5_FMPLL1_CLK.*/
+#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+typedef enum {
+ SPC5_RUNMODE_TEST = 1,
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc560prunmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc560p_clock_init(void);
+ bool_t halSPC560PSetRunMode(spc560prunmode_t mode);
+ void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPC560PGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC560BCxx/platform.mk b/os/hal/platforms/SPC560BCxx/platform.mk new file mode 100644 index 000000000..1ce2604a6 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/platform.mk @@ -0,0 +1,9 @@ +# List of all the SPC560B/Cxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1
diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h new file mode 100644 index 000000000..1390b6575 --- /dev/null +++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h @@ -0,0 +1,73 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560BCxx/spc560bc_registry.h
+ * @brief SPC560B/Cxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _SPC560BC_REGISTRY_H_
+#define _SPC560BC_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC560Pxx capabilities
+ * @{
+ */
+/* LINFlex attributes.*/
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+
+#define SPC5_HAS_LINFLEX2 FALSE
+
+#define SPC5_HAS_LINFLEX3 FALSE
+
+/* SIU/SIUL attributes.*/
+#define SPC5_HAS_SIU FALSE
+#define SPC5_SIU_SUPPORTS_PORTS TRUE
+#define SPC5_SIU_NUM_PORTS 4
+#define SPC5_SIU_NUM_PCRS 108
+#define SPC5_SIU_NUM_PADSELS 36
+/** @} */
+
+#endif /* _SPC560BC_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index 46b7785fa..bb55dede0 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -61,11 +61,11 @@ #define SPC5_HAS_LINFLEX3 FALSE
/* SIU/SIUL attributes.*/
-#define SPC5_HAS_SIU FALSE
-#define SPC5_SIU_SUPPORTS_PORTS TRUE
-#define SPC5_SIU_NUM_PORTS 4
-#define SPC5_SIU_NUM_PCRS 108
-#define SPC5_SIU_NUM_PADSELS 36
+#define SPC5_HAS_SIU FALSE
+#define SPC5_SIU_SUPPORTS_PORTS TRUE
+#define SPC5_SIU_NUM_PORTS 4
+#define SPC5_SIU_NUM_PCRS 108
+#define SPC5_SIU_NUM_PADSELS 36
/** @} */
#endif /* _SPC560P_REGISTRY_H_ */
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