diff options
| -rw-r--r-- | demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/adc_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/adc_lld.h | 4 | ||||
| -rw-r--r-- | readme.txt | 6 | ||||
| -rw-r--r-- | testhal/STM32/ADC/main.c | 2 |
5 files changed, 11 insertions, 9 deletions
diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 07ab18537..4d4df9297 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -48,7 +48,7 @@ static const ADCConversionGroup adcgrpcfg = { adccb,
/* HW dependent part.*/
0,
- ADC_CR2_TSVREFE | ADC_CR2_CONT,
+ ADC_CR2_TSVREFE,
ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5),
0,
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),
diff --git a/os/hal/platforms/STM32/adc_lld.c b/os/hal/platforms/STM32/adc_lld.c index 1a9069c59..91fd8a6e8 100644 --- a/os/hal/platforms/STM32/adc_lld.c +++ b/os/hal/platforms/STM32/adc_lld.c @@ -204,7 +204,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup.*/
adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN;
- adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+ adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA |
+ ADC_CR2_CONT | ADC_CR2_ADON;
adcp->ad_adc->SMPR1 = grpp->acg_smpr1;
adcp->ad_adc->SMPR2 = grpp->acg_smpr2;
adcp->ad_adc->SQR1 = grpp->acg_sqr1;
@@ -212,7 +213,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->ad_adc->SQR3 = grpp->acg_sqr3;
/* ADC start by writing ADC_CR2_ADON a second time.*/
- adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
+ adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA |
+ ADC_CR2_CONT | ADC_CR2_ADON;
}
/**
diff --git a/os/hal/platforms/STM32/adc_lld.h b/os/hal/platforms/STM32/adc_lld.h index 0850b62f4..92fa21b9d 100644 --- a/os/hal/platforms/STM32/adc_lld.h +++ b/os/hal/platforms/STM32/adc_lld.h @@ -173,8 +173,8 @@ typedef struct { /**
* @brief ADC CR2 register initialization data.
* @note All the required bits must be defined into this field except
- * @p ADC_CR2_DMA and @p ADC_CR2_ADON that are enforced inside the
- * driver.
+ * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
+ * enforced inside the driver.
*/
uint32_t acg_cr2;
/**
diff --git a/readme.txt b/readme.txt index a9c0479d6..e94d15881 100644 --- a/readme.txt +++ b/readme.txt @@ -74,9 +74,9 @@ there is the possibility that the various vendors would use different
CMSIS versions now that CMSIS 2.x has been released.
- CHANGE: Modified the start of the ADC in the STM32 ADC driver, now it is
- no more required to specify ADC_CR2_EXTSEL_SWSTART in the CR2 register
- configuration. Also reordered the start sequence in order to allows a
- longer stabilization time for the ADC.
+ no more required to specify ADC_CR2_EXTSEL_SWSTART and ADC_CR2_CONT
+ in the CR2 register configuration. Also reordered the start sequence
+ in order to allows a longer stabilization time for the ADC.
*** 2.1.5 ***
- FIX: Fixed references to non-existing SSP1 device in LPC13xx SPI device
diff --git a/testhal/STM32/ADC/main.c b/testhal/STM32/ADC/main.c index ee6975046..20fa6005b 100644 --- a/testhal/STM32/ADC/main.c +++ b/testhal/STM32/ADC/main.c @@ -55,7 +55,7 @@ static const ADCConversionGroup adcgrpcfg = { ADC_GRP1_NUM_CHANNELS,
adccallback,
0,
- ADC_CR2_TSVREFE | ADC_CR2_CONT,
+ ADC_CR2_TSVREFE,
0,
0,
ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS),
|