diff options
| -rw-r--r-- | boards/GENERIC_SPC564A/board.h | 2 | ||||
| -rw-r--r-- | demos/PPC-SPC564A-GCC/mcuconf.h | 6 | ||||
| -rw-r--r-- | os/hal/platforms/SPC563Mxx/hal_lld.h | 1 | ||||
| -rw-r--r-- | os/hal/platforms/SPC564Axx/hal_lld.h | 7 | ||||
| -rw-r--r-- | os/hal/platforms/SPC564Axx/spc564a_registry.h | 4 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c | 2 |
6 files changed, 10 insertions, 12 deletions
diff --git a/boards/GENERIC_SPC564A/board.h b/boards/GENERIC_SPC564A/board.h index a5e4d0834..f97840795 100644 --- a/boards/GENERIC_SPC564A/board.h +++ b/boards/GENERIC_SPC564A/board.h @@ -29,7 +29,7 @@ * Board frequencies.
*/
#if !defined(SPC5_XOSC_CLK)
-#define SPC5_XOSC_CLK 8000000
+#define SPC5_XOSC_CLK 40000000
#endif
/*
diff --git a/demos/PPC-SPC564A-GCC/mcuconf.h b/demos/PPC-SPC564A-GCC/mcuconf.h index e759030f2..42ec272ec 100644 --- a/demos/PPC-SPC564A-GCC/mcuconf.h +++ b/demos/PPC-SPC564A-GCC/mcuconf.h @@ -31,9 +31,9 @@ #define SPC5_NO_INIT FALSE
#define SPC5_CLK_BYPASS FALSE
#define SPC5_ALLOW_OVERCLOCK FALSE
-#define SPC5_CLK_PREDIV_VALUE 2
-#define SPC5_CLK_MFD_VALUE 150
-#define SPC5_CLK_RFD SPC5_RFD_DIV4
+#define SPC5_CLK_PREDIV_VALUE 8
+#define SPC5_CLK_MFD_VALUE 60
+#define SPC5_CLK_RFD SPC5_RFD_DIV2
#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
BIUCR_MASTER4_PREFETCH | \
BIUCR_MASTER0_PREFETCH | \
diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.h b/os/hal/platforms/SPC563Mxx/hal_lld.h index 4feb08a7d..c0061556d 100644 --- a/os/hal/platforms/SPC563Mxx/hal_lld.h +++ b/os/hal/platforms/SPC563Mxx/hal_lld.h @@ -129,7 +129,6 @@ /**
* @brief External clock pre-divider.
* @note Must be in range 1...15.
- * @note The effective divider factor is this value.
*/
#if !defined(SPC5_CLK_PREDIV) || defined(__DOXYGEN__)
#define SPC5_CLK_PREDIV_VALUE 2
diff --git a/os/hal/platforms/SPC564Axx/hal_lld.h b/os/hal/platforms/SPC564Axx/hal_lld.h index c7ffd1400..7b26945a9 100644 --- a/os/hal/platforms/SPC564Axx/hal_lld.h +++ b/os/hal/platforms/SPC564Axx/hal_lld.h @@ -129,10 +129,9 @@ /**
* @brief External clock pre-divider.
* @note Must be in range 1...15.
- * @note The effective divider factor is this value.
*/
#if !defined(SPC5_CLK_PREDIV) || defined(__DOXYGEN__)
-#define SPC5_CLK_PREDIV_VALUE 2
+#define SPC5_CLK_PREDIV_VALUE 8
#endif
/**
@@ -140,14 +139,14 @@ * @note Must be in range 32...96.
*/
#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
-#define SPC5_CLK_MFD_VALUE 80
+#define SPC5_CLK_MFD_VALUE 60
#endif
/**
* @brief Reduced frequency divider.
*/
#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
-#define SPC5_CLK_RFD RFD_DIV4
+#define SPC5_CLK_RFD RFD_DIV2
#endif
/**
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index a879ae012..4ba03c260 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -49,8 +49,8 @@ #define SPC5_ESCIB_NUMBER 149
#define SPC5_HAS_ESCIC TRUE
-#define SPC5_ESCIB_HANDLER vector473
-#define SPC5_ESCIB_NUMBER 473
+#define SPC5_ESCIC_HANDLER vector473
+#define SPC5_ESCIC_NUMBER 473
/* SIU attributes.*/
#define SPC5_HAS_SIU TRUE
diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c index 15e851386..dcac0a593 100644 --- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c +++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c @@ -665,7 +665,7 @@ CH_IRQ_HANDLER(vector42) { */
CH_IRQ_HANDLER(vector210) {
edma_channel_t channel;
- uint32_t erl, esr = EDMA.ESR.R;
+ uint32_t erh, esr = EDMA.ESR.R;
CH_IRQ_PROLOGUE();
|