diff options
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/adc_lld.c | 11 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/adc_lld.h | 27 | ||||
| -rw-r--r-- | testhal/STM32/STM32F0xx/ADC/main.c | 4 |
3 files changed, 29 insertions, 13 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/adc_lld.c b/os/hal/ports/STM32/STM32F0xx/adc_lld.c index 1cc1bdcd1..753f4ac43 100644 --- a/os/hal/ports/STM32/STM32F0xx/adc_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/adc_lld.c @@ -245,13 +245,15 @@ void adc_lld_stop(ADCDriver *adcp) { * @notapi
*/
void adc_lld_start_conversion(ADCDriver *adcp) {
- uint32_t mode;
+ uint32_t mode, cfgr1;
const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
- mode = adcp->dmamode;
+ mode = adcp->dmamode;
+ cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN;
if (grpp->circular) {
- mode |= STM32_DMA_CR_CIRC;
+ mode |= STM32_DMA_CR_CIRC;
+ cfgr1 |= ADC_CFGR1_DMACFG;
if (adcp->depth > 1) {
/* If circular buffer depth > 1, then the half transfer interrupt
is enabled in order to allow streaming processing.*/
@@ -273,8 +275,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adc->CHSELR = grpp->chselr;
/* ADC configuration and start.*/
- adcp->adc->CFGR1 = grpp->cfgr1 | ADC_CFGR1_CONT | ADC_CFGR1_DMACFG |
- ADC_CFGR1_DMAEN;
+ adcp->adc->CFGR1 = cfgr1;
adcp->adc->CR |= ADC_CR_ADSTART;
}
diff --git a/os/hal/ports/STM32/STM32F0xx/adc_lld.h b/os/hal/ports/STM32/STM32F0xx/adc_lld.h index 4ccd50eb7..ec765df67 100644 --- a/os/hal/ports/STM32/STM32F0xx/adc_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/adc_lld.h @@ -46,20 +46,30 @@ /** @} */
/**
- * @name Resolution
+ * @name CFGR1 register configuration helpers
* @{
*/
-#define ADC_CFGR1_RES_12BIT (0 << 3)
-#define ADC_CFGR1_RES_10BIT (1 << 3)
-#define ADC_CFGR1_RES_8BIT (2 << 3)
-#define ADC_CFGR1_RES_6BIT (3 << 3)
+#define ADC_CFGR1_RES_12BIT (0 << 3)
+#define ADC_CFGR1_RES_10BIT (1 << 3)
+#define ADC_CFGR1_RES_8BIT (2 << 3)
+#define ADC_CFGR1_RES_6BIT (3 << 3)
+
+#define ADC_CFGR1_EXTSEL_MASK (15 << 6)
+#define ADC_CFGR1_EXTSEL_SRC(n) ((n) << 6)
+
+#define ADC_CFGR1_EXTEN_MASK (3 << 10)
+#define ADC_CFGR1_EXTEN_DISABLED (0 << 10)
+#define ADC_CFGR1_EXTEN_RISING (1 << 10)
+#define ADC_CFGR1_EXTEN_FALLING (2 << 10)
+#define ADC_CFGR1_EXTEN_BOTH (3 << 10)
/** @} */
/**
* @name Threashold register initializer
* @{
*/
-#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
+#define ADC_TR(low, high) (((uint32_t)(high) << 16) | \
+ (uint32_t)(low))
/** @} */
/*===========================================================================*/
@@ -210,6 +220,11 @@ typedef struct { /* End of the mandatory fields.*/
/**
* @brief ADC CFGR1 register initialization data.
+ * @note The bits DMAEN and DMACFG are enforced internally
+ * to the driver, keep them to zero.
+ * @note The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be
+ * specified in continuous more or if the buffer depth is
+ * greater than one.
*/
uint32_t cfgr1;
/**
diff --git a/testhal/STM32/STM32F0xx/ADC/main.c b/testhal/STM32/STM32F0xx/ADC/main.c index 86eb71780..ca0aecd07 100644 --- a/testhal/STM32/STM32F0xx/ADC/main.c +++ b/testhal/STM32/STM32F0xx/ADC/main.c @@ -57,7 +57,7 @@ static const ADCConversionGroup adcgrpcfg1 = { ADC_GRP1_NUM_CHANNELS,
NULL,
adcerrorcallback,
- ADC_CFGR1_RES_12BIT, /* CFGRR1 */
+ ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGRR1 */
ADC_TR(0, 0), /* TR */
ADC_SMPR_SMP_1P5, /* SMPR */
ADC_CHSELR_CHSEL10 /* CHSELR */
@@ -73,7 +73,7 @@ static const ADCConversionGroup adcgrpcfg2 = { ADC_GRP2_NUM_CHANNELS,
adccallback,
adcerrorcallback,
- ADC_CFGR1_RES_12BIT, /* CFGRR1 */
+ ADC_CFGR1_CONT | ADC_CFGR1_RES_12BIT, /* CFGRR1 */
ADC_TR(0, 0), /* TR */
ADC_SMPR_SMP_28P5, /* SMPR */
ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL11 |
|