diff options
| -rw-r--r-- | demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 4 | ||||
| -rw-r--r-- | demos/ARMCM3-STM32F103-GCC/Makefile | 4 | ||||
| -rw-r--r-- | docs/Doxyfile | 6 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/platform.dox | 2 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/LPC11xx/cmparams.h | 121 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/LPC11xx/port.mk | 10 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/LPC11xx/vectors.s | 212 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/STM32F103/cmparams.h | 6 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/STM32F103/port.mk | 14 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/chcore.c | 6 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/chcore.h | 15 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/chtypes.h | 4 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/cmsis/core_cm0.c | 455 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/cmsis/core_cm0.h | 984 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/crt0.s | 6 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/nvic.c | 6 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/nvic.h | 6 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/port.dox | 51 |
18 files changed, 63 insertions, 1849 deletions
diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index ced25453b..c9354ec9e 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
-include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
include $(CHIBIOS)/ext/fatfs/fatfs.mk
@@ -104,7 +104,7 @@ TCPPSRC = # List ASM source files here
ASMSRC = $(PORTASM) \
- $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s
+ $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 0c6ba31ba..347a6f7e0 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
-include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
@@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here
ASMSRC = $(PORTASM) \
- $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s
+ $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \
diff --git a/docs/Doxyfile b/docs/Doxyfile index e7d12a581..e67416a4c 100644 --- a/docs/Doxyfile +++ b/docs/Doxyfile @@ -600,9 +600,9 @@ INPUT = ../docs/src \ ../os/ports/GCC/ARM7 \ ../os/ports/GCC/ARM7/crt0.s \ ../os/ports/GCC/ARM7/chcoreasm.s \ - ../os/ports/GCC/ARMCMx \ - ../os/ports/GCC/ARMCMx/crt0.s \ - ../os/ports/GCC/ARMCMx\STM32F103 \ + ../os/ports/GCC/ARMCM3 \ + ../os/ports/GCC/ARMCM3/crt0.s \ + ../os/ports/GCC/ARMCM3\STM32F103 \ ../os/ports/GCC/PPC \ ../os/ports/GCC/PPC/crt0.s \ ../os/ports/GCC/MSP430 \ diff --git a/os/hal/platforms/STM32/platform.dox b/os/hal/platforms/STM32/platform.dox index 3afdf9b70..0eae343e2 100644 --- a/os/hal/platforms/STM32/platform.dox +++ b/os/hal/platforms/STM32/platform.dox @@ -30,7 +30,7 @@ * - A demo supporting the kernel test suite.
* - A demo that demonstrate the FatFs use with the MMC driver.
* .
- * @ingroup ARMCMx
+ * @ingroup ARMCM3
*/
/**
diff --git a/os/ports/GCC/ARMCM3/LPC11xx/cmparams.h b/os/ports/GCC/ARMCM3/LPC11xx/cmparams.h deleted file mode 100644 index 7b8834ac9..000000000 --- a/os/ports/GCC/ARMCM3/LPC11xx/cmparams.h +++ /dev/null @@ -1,121 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file ARMCMx/LPC111x/cmparams.h
- * @brief ARM Cortex-M0 LPC111x specific parameters.
- *
- * @defgroup ARMCMx_LPC111x LPC111x specific parameters
- * @ingroup ARMCMx
- * @details This file contains the Cortex-M0 specific parameters for the
- * LPC111x platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/*===========================================================================*/
-/* Constants parameters. */
-/*===========================================================================*/
-
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-
-/**
- * @brief Cortex core model.
- */
-#define CORTEX_MODEL CORTEX_M0
-
-/**
- * @brief Systick unit presence.
- */
-#define CORTEX_HAS_ST TRUE
-
-/**
- * @brief Memory Protection unit presence.
- */
-#define CORTEX_HAS_MPU FALSE
-
-/**
- * @brief Number of bits in priority masks.
- * @details The available number of priority levels is equal to
- * (1 << @p CORTEX_PRIORITY_BITS).
- */
-#define CORTEX_PRIORITY_BITS 2
-
-/**
- * @brief Priority to priority mask conversion macro.
- */
-#define CORTEX_PRIORITY(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
-
-/*===========================================================================*/
-/* Configurable parameters. */
-/*===========================================================================*/
-
-/**
- * @brief BASEPRI user level, 0 = disabled.
- */
-#ifndef CORTEX_BASEPRI_USER
-#define CORTEX_BASEPRI_USER CORTEX_PRIORITY(0)
-#endif
-
-/**
- * @brief BASEPRI level within kernel lock.
- * @details Priority levels higher than this one (lower values) are unaffected
- * by the OS activity and can be classified as fast interrupt sources,
- * see @ref interrupt_classes.
- */
-#ifndef CORTEX_BASEPRI_KERNEL
-#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY(1)
-#endif
-
-/**
- * @brief SVCALL handler priority.
- * @note This priority must always be one level above the @p BASEPRI_KERNEL
- * value.
- * @note It is recommended, but not mandatory, to leave this priority level
- * for this handler alone.
- */
-#ifndef CORTEX_PRIORITY_SVCALL
-#define CORTEX_PRIORITY_SVCALL CORTEX_PRIORITY(0)
-#endif
-
-/**
- * @brief SYSTICK handler priority.
- */
-#ifndef CORTEX_PRIORITY_SYSTICK
-#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(2)
-#endif
-
-/**
- * @brief PENDSV handler priority.
- * @note It is recommended to leave this priority level for this handler
- * alone.
- * @note This is a reserved handler and its priority must always be the
- * lowest priority in the system in order to be always executed last
- * in the interrupt servicing chain.
- */
-#ifndef CORTEX_PRIORITY_PENDSV
-#define CORTEX_PRIORITY_PENDSV CORTEX_PRIORITY(3)
-#endif
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/ports/GCC/ARMCM3/LPC11xx/port.mk b/os/ports/GCC/ARMCM3/LPC11xx/port.mk deleted file mode 100644 index 0d82384fb..000000000 --- a/os/ports/GCC/ARMCM3/LPC11xx/port.mk +++ /dev/null @@ -1,10 +0,0 @@ -# List of the ChibiOS/RT Cortex-M0 LPC11xx port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c
-# ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm0.c
-
-PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s
-
-PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC11xx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis
diff --git a/os/ports/GCC/ARMCM3/LPC11xx/vectors.s b/os/ports/GCC/ARMCM3/LPC11xx/vectors.s deleted file mode 100644 index 44ea654ce..000000000 --- a/os/ports/GCC/ARMCM3/LPC11xx/vectors.s +++ /dev/null @@ -1,212 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-.syntax unified
-.thumb
-
-.section vectors
-_vectors:
- .word __ram_end__
- .word ResetHandler
- .word NMIVector
- .word HardFaultVector
- .word MemManageVector
- .word BusFaultVector
- .word UsageFaultVector
- .word Vector1C
- .word Vector20
- .word Vector24
- .word Vector28
- .word SVCallVector
- .word DebugMonitorVector
- .word Vector34
- .word PendSVVector
- .word SysTickVector
- .word Vector40
- .word Vector44
- .word Vector48
- .word Vector4C
- .word Vector50
- .word Vector54
- .word Vector58
- .word Vector5C
- .word Vector60
- .word Vector64
- .word Vector68
- .word Vector6C
- .word Vector70
- .word Vector74
- .word Vector78
- .word Vector7C
- .word Vector80
- .word Vector84
- .word Vector88
- .word Vector8C
- .word Vector90
- .word Vector94
- .word Vector98
- .word Vector9C
- .word VectorA0
- .word VectorA4
- .word VectorA8
- .word VectorAC
- .word VectorB0
- .word VectorB4
- .word VectorB8
- .word VectorBC
-
-.weak NMIVector
-NMIVector:
-
-.weak HardFaultVector
-HardFaultVector:
-
-.weak MemManageVector
-MemManageVector:
-
-.weak BusFaultVector
-BusFaultVector:
-
-.weak UsageFaultVector
-UsageFaultVector:
-
-.weak Vector1C
-Vector1C:
-
-.weak Vector20
-Vector20:
-
-.weak Vector24
-Vector24:
-
-.weak Vector28
-Vector28:
-
-.weak SVCallVector
-SVCallVector:
-
-.weak DebugMonitorVector
-DebugMonitorVector:
-
-.weak Vector34
-Vector34:
-
-.weak PendSVVector
-PendSVVector:
-
-.weak SysTickVector
-SysTickVector:
-
-.weak Vector40
-Vector40:
-
-.weak Vector44
-Vector44:
-
-.weak Vector48
-Vector48:
-
-.weak Vector4C
-Vector4C:
-
-.weak Vector50
-Vector50:
-
-.weak Vector54
-Vector54:
-
-.weak Vector58
-Vector58:
-
-.weak Vector5C
-Vector5C:
-
-.weak Vector60
-Vector60:
-
-.weak Vector64
-Vector64:
-
-.weak Vector68
-Vector68:
-
-.weak Vector6C
-Vector6C:
-
-.weak Vector70
-Vector70:
-
-.weak Vector74
-Vector74:
-
-.weak Vector78
-Vector78:
-
-.weak Vector7C
-Vector7C:
-
-.weak Vector80
-Vector80:
-
-.weak Vector84
-Vector84:
-
-.weak Vector88
-Vector88:
-
-.weak Vector8C
-Vector8C:
-
-.weak Vector90
-Vector90:
-
-.weak Vector94
-Vector94:
-
-.weak Vector98
-Vector98:
-
-.weak Vector9C
-Vector9C:
-
-.weak VectorA0
-VectorA0:
-
-.weak VectorA4
-VectorA4:
-
-.weak VectorA8
-VectorA8:
-
-.weak VectorAC
-VectorAC:
-
-.weak VectorB0
-VectorB0:
-
-.weak VectorB4
-VectorB4:
-
-.weak VectorB8
-VectorB8:
-
-.weak VectorBC
-VectorBC:
-
-here: b here
diff --git a/os/ports/GCC/ARMCM3/STM32F103/cmparams.h b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h index 70c28e875..a3b481037 100644 --- a/os/ports/GCC/ARMCM3/STM32F103/cmparams.h +++ b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h @@ -18,11 +18,11 @@ */
/**
- * @file ARMCMx/STM32F103/cmparams.h
+ * @file ARMCM3/STM32F103/cmparams.h
* @brief ARM Cortex-M3 STM32F10x specific parameters.
*
- * @defgroup ARMCMx_STM32F10x STM32F10x specific parameters
- * @ingroup ARMCMx
+ * @defgroup ARMCM3_STM32F10x STM32F10x specific parameters
+ * @ingroup ARMCM3
* @details This file contains the Cortex-M3 specific parameters for the
* STM32F10x platform.
* @{
diff --git a/os/ports/GCC/ARMCM3/STM32F103/port.mk b/os/ports/GCC/ARMCM3/STM32F103/port.mk index 758d400c2..c656f7b10 100644 --- a/os/ports/GCC/ARMCM3/STM32F103/port.mk +++ b/os/ports/GCC/ARMCM3/STM32F103/port.mk @@ -1,10 +1,10 @@ # List of the ChibiOS/RT Cortex-M3 port files.
-PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/nvic.c \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis/core_cm3.c
+PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCM3/chcore.c \
+ ${CHIBIOS}/os/ports/GCC/ARMCM3/nvic.c \
+ ${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis/core_cm3.c
-PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCMx/crt0.s
+PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCM3/crt0.s
-PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCMx \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F103 \
- ${CHIBIOS}/os/ports/GCC/ARMCMx/cmsis
+PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCM3 \
+ ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103 \
+ ${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis
diff --git a/os/ports/GCC/ARMCM3/chcore.c b/os/ports/GCC/ARMCM3/chcore.c index 2ab8d4941..91598c0d6 100644 --- a/os/ports/GCC/ARMCM3/chcore.c +++ b/os/ports/GCC/ARMCM3/chcore.c @@ -18,10 +18,10 @@ */
/**
- * @file ARMCMx/chcore.c
- * @brief ARM Cortex-Mx architecture port code.
+ * @file ARMCM3/chcore.c
+ * @brief ARM Cortex-M3 architecture port code.
*
- * @addtogroup ARMCMx_CORE
+ * @addtogroup ARMCM3_CORE
* @{
*/
diff --git a/os/ports/GCC/ARMCM3/chcore.h b/os/ports/GCC/ARMCM3/chcore.h index 1927ccff0..1808e8b26 100644 --- a/os/ports/GCC/ARMCM3/chcore.h +++ b/os/ports/GCC/ARMCM3/chcore.h @@ -18,10 +18,10 @@ */
/**
- * @file ARMCMx/chcore.h
- * @brief ARM Cortex-Mx architecture port macros and structures.
+ * @file ARMCM3/chcore.h
+ * @brief ARM Cortex-M3 architecture port macros and structures.
*
- * @addtogroup ARMCMx_CORE
+ * @addtogroup ARMCM3_CORE
* @{
*/
@@ -44,7 +44,7 @@ */
#define CH_ARCHITECTURE_NAME "ARM"
-/* Inclusion of the Cortex-Mx implementation specific parameters.*/
+/* Inclusion of the Cortex-M3 implementation specific parameters.*/
#include "cmparams.h"
/* Generating model-dependent info.*/
@@ -58,11 +58,8 @@ * @brief Name of the architecture variant (optional).
*/
#define CH_CORE_VARIANT_NAME "Cortex-M3"
-#elif (CORTEX_MODEL == CORTEX_M0)
-#define CH_ARCHITECTURE_ARMCM0
-#define CH_CORE_VARIANT_NAME "Cortex-M0"
#else
-#error "unknown or unsupported Cortex-M model"
+#error "this ports only supports the Cortex-M3 architecture"
#endif
/**
@@ -120,7 +117,7 @@ struct intctx { #if !defined(__DOXYGEN__)
/**
* @brief Platform dependent part of the @p Thread structure.
- * @details In the Cortex-Mx port this structure just holds a pointer to the
+ * @details In the Cortex-M3 port this structure just holds a pointer to the
* @p intctx structure representing the stack pointer at the time
* of the context switch.
*/
diff --git a/os/ports/GCC/ARMCM3/chtypes.h b/os/ports/GCC/ARMCM3/chtypes.h index be89b04bf..f89ba4dc8 100644 --- a/os/ports/GCC/ARMCM3/chtypes.h +++ b/os/ports/GCC/ARMCM3/chtypes.h @@ -18,9 +18,9 @@ */
/**
- * @file ARMCMx/chtypes.h
+ * @file ARMCM3/chtypes.h
* @brief ARM Cortex-M3 architecture port system types.
- * @addtogroup ARMCMx_CORE
+ * @addtogroup ARMCM3_CORE
* @{
*/
diff --git a/os/ports/GCC/ARMCM3/cmsis/core_cm0.c b/os/ports/GCC/ARMCM3/cmsis/core_cm0.c deleted file mode 100644 index c08a7b6c6..000000000 --- a/os/ports/GCC/ARMCM3/cmsis/core_cm0.c +++ /dev/null @@ -1,455 +0,0 @@ -/**************************************************************************//**
- * @file core_cm0.c
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/os/ports/GCC/ARMCM3/cmsis/core_cm0.h b/os/ports/GCC/ARMCM3/cmsis/core_cm0.h deleted file mode 100644 index af27881d4..000000000 --- a/os/ports/GCC/ARMCM3/cmsis/core_cm0.h +++ /dev/null @@ -1,984 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/*
- * Parts of this files have been modified in ChibiOS/RT in order to fix
- * some code quality issues.
- */
-
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM0_CORE_H__
-#define __CM0_CORE_H__
-
-/** @addtogroup CMSIS_CM0_core_LintCinfiguration CMSIS CM0 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - not yet checked
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-
-/** @addtogroup CMSIS_CM0_core_definitions CM0 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define __CM0_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex core */
-
-#include <stdint.h> /* Include standard types */
-
-#if defined (__ICCARM__)
- #include <intrinsics.h> /* IAR Intrinsics */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM0_core_register CMSIS CM0 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM0_NVIC CMSIS CM0 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
- @{
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< (Offset: 0x000) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< (Offset: 0x080) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< (Offset: 0x100) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< (Offset: 0x180) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IPR[8]; /*!< (Offset: 0x3EC) Interrupt Priority Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM0_NVIC */
-
-
-/** @addtogroup CMSIS_CM0_SCB CMSIS CM0 SCB
- memory mapped structure for System Control Block (SCB)
- @{
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- uint32_t RESERVED0;
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x1C System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- uint32_t RESERVED2[2];
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFul << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM0_SCB */
-
-
-/** @addtogroup CMSIS_CM0_SysTick CMSIS CM0 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM0_SysTick */
-
-
-/** @addtogroup CMSIS_CM0_CoreDebug CMSIS CM0 Core Debug
- memory mapped structure for Core Debug Register
- @{
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos 24 /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk (1ul << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM0_CoreDebug */
-
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-/*@}*/ /* end of group CMSIS_CM0_core_register */
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-
-
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP(void) { __ASM volatile ("nop"); }
-static __INLINE void __WFI(void) { __ASM volatile ("wfi"); }
-static __INLINE void __WFE(void) { __ASM volatile ("wfe"); }
-static __INLINE void __SEV(void) { __ASM volatile ("sev"); }
-static __INLINE void __ISB(void) { __ASM volatile ("isb"); }
-static __INLINE void __DSB(void) { __ASM volatile ("dsb"); }
-static __INLINE void __DMB(void) { __ASM volatile ("dmb"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM0_Core_FunctionInterface CMSIS CM0 Core Function Interface
- Core Function Interface containing:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Reset Functions
-*/
-/*@{*/
-
-/* ########################## NVIC functions #################################### */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-
-/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM0_Core_FunctionInterface */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM0_core_definitions */
-
-#endif /* __CM0_CORE_H__ */
-
-/*lint -restore */
diff --git a/os/ports/GCC/ARMCM3/crt0.s b/os/ports/GCC/ARMCM3/crt0.s index 15aed34a6..8a6d9b9f0 100644 --- a/os/ports/GCC/ARMCM3/crt0.s +++ b/os/ports/GCC/ARMCM3/crt0.s @@ -18,9 +18,9 @@ */
/**
- * @file ARMCMx/crt0.s
- * @brief Generic ARM Cortex-Mx startup file for ChibiOS/RT.
- * @addtogroup ARMCMx_CORE
+ * @file ARMCM3/crt0.s
+ * @brief Generic ARM Cortex-M3 startup file for ChibiOS/RT.
+ * @addtogroup ARMCM3_CORE
* @{
*/
diff --git a/os/ports/GCC/ARMCM3/nvic.c b/os/ports/GCC/ARMCM3/nvic.c index 67551ec1d..44a80584a 100644 --- a/os/ports/GCC/ARMCM3/nvic.c +++ b/os/ports/GCC/ARMCM3/nvic.c @@ -18,9 +18,9 @@ */
/**
- * @file ARMCMx/nvic.c
- * @brief Cortex-Mx NVIC support code.
- * @addtogroup ARMCMx_NVIC
+ * @file ARMCM3/nvic.c
+ * @brief Cortex-M3 NVIC support code.
+ * @addtogroup ARMCM3_NVIC
* @{
*/
diff --git a/os/ports/GCC/ARMCM3/nvic.h b/os/ports/GCC/ARMCM3/nvic.h index 8a9950fcf..0538af307 100644 --- a/os/ports/GCC/ARMCM3/nvic.h +++ b/os/ports/GCC/ARMCM3/nvic.h @@ -18,9 +18,9 @@ */
/**
- * @file ARMCMx/nvic.h
- * @brief Cortex-Mx NVIC support macros and structures.
- * @addtogroup ARMCMx_NVIC
+ * @file ARMCM3/nvic.h
+ * @brief Cortex-M3 NVIC support macros and structures.
+ * @addtogroup ARMCM3_NVIC
* @{
*/
diff --git a/os/ports/GCC/ARMCM3/port.dox b/os/ports/GCC/ARMCM3/port.dox index 6ec32f56f..fd18ae82d 100644 --- a/os/ports/GCC/ARMCM3/port.dox +++ b/os/ports/GCC/ARMCM3/port.dox @@ -18,18 +18,17 @@ */
/**
- * @defgroup ARMCMx ARM Cortex-Mx
- * @details This port supports the ARM Cortex-Mx architectures, specifically
- * the Cortex-M0 and the Cortex-M3.
+ * @defgroup ARMCM3 ARM Cortex-M3
+ * @details This port supports the ARM Cortex-M3 architecture.
*
- * @section ARMCMx_STATES Mapping of the System States in the ARM Cortex-Mx port
+ * @section ARMCM3_STATES Mapping of the System States in the ARM Cortex-M3 port
* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
- * Cortex-Mx port:
+ * Cortex-M3 port:
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
* - <b>Normal</b>. This is the state the system has after executing
- * @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
+ * @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
* processor is running in thread-privileged mode.
* - <b>Suspended</b>. In this state the interrupt sources are not globally
@@ -54,15 +53,15 @@ * - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
* but it is not possible to switch to the I-Locked state because fast
* interrupts can preempt the kernel critical zone.
- * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered to be in this category.
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
* the maskable interrupt sources. The ARM state is whatever the processor
* was running when @p chSysHalt() was invoked.
* .
- * @section ARMCMx_NOTES The ARM Cortex-Mx port notes
- * The ARM Cortex-Mx port is organized as follow:
+ * @section ARMCM3_NOTES The ARM Cortex-M3 port notes
+ * The ARM Cortex-M3 port is organized as follow:
* - The @p main() function is invoked in thread-privileged mode.
* - Each thread has a private process stack, the system has a single main
* stack where all the interrupts and exceptions are processed.
@@ -83,9 +82,9 @@ */
/**
- * @defgroup ARMCMx_CONF Configuration Options
- * @brief ARM Cortex-Mx Configuration Options.
- * @details The ARMCMx port allows some architecture-specific configurations
+ * @defgroup ARMCM3_CONF Configuration Options
+ * @brief ARM Cortex-M3 Configuration Options.
+ * @details The ARMCM3 port allows some architecture-specific configurations
* settings that can be specified externally, as example on the compiler
* command line:
* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
@@ -97,32 +96,32 @@ * - @p CORTEX_BASEPRI_USER, this is the @p BASEPRI value for the user threads.
* The default value is @p 0 (disabled).<br>
* Usually there is no need to change this value, please refer to the
- * Cortex-Mx technical reference manual for a detailed description.
+ * Cortex-M3 technical reference manual for a detailed description.
* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
* code.<br>
* Code running at higher priority levels must not invoke any OS API.<br>
* Usually there is no need to change this value, please refer to the
- * Cortex-Mx technical reference manual for a detailed description.
+ * Cortex-M3 technical reference manual for a detailed description.
* - @p ENABLE_WFI_IDLE, if set to @p 1 enables the use of the @p <b>wfi</b>
* instruction from within the idle loop. This is defaulted to 0 because
* it can create problems with some debuggers. Setting this option to 1
* reduces the system power requirements.
* .
- * @ingroup ARMCMx
+ * @ingroup ARMCM3
*/
/**
- * @defgroup ARMCMx_CORE Core Port Implementation
- * @brief ARM Cortex-Mx specific port code, structures and macros.
+ * @defgroup ARMCM3_CORE Core Port Implementation
+ * @brief ARM Cortex-M3 specific port code, structures and macros.
*
- * @ingroup ARMCMx
+ * @ingroup ARMCM3
*/
/**
- * @defgroup ARMCMx_STARTUP Startup Support
- * @brief ARM Cortex-Mx startup code support.
+ * @defgroup ARMCM3_STARTUP Startup Support
+ * @brief ARM Cortex-M3 startup code support.
* @details ChibiOS/RT provides its own generic startup file for the ARM
- * Cortex-Mx port.
+ * Cortex-M3 port.
* Of course it is not mandatory to use it but care should be taken about the
* startup phase details.
*
@@ -158,13 +157,13 @@ * - @p _bss_start BSS start location.
* - @p _bss_end BSS end location +1.
* .
- * @ingroup ARMCMx
- * @file ARMCMx/crt0.s Startup code.
+ * @ingroup ARMCM3
+ * @file ARMCM3/crt0.s Startup code.
*/
/**
- * @defgroup ARMCMx_NVIC NVIC Support
- * @brief ARM Cortex-Mx NVIC support.
+ * @defgroup ARMCM3_NVIC NVIC Support
+ * @brief ARM Cortex-M3 NVIC support.
*
- * @ingroup ARMCMx
+ * @ingroup ARMCM3
*/
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