diff options
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 23 | ||||
| -rw-r--r-- | readme.txt | 2 |
2 files changed, 24 insertions, 1 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index 4eea068c9..c4916b8af 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -48,7 +48,7 @@ uint32_t SystemCoreClock = STM32_HCLK; /**
* @brief Initializes the backup domain.
- * @note WARNING! Changing clock source impossible without resetting
+ * @note WARNING! Changing RTC clock source impossible without resetting
* of the whole BKP domain.
*/
static void hal_lld_backup_domain_init(void) {
@@ -60,6 +60,27 @@ static void hal_lld_backup_domain_init(void) { RCC->BDCR = 0;
}
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+#if STM32_MSIPLL_ENABLED
+ /* MSI PLL activation depends on LSE. Reactivating and checking for
+ MSI stability.*/
+ RCC->CR |= RCC_CR_MSIPLLEN;
+ while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+ ; /* Wait until MSI is stable. */
+#endif
+
#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
diff --git a/readme.txt b/readme.txt index bea561828..e7570882c 100644 --- a/readme.txt +++ b/readme.txt @@ -120,6 +120,8 @@ - RT: Merged RT4.
- NIL: Merged NIL2.
- NIL: Added STM32F7 demo.
+- HAL: Fixed wrong backup domain reset in STM32L4xx\hal_lld (bug #763)
+ (backported to 16.1.6).
- HAL: Fixed wrong PWR configurations in STM32L4xx\hal_lld (bug #761)
(backported to 16.1.5).
- HAL: Fixed wrong comment in STM32L4xx\hal_lld (bug #760)
|