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-rw-r--r--os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c99
-rw-r--r--os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h4
-rw-r--r--os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c123
-rw-r--r--os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h93
4 files changed, 278 insertions, 41 deletions
diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
index 6f0d5447b..cbb7e7ef8 100644
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
+++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
@@ -82,7 +82,8 @@ CH_IRQ_HANDLER(vector11) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 0;
- channels[0]->dma_func(0, channels[0]->dma_param);
+ if (channels[0] != NULL)
+ channels[0]->dma_func(0, channels[0]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -100,7 +101,8 @@ CH_IRQ_HANDLER(vector12) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 1;
- channels[1]->dma_func(1, channels[1]->dma_param);
+ if (channels[1] != NULL)
+ channels[1]->dma_func(1, channels[1]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -118,7 +120,8 @@ CH_IRQ_HANDLER(vector13) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 2;
- channels[2]->dma_func(2, channels[2]->dma_param);
+ if (channels[2] != NULL)
+ channels[2]->dma_func(2, channels[2]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -136,7 +139,8 @@ CH_IRQ_HANDLER(vector14) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 3;
- channels[3]->dma_func(3, channels[3]->dma_param);
+ if (channels[3] != NULL)
+ channels[3]->dma_func(3, channels[3]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -154,7 +158,8 @@ CH_IRQ_HANDLER(vector15) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 4;
- channels[4]->dma_func(4, channels[4]->dma_param);
+ if (channels[4] != NULL)
+ channels[4]->dma_func(4, channels[4]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -172,7 +177,8 @@ CH_IRQ_HANDLER(vector16) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 5;
- channels[5]->dma_func(5, channels[5]->dma_param);
+ if (channels[5] != NULL)
+ channels[5]->dma_func(5, channels[5]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -190,7 +196,8 @@ CH_IRQ_HANDLER(vector17) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 6;
- channels[6]->dma_func(6, channels[6]->dma_param);
+ if (channels[6] != NULL)
+ channels[6]->dma_func(6, channels[6]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -208,7 +215,8 @@ CH_IRQ_HANDLER(vector18) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 7;
- channels[7]->dma_func(7, channels[7]->dma_param);
+ if (channels[7] != NULL)
+ channels[7]->dma_func(7, channels[7]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -226,7 +234,8 @@ CH_IRQ_HANDLER(vector19) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 8;
- channels[8]->dma_func(8, channels[8]->dma_param);
+ if (channels[8] != NULL)
+ channels[8]->dma_func(8, channels[8]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -244,7 +253,8 @@ CH_IRQ_HANDLER(vector20) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 9;
- channels[9]->dma_func(9, channels[9]->dma_param);
+ if (channels[9] != NULL)
+ channels[9]->dma_func(9, channels[9]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -262,7 +272,8 @@ CH_IRQ_HANDLER(vector21) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 10;
- channels[10]->dma_func(10, channels[10]->dma_param);
+ if (channels[10] != NULL)
+ channels[10]->dma_func(10, channels[10]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -280,7 +291,8 @@ CH_IRQ_HANDLER(vector22) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 11;
- channels[11]->dma_func(11, channels[11]->dma_param);
+ if (channels[11] != NULL)
+ channels[11]->dma_func(11, channels[11]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -298,7 +310,8 @@ CH_IRQ_HANDLER(vector23) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 12;
- channels[12]->dma_func(12, channels[12]->dma_param);
+ if (channels[12] != NULL)
+ channels[12]->dma_func(12, channels[12]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -316,7 +329,8 @@ CH_IRQ_HANDLER(vector24) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 13;
- channels[13]->dma_func(13, channels[13]->dma_param);
+ if (channels[13] != NULL)
+ channels[13]->dma_func(13, channels[13]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -334,7 +348,8 @@ CH_IRQ_HANDLER(vector25) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 14;
- channels[14]->dma_func(14, channels[14]->dma_param);
+ if (channels[14] != NULL)
+ channels[14]->dma_func(14, channels[14]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -352,7 +367,8 @@ CH_IRQ_HANDLER(vector26) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 15;
- channels[15]->dma_func(15, channels[15]->dma_param);
+ if (channels[15] != NULL)
+ channels[15]->dma_func(15, channels[15]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -371,7 +387,8 @@ CH_IRQ_HANDLER(vector27) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 16;
- channels[16]->dma_func(16, channels[16]->dma_param);
+ if (channels[16] != NULL)
+ channels[16]->dma_func(16, channels[16]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -389,7 +406,8 @@ CH_IRQ_HANDLER(vector28) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 17;
- channels[17]->dma_func(17, channels[17]->dma_param);
+ if (channels[17] != NULL)
+ channels[17]->dma_func(17, channels[17]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -407,7 +425,8 @@ CH_IRQ_HANDLER(vector29) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 18;
- channels[18]->dma_func(18, channels[18]->dma_param);
+ if (channels[18] != NULL)
+ channels[18]->dma_func(18, channels[18]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -425,7 +444,8 @@ CH_IRQ_HANDLER(vector30) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 19;
- channels[19]->dma_func(19, channels[19]->dma_param);
+ if (channels[19] != NULL)
+ channels[19]->dma_func(19, channels[19]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -443,7 +463,8 @@ CH_IRQ_HANDLER(vector31) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 20;
- channels[20]->dma_func(20, channels[20]->dma_param);
+ if (channels[20] != NULL)
+ channels[20]->dma_func(20, channels[20]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -461,7 +482,8 @@ CH_IRQ_HANDLER(vector32) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 21;
- channels[21]->dma_func(21, channels[21]->dma_param);
+ if (channels[21] != NULL)
+ channels[21]->dma_func(21, channels[21]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -479,7 +501,8 @@ CH_IRQ_HANDLER(vector33) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 22;
- channels[22]->dma_func(22, channels[22]->dma_param);
+ if (channels[22] != NULL)
+ channels[22]->dma_func(22, channels[22]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -497,7 +520,8 @@ CH_IRQ_HANDLER(vector34) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 23;
- channels[23]->dma_func(23, channels[23]->dma_param);
+ if (channels[23] != NULL)
+ channels[23]->dma_func(23, channels[23]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -515,7 +539,8 @@ CH_IRQ_HANDLER(vector35) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 24;
- channels[24]->dma_func(24, channels[24]->dma_param);
+ if (channels[24] != NULL)
+ channels[24]->dma_func(24, channels[24]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -533,7 +558,8 @@ CH_IRQ_HANDLER(vector36) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 25;
- channels[25]->dma_func(25, channels[25]->dma_param);
+ if (channels[25] != NULL)
+ channels[25]->dma_func(25, channels[25]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -551,7 +577,8 @@ CH_IRQ_HANDLER(vector37) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 26;
- channels[26]->dma_func(26, channels[26]->dma_param);
+ if (channels[26] != NULL)
+ channels[26]->dma_func(26, channels[26]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -569,7 +596,8 @@ CH_IRQ_HANDLER(vector38) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 27;
- channels[27]->dma_func(27, channels[27]->dma_param);
+ if (channels[27] != NULL)
+ channels[27]->dma_func(27, channels[27]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -587,7 +615,8 @@ CH_IRQ_HANDLER(vector39) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 28;
- channels[28]->dma_func(28, channels[28]->dma_param);
+ if (channels[28] != NULL)
+ channels[28]->dma_func(28, channels[28]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -605,7 +634,8 @@ CH_IRQ_HANDLER(vector40) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 29;
- channels[29]->dma_func(29, channels[29]->dma_param);
+ if (channels[29] != NULL)
+ channels[29]->dma_func(29, channels[29]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -623,7 +653,8 @@ CH_IRQ_HANDLER(vector41) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 30;
- channels[30]->dma_func(30, channels[30]->dma_param);
+ if (channels[30] != NULL)
+ channels[30]->dma_func(30, channels[30]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -641,7 +672,8 @@ CH_IRQ_HANDLER(vector42) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 31;
- channels[31]->dma_func(31, channels[31]->dma_param);
+ if (channels[31] != NULL)
+ channels[31]->dma_func(31, channels[31]->dma_param);
CH_IRQ_EPILOGUE();
}
@@ -680,7 +712,8 @@ void edmaInit(void) {
edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
edma_channel_t channel;
- chDbgCheck((ccfg != NULL) && ((ccfg->dma_priority & 15) < 16) &&
+ chDbgCheck((ccfg != NULL) && ((ccfg->dma_prio & 15) < 16) &&
+ (ccfg->dma_irq_prio < 16) &&
(ccfg->dma_func != NULL) && (ccfg->dma_error_func != NULL),
"edmaChannelAllocate");
diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
index 3812254aa..1ea965551 100644
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
+++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
@@ -94,8 +94,10 @@ typedef void (*edma_callback_t)(edma_channel_t channel, void *p);
typedef struct {
uint8_t dma_periph; /**< @brief Peripheral to be
associated to the channel. */
- uint8_t dma_priority; /**< @brief Priority register value
+ uint8_t dma_prio; /**< @brief Priority register value
for this channel. */
+ uint8_t dma_irq_prio; /**< @brief IRQ priority level for
+ this channel. */
edma_callback_t dma_func; /**< @brief Channel callback. */
edma_callback_t dma_error_func; /**< @brief Channel error callback. */
void *dma_param; /**< @brief Channel callback param. */
diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
index a677a25e2..a9e8a5e26 100644
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
+++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
@@ -25,6 +25,11 @@
#if HAL_USE_ADC || defined(__DOXYGEN__)
+/* Some forward declarations.*/
+static void adc_serve_rfifo_irq(edma_channel_t channel, void *p);
+static void adc_serve_rfifo_error_irq(edma_channel_t channel, void *p);
+static void adc_serve_cfifo_error_irq(edma_channel_t channel, void *p);
+
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
@@ -87,6 +92,42 @@ ADCDriver ADCD6;
static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR;
+#if SPC5_ADC_USE_ADC0_Q0 || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for EQADC CFIFO0.
+ */
+static const edma_channel_config_t adc_cfifo0_dma_config = {
+ 0, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC0_FIFO0_DMA_IRQ_PRIO,
+ NULL, adc_serve_cfifo_error_irq, NULL
+};
+
+/**
+ * @brief DMA configuration for EQADC RFIFO0.
+ */
+static const edma_channel_config_t adc_rfifo0_dma_config = {
+ 1, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC0_FIFO0_DMA_IRQ_PRIO,
+ adc_serve_rfifo_irq, adc_serve_rfifo_error_irq, NULL
+};
+#endif /* SPC5_ADC_USE_ADC0_Q3 */
+
+#if SPC5_ADC_USE_ADC1_Q3 || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for EQADC CFIFO3.
+ */
+static const edma_channel_config_t adc_cfifo3_dma_config = {
+ 0, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC0_FIFO3_DMA_IRQ_PRIO,
+ NULL, adc_serve_cfifo_error_irq, NULL
+};
+
+/**
+ * @brief DMA configuration for EQADC RFIFO3.
+ */
+static const edma_channel_config_t adc_rfifo3_dma_config = {
+ 1, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC0_FIFO3_DMA_IRQ_PRIO,
+ adc_serve_rfifo_irq, adc_serve_rfifo_error_irq, NULL
+};
+#endif /* SPC5_ADC_USE_ADC1_Q3 */
+
/*===========================================================================*/
/* Driver local functions and macros. */
/*===========================================================================*/
@@ -267,6 +308,48 @@ static void adc_setup_resistors(uint32_t adc) {
adc_write_register(adc, ADC_REG_PUDCR(i), pudcrs[i]);
}
+/**
+ * @brief Shared ISR for RFIFO DMA events.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ *
+ * @notapi
+ */
+static void adc_serve_rfifo_irq(edma_channel_t channel, void *p) {
+
+ (void)channel;
+ (void)p;
+}
+
+/**
+ * @brief Shared ISR for RFIFO DMA error events.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ *
+ * @notapi
+ */
+static void adc_serve_rfifo_error_irq(edma_channel_t channel, void *p) {
+
+ (void)channel;
+ (void)p;
+}
+
+/**
+ * @brief Shared ISR for CFIFO DMA error events.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ *
+ * @notapi
+ */
+static void adc_serve_cfifo_error_irq(edma_channel_t channel, void *p) {
+
+ (void)channel;
+ (void)p;
+}
+
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@@ -282,11 +365,20 @@ static void adc_setup_resistors(uint32_t adc) {
*/
void adc_lld_init(void) {
-#if SPC5_ADC_USE_EQADC_Q0
+#if SPC5_ADC_USE_ADC0_Q0
/* Driver initialization.*/
adcObjectInit(&ADCD1);
+ ADCD1.cfifo_channel = EDMA_ERROR;
+ ADCD1.rfifo_channel = EDMA_ERROR;
#endif /* SPC5_ADC_USE_EQADC_Q0 */
+#if SPC5_ADC_USE_ADC1_Q3
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.cfifo_channel = EDMA_ERROR;
+ ADCD1.rfifo_channel = EDMA_ERROR;
+#endif /* SPC5_ADC_USE_ADC1_Q3 */
+
/* Temporarily enables CFIFO0 for calibration and initialization.*/
cfifo_enable(ADC_FIFO_0, EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWCS, 0);
adc_enable();
@@ -323,12 +415,24 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) {
/* Enables the peripheral.*/
-#if SPC5_ADC_USE_ADC0
+#if SPC5_ADC_USE_ADC0_Q0
if (&ADCD1 == adcp) {
-
+ adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo0_dma_config);
+ adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo0_dma_config);
}
#endif /* SPC5_ADC_USE_EQADC_Q0 */
+#if SPC5_ADC_USE_ADC1_Q3
+ if (&ADCD4 == adcp) {
+ adcp->cfifo_channel = edmaChannelAllocate(&adc_cfifo3_dma_config);
+ adcp->rfifo_channel = edmaChannelAllocate(&adc_rfifo3_dma_config);
+ }
+#endif /* SPC5_ADC_USE_ADC1_Q3 */
}
+
+ chDbgAssert((adcp->cfifo_channel != EDMA_ERROR) &&
+ (adcp->rfifo_channel != EDMA_ERROR),
+ "adc_lld_start(), #1", "channel cannot be allocated");
+
/* Configures the peripheral.*/
}
@@ -345,12 +449,19 @@ void adc_lld_stop(ADCDriver *adcp) {
if (adcp->state == ADC_READY) {
/* Resets the peripheral.*/
+ /* Releases the allocated EDMA channels.*/
+ edmaChannelRelease(adcp->cfifo_channel);
+ edmaChannelRelease(adcp->rfifo_channel);
+
/* Disables the peripheral.*/
-#if SPC5_ADC_USE_ADC0
+#if SPC5_ADC_USE_ADC0_Q0
if (&ADCD1 == adcp) {
-
}
-#endif /* SPC5_ADC_USE_EQADC_Q0 */
+#endif /* SPC5_ADC_USE_ADC0_Q0 */
+#if SPC5_ADC_USE_ADC1_Q3
+ if (&ADCD1 == adcp) {
+ }
+#endif /* SPC5_ADC_USE_ADC1_Q3 */
}
}
diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
index 6b1fd4b1c..395f7f871 100644
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
+++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
@@ -255,7 +255,90 @@
#endif
/**
- *
+ * @brief EQADC CFIFO0 and RFIFO0 DMA priority.
+ */
+#if !defined(SPC5_ADC_FIFO0_DMA_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC_FIFO0_DMA_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO1 and RFIFO1 DMA priority.
+ */
+#if !defined(SPC5_ADC_FIFO1_DMA_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC_FIFO1_DMA_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO2 and RFIFO2 DMA priority.
+ */
+#if !defined(SPC5_ADC_FIFO2_DMA_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC_FIFO2_DMA_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO3 and RFIFO3 DMA priority.
+ */
+#if !defined(SPC5_ADC_FIFO3_DMA_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC_FIFO3_DMA_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO4 and RFIFO4 DMA priority.
+ */
+#if !defined(SPC5_ADC_FIFO4_DMA_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC_FIFO4_DMA_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO5 and RFIFO5 DMA priority.
+ */
+#if !defined(SPC5_ADC_FIFO5_DMA_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC_FIFO5_DMA_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO0 and RFIFO0 DMA IRQ priority.
+ */
+#if !defined(SPC5_ADC0_FIFO0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC0_FIFO0_DMA_IRQ_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO1 and RFIFO1 DMA IRQ priority.
+ */
+#if !defined(SPC5_ADC0_FIFO1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC0_FIFO1_DMA_IRQ_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO2 and RFIFO2 DMA IRQ priority.
+ */
+#if !defined(SPC5_ADC0_FIFO2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC0_FIFO2_DMA_IRQ_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO3 and RFIFO3 DMA IRQ priority.
+ */
+#if !defined(SPC5_ADC0_FIFO3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC0_FIFO3_DMA_IRQ_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO4 and RFIFO4 DMA IRQ priority.
+ */
+#if !defined(SPC5_ADC0_FIFO4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC0_FIFO4_DMA_IRQ_PRIO 12
+#endif
+
+/**
+ * @brief EQADC CFIFO5 and RFIFO5 DMA IRQ priority.
+ */
+#if !defined(SPC5_ADC0_FIFO5_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_ADC0_FIFO5_DMA_IRQ_PRIO 12
+#endif
+
+/**
* @brief EQADC clock prescaler value.
*/
#if !defined(SPC5_ADC_CR_CLK_PS) || defined(__DOXYGEN__)
@@ -447,6 +530,14 @@ struct ADCDriver {
ADC_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
+ /**
+ * @brief EDMA channel used for the CFIFO.
+ */
+ edma_channel_t cfifo_channel;
+ /**
+ * @brief EDMA channel used for the RFIFO.
+ */
+ edma_channel_t rfifo_channel;
};
/*===========================================================================*/
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 00:39:27 +0000