diff options
| -rw-r--r-- | os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c | 21 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h | 2 |
2 files changed, 21 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c index 4c8ee0f2d..f3a889b57 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c @@ -291,7 +291,6 @@ void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp, dmaStreamEnable(qspip->dma);
}
-
#if (QSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)
/**
* @brief Maps in memory space a QSPI flash device.
@@ -309,6 +308,19 @@ void qspi_lld_map_flash(QSPIDriver *qspip, const qspi_command_t *cmdp,
uint8_t **addrp) {
+ /* Disabling the DMA request while in memory mapped mode.*/
+ qspip->qspi->CR &= ~QUADSPI_CR_DMAEN;
+
+ /* Starting memory mapped mode using the passed parameters.*/
+ qspip->qspi->DLR = 0;
+ qspip->qspi->ABR = 0;
+ qspip->qspi->AR = 0;
+ qspip->qspi->CCR = cmdp->cfg | QUADSPI_CCR_FMODE_1 | QUADSPI_CCR_FMODE_0;
+
+ /* Mapped flash absolute base address.*/
+ if (addrp != NULL) {
+ *addrp = (uint8_t *)0x90000000;
+ }
}
/**
@@ -322,6 +334,13 @@ void qspi_lld_map_flash(QSPIDriver *qspip, */
void qspi_lld_unmap_flash(QSPIDriver *qspip) {
+ /* Aborting memory mapped mode.*/
+ qspip->qspi->CR |= QUADSPI_CR_ABORT;
+ while ((qspip->qspi->CR & QUADSPI_CR_ABORT) != 0U) {
+ }
+
+ /* Re-enabling DMA request, we are going back to indirect mode.*/
+ qspip->qspi->CR |= QUADSPI_CR_DMAEN;
}
#endif /* QSPI_SUPPORTS_MEMMAP == TRUE */
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h index 5f8cd86af..8e3acfa57 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h @@ -35,7 +35,7 @@ * @name QSPI capabilities
* @{
*/
-#define QSPI_SUPPORTS_MEMMAP FALSE
+#define QSPI_SUPPORTS_MEMMAP TRUE
/** @} */
/**
|