diff options
| -rw-r--r-- | os/hal/include/hal_can.h | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F37x/stm32_rcc.h | 21 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/stm32_rcc.h | 8 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 4 |
4 files changed, 25 insertions, 10 deletions
diff --git a/os/hal/include/hal_can.h b/os/hal/include/hal_can.h index d32e91e93..3a12c09d1 100644 --- a/os/hal/include/hal_can.h +++ b/os/hal/include/hal_can.h @@ -162,7 +162,7 @@ typedef enum { */
#define _can_wakeup_isr(canp) { \
osalSysLockFromISR(); \
- osalEventBroadcastFlagsI(&(canp)->wakeup_event, 0U); \
+ osalEventBroadcastFlagsI(&(canp)->wakeup_event, 0U); \
osalSysUnlockFromISR(); \
}
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h index 600b70728..6cf48250f 100644 --- a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h @@ -975,6 +975,27 @@ #define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
/** @} */
+/**
+ * @name CRC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRC peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
+
+/**
+ * @brief Disables the CRC peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
+/** @} */
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h index 1c1d4fc19..cf043bfa1 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h @@ -796,11 +796,9 @@ /**
* @brief Disables the HRTIM1 peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableHRTIM1(lp) rccDisableAPB2(RCC_APB2ENR_HRTIM1EN, lp)
+#define rccDisableHRTIM1(lp) rccDisableAPB2(RCC_APB2ENR_HRTIM1EN)
/**
* @brief Resets the HRTIM1 peripheral.
@@ -998,11 +996,9 @@ /**
* @brief Disables the CRC peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN)
+#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN)
/** @} */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 44876d18f..6b110b146 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -1527,11 +1527,9 @@ /**
* @brief Disables the CRC peripheral clock.
*
- * @param[in] lp low power enable flag
- *
* @api
*/
-#define rccDisableCRC(lp) rccDisableAHB1(RCC_AHB1ENR_CRCEN)
+#define rccDisableCRC() rccDisableAHB1(RCC_AHB1ENR_CRCEN)
/**
* @brief Resets the CRC peripheral.
|