diff options
24 files changed, 250 insertions, 34 deletions
diff --git a/docs/Doxyfile b/docs/Doxyfile index 91e033402..d1dd65d2a 100644 --- a/docs/Doxyfile +++ b/docs/Doxyfile @@ -626,6 +626,8 @@ INPUT = ../docs/src \ ../os/ports/GCC/PPC \ ../os/ports/GCC/AVR \ ../os/ports/GCC/MSP430 \ + ../os/ports/IAR/ARMCMx \ + ../os/ports/IAR/ARMCMx/STM32 \ ../os/ports/cosmic/STM8 \ ../os/ports/RC/STM8 \ ../os/hal \ diff --git a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h index b3dfd2949..89c685f7f 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/LPC11xx/cmparams.h @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/LPC11xx/cmparams.h
+ * @file GCC/ARMCMx/LPC11xx/cmparams.h
* @brief ARM Cortex-M0 LPC11xx Specific Parameters.
*
* @defgroup ARMCMx_LPC11xx LPC11xx Specific Parameters
diff --git a/os/ports/GCC/ARMCMx/LPC11xx/vectors.c b/os/ports/GCC/ARMCMx/LPC11xx/vectors.c index 86672a338..34b220807 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/vectors.c +++ b/os/ports/GCC/ARMCMx/LPC11xx/vectors.c @@ -18,7 +18,7 @@ */
/**
- * @file LPC11xx/vectors.c
+ * @file GCC/ARMCMx/LPC11xx/vectors.c
* @brief Interrupt vectors for the LPC11xx family.
*
* @defgroup ARMCMx_LPC11xx_VECTORS LPC11xx Interrupt Vectors
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h index 1822647d3..fb08f181f 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h +++ b/os/ports/GCC/ARMCMx/LPC13xx/cmparams.h @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/LPC13xx/cmparams.h
+ * @file GCC/ARMCMx/LPC13xx/cmparams.h
* @brief ARM Cortex-M3 LPC13xx Specific Parameters.
*
* @defgroup ARMCMx_LPC13xx LPC13xx Specific Parameters
diff --git a/os/ports/GCC/ARMCMx/LPC13xx/vectors.c b/os/ports/GCC/ARMCMx/LPC13xx/vectors.c index 2d62da81f..4602f3c1b 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/vectors.c +++ b/os/ports/GCC/ARMCMx/LPC13xx/vectors.c @@ -18,7 +18,7 @@ */
/**
- * @file LPC13xx/vectors.c
+ * @file GCC/ARMCMx/LPC13xx/vectors.c
* @brief Interrupt vectors for the LPC13xx family.
*
* @defgroup ARMCMx_LPC13xx_VECTORS LPC13xx Interrupt Vectors
diff --git a/os/ports/GCC/ARMCMx/STM32/cmparams.h b/os/ports/GCC/ARMCMx/STM32/cmparams.h index de07b7c67..fe9f219e5 100644 --- a/os/ports/GCC/ARMCMx/STM32/cmparams.h +++ b/os/ports/GCC/ARMCMx/STM32/cmparams.h @@ -18,7 +18,7 @@ */
/**
- * @file STM32/cmparams.h
+ * @file GCC/ARMCMx/STM32/cmparams.h
* @brief ARM Cortex-M3 parameters for the STM32.
*
* @defgroup ARMCMx_STM32 STM32 Specific Parameters
diff --git a/os/ports/GCC/ARMCMx/STM32/vectors.c b/os/ports/GCC/ARMCMx/STM32/vectors.c index d2306add0..1ecbae7e4 100644 --- a/os/ports/GCC/ARMCMx/STM32/vectors.c +++ b/os/ports/GCC/ARMCMx/STM32/vectors.c @@ -18,7 +18,7 @@ */
/**
- * @file STM32/vectors.c
+ * @file GCC/ARMCMx/STM32/vectors.c
* @brief Interrupt vectors for the STM32 family.
*
* @defgroup ARMCMx_STM32_VECTORS STM32 Interrupt Vectors
diff --git a/os/ports/GCC/ARMCMx/chcore.c b/os/ports/GCC/ARMCMx/chcore.c index 24a9d7f7a..4bb0436cd 100644 --- a/os/ports/GCC/ARMCMx/chcore.c +++ b/os/ports/GCC/ARMCMx/chcore.c @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/chcore.c
+ * @file GCC/ARMCMx/chcore.c
* @brief ARM Cortex-Mx port code.
*
* @addtogroup ARMCMx_CORE
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 41d433508..3fe046a95 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/chcore.h
+ * @file GCC/ARMCMx/chcore.h
* @brief ARM Cortex-Mx port macros and structures.
*
* @addtogroup ARMCMx_CORE
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c index c8ee32387..246426f2c 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.c +++ b/os/ports/GCC/ARMCMx/chcore_v6m.c @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/chcore_v6m.c
+ * @file GCC/ARMCMx/chcore_v6m.c
* @brief ARMv6-M architecture port code.
*
* @addtogroup ARMCMx_V6M_CORE
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index 70447712c..5ca439365 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/chcore_v6m.h
+ * @file GCC/ARMCMx/chcore_v6m.h
* @brief ARMv6-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V6M_CORE
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index 527161ebf..6e3732a8d 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/chcore_v7m.c
+ * @file GCC/ARMCMx/chcore_v7m.c
* @brief ARMv7-M architecture port code.
*
* @addtogroup ARMCMx_V7M_CORE
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 32b5a1361..2a4838669 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/chcore_v7m.h
+ * @file GCC/ARMCMx/chcore_v7m.h
* @brief ARMv7-M architecture port macros and structures.
*
* @addtogroup ARMCMx_V7M_CORE
diff --git a/os/ports/GCC/ARMCMx/chtypes.h b/os/ports/GCC/ARMCMx/chtypes.h index e5e68b92f..f4bf93c1c 100644 --- a/os/ports/GCC/ARMCMx/chtypes.h +++ b/os/ports/GCC/ARMCMx/chtypes.h @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/chtypes.h
+ * @file GCC/ARMCMx/chtypes.h
* @brief ARM Cortex-Mx port system types.
*
* @addtogroup ARMCMx_CORE
diff --git a/os/ports/GCC/ARMCMx/crt0_v6m.s b/os/ports/GCC/ARMCMx/crt0_v6m.s index fd7e4fca4..82dc066fb 100644 --- a/os/ports/GCC/ARMCMx/crt0_v6m.s +++ b/os/ports/GCC/ARMCMx/crt0_v6m.s @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/crt0_v6m.s
+ * @file GCC/ARMCMx/crt0_v6m.s
* @brief Generic ARMv6-M (Cortex-M0/M1) startup file for ChibiOS/RT.
*
* @addtogroup ARMCMx_CORE
diff --git a/os/ports/GCC/ARMCMx/crt0_v7m.s b/os/ports/GCC/ARMCMx/crt0_v7m.s index fb0d4a137..1c76975c6 100644 --- a/os/ports/GCC/ARMCMx/crt0_v7m.s +++ b/os/ports/GCC/ARMCMx/crt0_v7m.s @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/crt0_v7m.s
+ * @file GCC/ARMCMx/crt0_v7m.s
* @brief Generic ARMv7-M (Cortex-M3/M4) startup file for ChibiOS/RT.
*
* @addtogroup ARMCMx_CORE
diff --git a/os/ports/GCC/ARMCMx/nvic.c b/os/ports/GCC/ARMCMx/nvic.c index 5b0dd9782..fb470c2e1 100644 --- a/os/ports/GCC/ARMCMx/nvic.c +++ b/os/ports/GCC/ARMCMx/nvic.c @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/nvic.c
+ * @file GCC/ARMCMx/nvic.c
* @brief Cortex-Mx NVIC support code.
*
* @addtogroup ARMCMx_NVIC
diff --git a/os/ports/GCC/ARMCMx/nvic.h b/os/ports/GCC/ARMCMx/nvic.h index 196b78fbd..bd5d0f31b 100644 --- a/os/ports/GCC/ARMCMx/nvic.h +++ b/os/ports/GCC/ARMCMx/nvic.h @@ -18,7 +18,7 @@ */
/**
- * @file ARMCMx/nvic.h
+ * @file GCC/ARMCMx/nvic.h
* @brief Cortex-Mx NVIC support macros and structures.
*
* @addtogroup ARMCMx_NVIC
diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox index 9fff65dd0..32b736434 100644 --- a/os/ports/GCC/ARMCMx/port.dox +++ b/os/ports/GCC/ARMCMx/port.dox @@ -187,18 +187,14 @@ * -# The two stacks are initialized by assigning them the sizes defined in the
* linker script (usually named @p ch.ld). Stack areas are allocated from
* the highest RAM location downward.
- * -# An early initialization routine @p hwinit0 is invoked, if the symbol is
- * not defined then an empty default routine is executed (weak symbol).
- * -# DATA and BSS segments are initialized.
* -# The CPU state is switched to Privileged and the PSP stack is used.
- * -# A late initialization routine @p hwinit1 is invoked, if the symbol not
- * defined then an empty default routine is executed (weak symbol).<br>
- * This late initialization function is also the proper place for a
- * @a bootloader, if your application requires one.
- * -# The @p main() function is invoked with the parameters @p argc and @p argv
- * set to zero.
+ * -# An early initialization routine @p __early_init() is invoked, if the
+ * symbol is not defined then an empty default routine is executed
+ * (weak symbol).
+ * -# DATA and BSS segments are initialized.
+ * -# The @p main() function is invoked with no parameters.
* -# Should the @p main() function return a branch is performed to the weak
- * symbol MainExitHandler. The default code is an endless empty loop.
+ * symbol _main_exit_handler. The default code is an endless empty loop.
* .
* @section ARMCMx_STARTUP_2 Expected linker symbols
* The startup code starts at the symbol @p ResetHandler and expects the
diff --git a/os/ports/IAR/ARMCMx/STM32/cmparams.h b/os/ports/IAR/ARMCMx/STM32/cmparams.h index de07b7c67..d75c3ca2c 100644 --- a/os/ports/IAR/ARMCMx/STM32/cmparams.h +++ b/os/ports/IAR/ARMCMx/STM32/cmparams.h @@ -18,11 +18,11 @@ */
/**
- * @file STM32/cmparams.h
+ * @file IAR/ARMCMx/STM32/cmparams.h
* @brief ARM Cortex-M3 parameters for the STM32.
*
- * @defgroup ARMCMx_STM32 STM32 Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
+ * @defgroup IAR_ARMCMx_STM32 STM32 Specific Parameters
+ * @ingroup IAR_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
* STM32 platform.
* @{
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.c b/os/ports/IAR/ARMCMx/chcore_v6m.c index 4f8bdf02a..dbd2e017a 100644 --- a/os/ports/IAR/ARMCMx/chcore_v6m.c +++ b/os/ports/IAR/ARMCMx/chcore_v6m.c @@ -18,10 +18,10 @@ */
/**
- * @file ARMCMx/chcore_v6m.c
+ * @file IAR/ARMCMx/chcore_v6m.c
* @brief ARMv6-M architecture port code.
*
- * @addtogroup ARMCMx_V6M_CORE
+ * @addtogroup IAR_ARMCMx_V6M_CORE
* @{
*/
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h index 5f45f581d..ecf9a8ea7 100644 --- a/os/ports/IAR/ARMCMx/chcore_v6m.h +++ b/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -18,10 +18,10 @@ */
/**
- * @file ARMCMx/chcore_v6m.h
+ * @file IAR/ARMCMx/chcore_v6m.h
* @brief ARMv6-M architecture port macros and structures.
*
- * @addtogroup ARMCMx_V6M_CORE
+ * @addtogroup IAR_ARMCMx_V6M_CORE
* @{
*/
diff --git a/os/ports/IAR/ARMCMx/port.dox b/os/ports/IAR/ARMCMx/port.dox new file mode 100644 index 000000000..00d669726 --- /dev/null +++ b/os/ports/IAR/ARMCMx/port.dox @@ -0,0 +1,211 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @defgroup IAR_ARMCMx ARM Cortex-Mx
+ * @details ARM Cortex-Mx port for the IAR compiler.
+
+ * @section IAR_ARMCMx_INTRO Introduction
+ * This port supports all the cores implementing the ARMv6-M and ARMv7-M
+ * architectures.
+ *
+ * @section IAR_ARMCMx_STATES_A System logical states in ARMv6-M mode
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
+ * Cortex-M0 port:
+ * - <b>Init</b>. This state is represented by the startup code and the
+ * initialization code before @p chSysInit() is executed. It has not a
+ * special hardware state associated.
+ * - <b>Normal</b>. This is the state the system has after executing
+ * @p chSysInit(). In this state interrupts are enabled. The processor
+ * is running in thread-privileged mode.
+ * - <b>Suspended</b>. In this state the interrupt sources are globally
+ * disabled. The processor is running in thread-privileged mode. In this
+ * mode this state is not different from the <b>Disabled</b> state.
+ * - <b>Disabled</b>. In this state the interrupt sources are globally
+ * disabled. The processor is running in thread-privileged mode. In this
+ * mode this state is not different from the <b>Suspended</b> state.
+ * - <b>Sleep</b>. This state is entered with the execution of the specific
+ * instruction @p <b>wfi</b>.
+ * - <b>S-Locked</b>. In this state the interrupt sources are globally
+ * disabled. The processor is running in thread-privileged mode.
+ * - <b>I-Locked</b>. In this state the interrupt sources are globally
+ * disabled. The processor is running in exception-privileged mode.
+ * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
+ * not globally masked but only interrupts with higher priority can preempt
+ * the current handler. The processor is running in exception-privileged
+ * mode.
+ * - <b>Serving Fast Interrupt</b>. This state is not implemented in the
+ * ARMv6-M implementation.
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * asynchronous NMI vector and several synchronous fault vectors that can
+ * be considered belonging to this category.
+ * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
+ * the maskable interrupt sources. The ARM state is whatever the processor
+ * was running when @p chSysHalt() was invoked.
+ *
+ * @section IAR_ARMCMx_STATES_B System logical states in ARMv7-M mode
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
+ * Cortex-M3 port:
+ * - <b>Init</b>. This state is represented by the startup code and the
+ * initialization code before @p chSysInit() is executed. It has not a
+ * special hardware state associated.
+ * - <b>Normal</b>. This is the state the system has after executing
+ * @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
+ * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
+ * processor is running in thread-privileged mode.
+ * - <b>Suspended</b>. In this state the interrupt sources are not globally
+ * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
+ * masking any interrupt source with lower or equal priority. The processor
+ * is running in thread-privileged mode.
+ * - <b>Disabled</b>. Interrupt sources are globally masked. The processor
+ * is running in thread-privileged mode.
+ * - <b>Sleep</b>. This state is entered with the execution of the specific
+ * instruction @p <b>wfi</b>.
+ * - <b>S-Locked</b>. In this state the interrupt sources are not globally
+ * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
+ * masking any interrupt source with lower or equal priority. The processor
+ * is running in thread-privileged mode.
+ * - <b>I-Locked</b>. In this state the interrupt sources are not globally
+ * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
+ * masking any interrupt source with lower or equal priority. The processor
+ * is running in exception-privileged mode.
+ * - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
+ * not globally masked but only interrupts with higher priority can preempt
+ * the current handler. The processor is running in exception-privileged
+ * mode.
+ * - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
+ * but it is not possible to switch to the I-Locked state because fast
+ * interrupts can preempt the kernel critical zone.
+ * - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
+ * asynchronous NMI vector and several synchronous fault vectors that can
+ * be considered belonging to this category.
+ * - <b>Halted</b>. Implemented as an infinite loop after globally masking all
+ * the maskable interrupt sources. The ARM state is whatever the processor
+ * was running when @p chSysHalt() was invoked.
+ * .
+ * @section IAR_ARMCMx_NOTES ARM Cortex-Mx/IAR port notes
+ * The ARM Cortex-Mx port is organized as follow:
+ * - The @p main() function is invoked in thread-privileged mode.
+ * - Each thread has a private process stack, the system has a single main
+ * stack where all the interrupts and exceptions are processed.
+ * - The threads are started in thread-privileged mode.
+ * - Interrupt nesting and the other advanced core/NVIC features are supported.
+ * - When using an STM32 one of the following macros must be defined on the
+ * compiler command line or in a file named <tt>board.h</tt>:
+ * - @p STM32F10X_LD
+ * - @p STM32F10X_LD_VL
+ * - @p STM32F10X_MD
+ * - @p STM32F10X_MD_VL
+ * - @p STM32F10X_HD
+ * - @p STM32F10X_XL
+ * - @p STM32F10X_CL
+ * .
+ * This is required in order to include a vectors table with the correct
+ * length for the STM32 model, see the file
+ * <tt>./os/ports/IAR/ARMCMx/STM32/vectors.s</tt>.
+ * - The Cortex-Mx port is perfectly generic, support for more devices can be
+ * easily added by adding a subdirectory under <tt>./os/ports/IAR/ARMCMx</tt>
+ * and giving it the name of the new device, then copy the files from another
+ * device into the new directory and customize them for the new device.
+ * .
+ * @ingroup iar
+ */
+
+/**
+ * @defgroup IAR_ARMCMx_CONF Configuration Options
+ * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
+ * architecture-specific configurations settings that can be overridden
+ * by redefining them in @p chconf.h. Usually there is no need to change
+ * the default values.
+ * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
+ * by an interrupt handler between the @p extctx and @p intctx
+ * structures.
+ * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
+ * thread. Usually there is no need to change this value unless inserting
+ * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
+ * - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
+ * code. Code running at higher priority levels must not invoke any OS API.
+ * This setting is specific to the ARMv7-M architecture.
+ * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
+ * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
+ * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
+ * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
+ * @p <b>wfi</b> instruction from within the idle loop. This option is
+ * defaulted to FALSE because it can create problems with some debuggers.
+ * Setting this option to TRUE reduces the system power requirements.
+ * .
+ * @ingroup IAR_ARMCMx
+ */
+
+/**
+ * @defgroup IAR_ARMCMx_CORE Core Port Implementation
+ * @details ARM Cortex-Mx specific port code, structures and macros.
+ *
+ * @ingroup IAR_ARMCMx
+ */
+
+/**
+ * @defgroup IAR_ARMCMx_V6M_CORE ARMv6-M Specific Implementation
+ * @details ARMv6-M specific port code, structures and macros.
+ *
+ * @ingroup IAR_ARMCMx_CORE
+ */
+
+/**
+ * @defgroup IAR_ARMCMx_V7M_CORE ARMv7-M Specific Implementation
+ * @details ARMv7-M specific port code, structures and macros.
+ *
+ * @ingroup IAR_ARMCMx_CORE
+ */
+
+/**
+ * @defgroup IAR_ARMCMx_STARTUP Startup Support
+ * @details ChibiOS/RT provides its own generic startup file for the ARM
+ * Cortex-Mx port.
+ * Of course it is not mandatory to use it but care should be taken about the
+ * startup phase details.
+ *
+ * @section IAR_ARMCMx_STARTUP_1 Startup Process
+ * The startup process, as implemented, is the following:
+ * -# Interrupts are masked globally.
+ * -# The two stacks are initialized by assigning them the sizes defined in the
+ * linker script (usually named @p ch.icf).
+ * -# The CPU state is switched to Privileged and the PSP stack is used.
+ * -# An early initialization routine @p __early_init() is invoked, if the
+ * symbol is not defined then an empty default routine is executed
+ * (weak symbol).
+ * -# Control is passed to the C runtime entry point @p __cmain that performs
+ * the required initializations before invoking the @p main() function.
+ * .
+ * @ingroup IAR_ARMCMx
+ */
+
+/**
+ * @defgroup IAR_ARMCMx_NVIC NVIC Support
+ * @details ARM Cortex-Mx NVIC support.
+ *
+ * @ingroup IAR_ARMCMx
+ */
+
+/**
+ * @defgroup IAR_ARMCMx_SPECIFIC Specific Implementations
+ * @details Platform-specific port code.
+ *
+ * @ingroup IAR_ARMCMx
+ */
diff --git a/os/ports/ports.dox b/os/ports/ports.dox index 7c48feece..30d732504 100644 --- a/os/ports/ports.dox +++ b/os/ports/ports.dox @@ -31,6 +31,13 @@ */
/**
+ * @defgroup iar IAR Ports
+ * Ports for the IAR compiler.
+ *
+ * @ingroup ports
+ */
+
+/**
* @defgroup cosmic Cosmic Compiler Ports
* Ports for the Compiler compiler.
*
|