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-rw-r--r--docs/reports/LPC1114-48-RVCT.txt26
-rw-r--r--os/kernel/src/chmemcore.c8
-rw-r--r--os/ports/RVCT/ARMCMx/chcore_v6m.h12
-rw-r--r--os/ports/RVCT/ARMCMx/chcoreasm_v6m.s33
4 files changed, 34 insertions, 45 deletions
diff --git a/docs/reports/LPC1114-48-RVCT.txt b/docs/reports/LPC1114-48-RVCT.txt
index 17df988de..1b1015d94 100644
--- a/docs/reports/LPC1114-48-RVCT.txt
+++ b/docs/reports/LPC1114-48-RVCT.txt
@@ -6,7 +6,7 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation].
*** ChibiOS/RT test suite
***
-*** Kernel: 2.1.7unstable
+*** Kernel: 2.3.0unstable
*** Architecture: ARMv6-M
*** Core Variant: Cortex-M0
*** Platform: LPC11xx
@@ -98,51 +98,51 @@ Compiler: RealView C/C++ Compiler V4.1.0.561 [Evaluation].
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 116826 msgs/S, 233652 ctxswc/S
+--- Score : 119522 msgs/S, 239044 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
---- Score : 100172 msgs/S, 200344 ctxswc/S
+--- Score : 102156 msgs/S, 204312 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 99754 msgs/S, 199508 ctxswc/S
+--- Score : 102595 msgs/S, 205190 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
---- Score : 377360 ctxswc/S
+--- Score : 375344 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 79506 threads/S
+--- Score : 79025 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 112694 threads/S
+--- Score : 111705 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 33626 reschedules/S, 201756 ctxswc/S
+--- Score : 33692 reschedules/S, 202152 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 246616 ctxswc/S
+--- Score : 249324 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 261068 bytes/S
+--- Score : 264832 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 301424 timers/S
+--- Score : 303508 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 614472 wait+signal/S
+--- Score : 614828 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 382980 lock+unlock/S
+--- Score : 381660 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
diff --git a/os/kernel/src/chmemcore.c b/os/kernel/src/chmemcore.c
index 1fed481c5..c28d150fa 100644
--- a/os/kernel/src/chmemcore.c
+++ b/os/kernel/src/chmemcore.c
@@ -57,10 +57,10 @@ static uint8_t *endmem;
*/
void core_init(void) {
#if CH_MEMCORE_SIZE == 0
- extern uint8_t __heap_base__;
- extern uint8_t __heap_end__;
- nextmem = (uint8_t *)MEM_ALIGN_NEXT(&__heap_base__);
- endmem = (uint8_t *)MEM_ALIGN_PREV(&__heap_end__);
+ extern uint8_t __heap_base__[];
+ extern uint8_t __heap_end__[];
+ nextmem = (uint8_t *)MEM_ALIGN_NEXT(__heap_base__);
+ endmem = (uint8_t *)MEM_ALIGN_PREV(__heap_end__);
#else
static stkalign_t buffer[MEM_ALIGN_NEXT(CH_MEMCORE_SIZE)/MEM_ALIGN_SIZE];
nextmem = (uint8_t *)&buffer[0];
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h
index 796b7f22e..59d5b6af0 100644
--- a/os/ports/RVCT/ARMCMx/chcore_v6m.h
+++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h
@@ -118,18 +118,14 @@ struct intctx {
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_PROLOGUE() { \
- port_lock_from_isr(); \
- _port_irq_nesting++; \
- port_unlock_from_isr(); \
-}
+#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__return_address()
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
+#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
/**
* @brief IRQ handler function declaration.
@@ -149,7 +145,6 @@ struct intctx {
* @brief Port-related initialization code.
*/
#define port_init() { \
- _port_irq_nesting = 0; \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
@@ -230,7 +225,6 @@ struct intctx {
#if !defined(__DOXYGEN__)
extern regarm_t _port_saved_pc;
-extern unsigned _port_irq_nesting;
#endif
#ifdef __cplusplus
@@ -238,7 +232,7 @@ extern "C" {
#endif
void port_halt(void);
void _port_switch(Thread *ntp, Thread *otp);
- void _port_irq_epilogue(void);
+ void _port_irq_epilogue(regarm_t lr);
void _port_switch_from_isr(void);
void _port_thread_start(void);
#ifdef __cplusplus
diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
index 2424de03f..a789e4a0e 100644
--- a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
+++ b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
@@ -103,29 +103,24 @@ _port_switch_from_isr PROC
*/
EXPORT _port_irq_epilogue
_port_irq_epilogue PROC
- push {r4, lr}
+ push {r3, lr}
+ adds r0, r0, #15
+ beq stillnested
cpsid i
- ldr r2, =_port_irq_nesting
- ldr r3, [r2]
- subs r3, r3, #1
- str r3, [r2]
- cmp r3, #0
- beq skipexit
-notrequired
- cpsie i
- pop {r4, pc}
-skipexit
bl chSchIsRescRequiredExI
cmp r0, #0
- beq notrequired
- mrs r1, PSP
+ bne doresch
+ cpsie i
+stillnested
+ pop {r3, pc}
+doresch
+ mrs r3, PSP
ldr r2, =_port_saved_pc
- ldr r3, [r1, #24]
- str r3, [r2]
- ldr r3, =_port_switch_from_isr
- str r3, [r1, #24]
- pop {r4, pc}
- nop
+ ldr r1, [r3, #24]
+ str r1, [r2]
+ ldr r2, =_port_switch_from_isr
+ str r2, [r3, #24]
+ pop {r3, pc}
ENDP
END