diff options
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h | 27 | ||||
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/arm_math.h | 3862 | ||||
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/core_cm0.h | 224 | ||||
-rwxr-xr-x | os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h | 778 | ||||
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/core_cm3.h | 748 | ||||
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/core_cm4.h | 765 | ||||
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h | 302 | ||||
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h | 126 | ||||
-rw-r--r-- | os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h | 133 |
9 files changed, 4493 insertions, 2472 deletions
diff --git a/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h b/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h index 34f910f9b..5fd6ff4af 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h +++ b/os/ports/common/ARMCMx/CMSIS/include/arm_common_tables.h @@ -19,17 +19,20 @@ *
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern uint16_t armBitRevTable[256];
-extern q15_t armRecipTableQ15[64];
-extern q31_t armRecipTableQ31[64];
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
-
-#endif /* ARM_COMMON_TABLES_H */
+extern const float32_t twiddleCoef[6144];
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/arm_math.h b/os/ports/common/ARMCMx/CMSIS/include/arm_math.h index d8901db15..ebaf6b21b 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/arm_math.h +++ b/os/ports/common/ARMCMx/CMSIS/include/arm_math.h @@ -1,16 +1,19 @@ /* ----------------------------------------------------------------------
- * Copyright (C) 2010 ARM Limited. All rights reserved.
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
- * $Date: 15. July 2011
- * $Revision: V1.0.10
+ * $Date: 15. February 2012
+ * $Revision: V1.1.0
*
* Project: CMSIS DSP Library
- * Title: arm_math.h
+ * Title: arm_math.h
*
* Description: Public header file for CMSIS DSP Library
*
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
*
+ * Version 1.1.0 2012/02/15
+ * Updated with more optimizations, bug fixes and minor API changes.
+ *
* Version 1.0.10 2011/7/15
* Big Endian support added and Merged M0 and M3/M4 Source code.
*
@@ -35,7 +38,7 @@ * This user manual describes the CMSIS DSP software library,
* a suite of common signal processing functions for use on Cortex-M processor based devices.
*
- * The library is divided into a number of modules each covering a specific category:
+ * The library is divided into a number of functions each covering a specific category:
* - Basic math functions
* - Fast math functions
* - Complex math functions
@@ -50,18 +53,38 @@ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
* 32-bit integer and 32-bit floating-point values.
*
- * <b>Processor Support</b>
+ * <b>Pre-processor Macros</b>
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
*
- * The library is completely written in C and is fully CMSIS compliant.
- * High performance is achieved through maximum use of Cortex-M4 intrinsics.
+ * - ARM_MATH_CMx:
*
- * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
- * with the DSP intrinsics being emulated through software.
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.
+ *
+ * - __FPU_PRESENT:
*
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
*
* <b>Toolchain Support</b>
*
- * The library has been developed and tested with MDK-ARM version 4.21.
+ * The library has been developed and tested with MDK-ARM version 4.23.
* The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
*
* <b>Using the Library</b>
@@ -88,7 +111,7 @@ *
* <b>Building the Library</b>
*
- * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\DSP_Lib\Source\ARM</code> folder.
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
* - arm_cortexM0b_math.uvproj
* - arm_cortexM0l_math.uvproj
* - arm_cortexM3b_math.uvproj
@@ -98,26 +121,8 @@ * - arm_cortexM4bf_math.uvproj
* - arm_cortexM4lf_math.uvproj
*
- * Each library project have differant pre-processor macros.
- *
- * <b>ARM_MATH_CMx:</b>
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on cortex-M0 target.
- *
- * <b>ARM_MATH_BIG_ENDIAN:</b>
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * <b>ARM_MATH_MATRIX_CHECK:</b>
- * Define macro for checking on the input and output sizes of matrices
*
- * <b>ARM_MATH_ROUNDING:</b>
- * Define macro for rounding on support functions
- *
- * <b>__FPU_PRESENT:</b>
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
- *
- *
- * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
+ * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above.
*
* <b>Copyright Notice</b>
*
@@ -212,7 +217,7 @@ * ARM_MATH_SUCCESS
* </pre>
* There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the #define
+ * The matrix size checking is enabled via the \#define
* <pre>
* ARM_MATH_MATRIX_CHECK
* </pre>
@@ -251,22 +256,22 @@ #ifndef _ARM_MATH_H
#define _ARM_MATH_H
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
#if defined (ARM_MATH_CM4)
- #include "core_cm4.h"
+#include "core_cm4.h"
#elif defined (ARM_MATH_CM3)
- #include "core_cm3.h"
+#include "core_cm3.h"
#elif defined (ARM_MATH_CM0)
- #include "core_cm0.h"
+#include "core_cm0.h"
#else
#include "ARMCM4.h"
#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
#endif
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
#include "string.h"
- #include "math.h"
+#include "math.h"
#ifdef __cplusplus
extern "C"
{
@@ -280,7 +285,9 @@ extern "C" #define DELTA_Q31 (0x100)
#define DELTA_Q15 0x5
#define INDEX_MASK 0x0000003F
+#ifndef PI
#define PI 3.14159265358979f
+#endif
/**
* @brief Macros required for SINE and COSINE Fast math approximations
@@ -297,21 +304,33 @@ extern "C" /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
#define INPUT_SPACING 0xB60B61
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
/**
* @brief Error status returned by some functions in the library.
*/
typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
/**
* @brief 8-bit fractional data type in 1.7 format.
@@ -346,7 +365,15 @@ extern "C" /**
* @brief definition to read/write two 16 bit values.
*/
-#define __SIMD32(addr) (*(int32_t **) & (addr))
+#if defined (__GNUC__)
+ #define __SIMD32(addr) (*( int32_t **) & (addr))
+ #define _SIMD32_OFFSET(addr) (*( int32_t * ) (addr))
+#else
+ #define __SIMD32(addr) (*(__packed int32_t **) & (addr))
+ #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr))
+#endif
+
+ #define __SIMD64(addr) (*(int64_t **) & (addr))
#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
/**
@@ -354,6 +381,8 @@ extern "C" */
#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
(((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
#endif
@@ -367,21 +396,21 @@ extern "C" (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
+#else
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
(((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-
+
#endif
/**
* @brief Clips Q63 to Q31 values.
*/
- static __INLINE q31_t clip_q63_to_q31(
- q63_t x)
+ __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
{
return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
@@ -390,8 +419,8 @@ extern "C" /**
* @brief Clips Q63 to Q15 values.
*/
- static __INLINE q15_t clip_q63_to_q15(
- q63_t x)
+ __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
{
return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
@@ -400,8 +429,8 @@ extern "C" /**
* @brief Clips Q31 to Q7 values.
*/
- static __INLINE q7_t clip_q31_to_q7(
- q31_t x)
+ __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
{
return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
@@ -410,8 +439,8 @@ extern "C" /**
* @brief Clips Q31 to Q15 values.
*/
- static __INLINE q15_t clip_q31_to_q15(
- q31_t x)
+ __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
{
return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
@@ -421,9 +450,9 @@ extern "C" * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
*/
- static __INLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
+ __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
{
return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
(((q63_t) (x >> 32) * y)));
@@ -432,38 +461,42 @@ extern "C" #if defined (ARM_MATH_CM0) && defined ( __CC_ARM )
#define __CLZ __clz
-#endif
+#endif
+
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )
+/* No need to redefine __CLZ */
+#endif
-#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )
- static __INLINE uint32_t __CLZ(q31_t data);
+ __STATIC_INLINE uint32_t __CLZ(q31_t data);
- static __INLINE uint32_t __CLZ(q31_t data)
+ __STATIC_INLINE uint32_t __CLZ(q31_t data)
{
- uint32_t count = 0;
- uint32_t mask = 0x80000000;
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
- while((data & mask) == 0)
- {
- count += 1u;
- mask = mask >> 1u;
- }
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
- return(count);
+ return (count);
}
-#endif
+#endif
/**
* @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
*/
- static __INLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- q31_t * pRecipTable)
+ __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
{
uint32_t out, tempVal;
@@ -471,13 +504,13 @@ extern "C" uint32_t signBits;
if(in > 0)
- {
- signBits = __CLZ(in) - 1;
- }
+ {
+ signBits = __CLZ(in) - 1;
+ }
else
- {
- signBits = __CLZ(-in) - 1;
- }
+ {
+ signBits = __CLZ(-in) - 1;
+ }
/* Convert input sample to 1.31 format */
in = in << signBits;
@@ -492,13 +525,13 @@ extern "C" /* calculation of reciprocal value */
/* running approximation for two iterations */
for (i = 0u; i < 2u; i++)
- {
- tempVal = (q31_t) (((q63_t) in * out) >> 31u);
- tempVal = 0x7FFFFFFF - tempVal;
- /* 1.31 with exp 1 */
- //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
- out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
- }
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
/* write output */
*dst = out;
@@ -511,10 +544,10 @@ extern "C" /**
* @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
*/
- static __INLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- q15_t * pRecipTable)
+ __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
{
uint32_t out = 0, tempVal = 0;
@@ -522,13 +555,13 @@ extern "C" uint32_t signBits = 0;
if(in > 0)
- {
- signBits = __CLZ(in) - 17;
- }
+ {
+ signBits = __CLZ(in) - 17;
+ }
else
- {
- signBits = __CLZ(-in) - 17;
- }
+ {
+ signBits = __CLZ(-in) - 17;
+ }
/* Convert input sample to 1.15 format */
in = in << signBits;
@@ -543,12 +576,12 @@ extern "C" /* calculation of reciprocal value */
/* running approximation for two iterations */
for (i = 0; i < 2; i++)
- {
- tempVal = (q15_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFF - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- }
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
/* write output */
*dst = out;
@@ -564,37 +597,37 @@ extern "C" */
#if defined(ARM_MATH_CM0)
- static __INLINE q31_t __SSAT(
- q31_t x,
- uint32_t y)
+ __STATIC_INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
{
int32_t posMax, negMin;
uint32_t i;
posMax = 1;
for (i = 0; i < (y - 1); i++)
- {
- posMax = posMax * 2;
- }
+ {
+ posMax = posMax * 2;
+ }
if(x > 0)
- {
- posMax = (posMax - 1);
+ {
+ posMax = (posMax - 1);
- if(x > posMax)
- {
- x = posMax;
- }
+ if(x > posMax)
+ {
+ x = posMax;
}
+ }
else
- {
- negMin = -posMax;
+ {
+ negMin = -posMax;
- if(x < negMin)
- {
- x = negMin;
- }
+ if(x < negMin)
+ {
+ x = negMin;
}
+ }
return (x);
@@ -612,23 +645,24 @@ extern "C" /*
* @brief C custom defined QADD8 for M3 and M0 processors
*/
- static __INLINE q31_t __QADD8(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
{
q31_t sum;
q7_t r, s, t, u;
- r = (char) x;
- s = (char) y;
+ r = (q7_t) x;
+ s = (q7_t) y;
r = __SSAT((q31_t) (r + s), 8);
s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
- sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
(((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
return sum;
@@ -638,16 +672,16 @@ extern "C" /*
* @brief C custom defined QSUB8 for M3 and M0 processors
*/
- static __INLINE q31_t __QSUB8(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
{
q31_t sum;
q31_t r, s, t, u;
- r = (char) x;
- s = (char) y;
+ r = (q7_t) x;
+ s = (q7_t) y;
r = __SSAT((r - s), 8);
s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
@@ -655,7 +689,8 @@ extern "C" u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
sum =
- (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
return sum;
}
@@ -667,9 +702,9 @@ extern "C" /*
* @brief C custom defined QADD16 for M3 and M0 processors
*/
- static __INLINE q31_t __QADD16(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
{
q31_t sum;
@@ -690,9 +725,9 @@ extern "C" /*
* @brief C custom defined SHADD16 for M3 and M0 processors
*/
- static __INLINE q31_t __SHADD16(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
{
q31_t sum;
@@ -713,9 +748,9 @@ extern "C" /*
* @brief C custom defined QSUB16 for M3 and M0 processors
*/
- static __INLINE q31_t __QSUB16(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
{
q31_t sum;
@@ -735,9 +770,9 @@ extern "C" /*
* @brief C custom defined SHSUB16 for M3 and M0 processors
*/
- static __INLINE q31_t __SHSUB16(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
{
q31_t diff;
@@ -757,14 +792,16 @@ extern "C" /*
* @brief C custom defined QASX for M3 and M0 processors
*/
- static __INLINE q31_t __QASX(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
{
q31_t sum = 0;
- sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
return sum;
@@ -773,9 +810,9 @@ extern "C" /*
* @brief C custom defined SHASX for M3 and M0 processors
*/
- static __INLINE q31_t __SHASX(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
{
q31_t sum;
@@ -796,14 +833,16 @@ extern "C" /*
* @brief C custom defined QSAX for M3 and M0 processors
*/
- static __INLINE q31_t __QSAX(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
{
q31_t sum = 0;
- sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
return sum;
@@ -812,9 +851,9 @@ extern "C" /*
* @brief C custom defined SHSAX for M3 and M0 processors
*/
- static __INLINE q31_t __SHSAX(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
{
q31_t sum;
@@ -834,33 +873,33 @@ extern "C" /*
* @brief C custom defined SMUSDX for M3 and M0 processors
*/
- static __INLINE q31_t __SMUSDX(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
{
- return ((q31_t)(((short) x * (short) (y >> 16)) -
- ((short) (x >> 16) * (short) y)));
+ return ((q31_t) (((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
}
/*
* @brief C custom defined SMUADX for M3 and M0 processors
*/
- static __INLINE q31_t __SMUADX(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
{
- return ((q31_t)(((short) x * (short) (y >> 16)) +
- ((short) (x >> 16) * (short) y)));
+ return ((q31_t) (((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
}
/*
* @brief C custom defined QADD for M3 and M0 processors
*/
- static __INLINE q31_t __QADD(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
{
return clip_q63_to_q31((q63_t) x + y);
}
@@ -868,9 +907,9 @@ extern "C" /*
* @brief C custom defined QSUB for M3 and M0 processors
*/
- static __INLINE q31_t __QSUB(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
{
return clip_q63_to_q31((q63_t) x - y);
}
@@ -878,10 +917,10 @@ extern "C" /*
* @brief C custom defined SMLAD for M3 and M0 processors
*/
- static __INLINE q31_t __SMLAD(
- q31_t x,
- q31_t y,
- q31_t sum)
+ __STATIC_INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
{
return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
@@ -891,10 +930,10 @@ extern "C" /*
* @brief C custom defined SMLADX for M3 and M0 processors
*/
- static __INLINE q31_t __SMLADX(
- q31_t x,
- q31_t y,
- q31_t sum)
+ __STATIC_INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
{
return (sum + ((short) (x >> 16) * (short) (y)) +
@@ -904,10 +943,10 @@ extern "C" /*
* @brief C custom defined SMLSDX for M3 and M0 processors
*/
- static __INLINE q31_t __SMLSDX(
- q31_t x,
- q31_t y,
- q31_t sum)
+ __STATIC_INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
{
return (sum - ((short) (x >> 16) * (short) (y)) +
@@ -917,10 +956,10 @@ extern "C" /*
* @brief C custom defined SMLALD for M3 and M0 processors
*/
- static __INLINE q63_t __SMLALD(
- q31_t x,
- q31_t y,
- q63_t sum)
+ __STATIC_INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
{
return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
@@ -930,10 +969,10 @@ extern "C" /*
* @brief C custom defined SMLALDX for M3 and M0 processors
*/
- static __INLINE q63_t __SMLALDX(
- q31_t x,
- q31_t y,
- q63_t sum)
+ __STATIC_INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
{
return (sum + ((short) (x >> 16) * (short) y)) +
@@ -943,9 +982,9 @@ extern "C" /*
* @brief C custom defined SMUAD for M3 and M0 processors
*/
- static __INLINE q31_t __SMUAD(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
{
return (((x >> 16) * (y >> 16)) +
@@ -955,9 +994,9 @@ extern "C" /*
* @brief C custom defined SMUSD for M3 and M0 processors
*/
- static __INLINE q31_t __SMUSD(
- q31_t x,
- q31_t y)
+ __STATIC_INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
{
return (-((x >> 16) * (y >> 16)) +
@@ -965,9 +1004,19 @@ extern "C" }
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
-#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
/**
@@ -1020,10 +1069,10 @@ extern "C" * @return none.
*/
void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
@@ -1036,11 +1085,11 @@ extern "C" * @return none
*/
void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
/**
@@ -1052,10 +1101,10 @@ extern "C" * @return none.
*/
void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
@@ -1066,10 +1115,10 @@ extern "C" * @return none.
*/
void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q15 FIR filter.
@@ -1081,13 +1130,13 @@ extern "C" * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
* <code>numTaps</code> is not a supported value.
*/
-
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR filter.
@@ -1098,10 +1147,10 @@ extern "C" * @return none.
*/
void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
@@ -1112,10 +1161,10 @@ extern "C" * @return none.
*/
void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q31 FIR filter.
@@ -1127,11 +1176,11 @@ extern "C" * @return none.
*/
void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
/**
* @brief Processing function for the floating-point FIR filter.
@@ -1142,10 +1191,10 @@ extern "C" * @return none.
*/
void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the floating-point FIR filter.
@@ -1157,11 +1206,11 @@ extern "C" * @return none.
*/
void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
/**
@@ -1213,10 +1262,10 @@ extern "C" */
void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q15 Biquad cascade filter.
@@ -1229,11 +1278,11 @@ extern "C" */
void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
/**
@@ -1246,10 +1295,10 @@ extern "C" */
void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
@@ -1262,10 +1311,10 @@ extern "C" */
void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
@@ -1277,10 +1326,10 @@ extern "C" */
void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q31 Biquad cascade filter.
@@ -1293,11 +1342,11 @@ extern "C" */
void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
/**
* @brief Processing function for the floating-point Biquad cascade filter.
@@ -1309,10 +1358,10 @@ extern "C" */
void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the floating-point Biquad cascade filter.
@@ -1324,10 +1373,10 @@ extern "C" */
void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
/**
@@ -1377,9 +1426,9 @@ extern "C" */
arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix addition.
@@ -1391,9 +1440,9 @@ extern "C" */
arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix addition.
@@ -1405,9 +1454,9 @@ extern "C" */
arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
/**
@@ -1419,8 +1468,8 @@ extern "C" */
arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
/**
@@ -1432,8 +1481,8 @@ extern "C" */
arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix transpose.
@@ -1444,8 +1493,8 @@ extern "C" */
arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
/**
@@ -1458,9 +1507,9 @@ extern "C" */
arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix multiplication
@@ -1472,10 +1521,10 @@ extern "C" */
arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
/**
* @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
@@ -1488,10 +1537,10 @@ extern "C" */
arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
/**
* @brief Q31 matrix multiplication
@@ -1503,9 +1552,9 @@ extern "C" */
arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
/**
* @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
@@ -1517,9 +1566,9 @@ extern "C" */
arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
/**
@@ -1532,9 +1581,9 @@ extern "C" */
arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix subtraction
@@ -1546,9 +1595,9 @@ extern "C" */
arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix subtraction
@@ -1560,9 +1609,9 @@ extern "C" */
arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
/**
* @brief Floating-point matrix scaling.
@@ -1574,9 +1623,9 @@ extern "C" */
arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
/**
* @brief Q15 matrix scaling.
@@ -1589,10 +1638,10 @@ extern "C" */
arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
/**
* @brief Q31 matrix scaling.
@@ -1605,10 +1654,10 @@ extern "C" */
arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
/**
@@ -1621,10 +1670,10 @@ extern "C" */
void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t *pData);
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
/**
* @brief Q15 matrix initialization.
@@ -1636,10 +1685,10 @@ extern "C" */
void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t *pData);
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
/**
* @brief Floating-point matrix initialization.
@@ -1651,10 +1700,10 @@ extern "C" */
void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t *pData);
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
@@ -1663,13 +1712,13 @@ extern "C" */
typedef struct
{
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- #ifdef ARM_MATH_CM0
- q15_t A1;
- q15_t A2;
- #else
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0
+ q15_t A1;
+ q15_t A2;
+#else
q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
- #endif
+#endif
q15_t state[3]; /**< The state array of length 3. */
q15_t Kp; /**< The proportional gain. */
q15_t Ki; /**< The integral gain. */
@@ -1714,8 +1763,8 @@ extern "C" * @return none.
*/
void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
/**
* @brief Reset function for the floating-point PID Control.
@@ -1723,7 +1772,7 @@ extern "C" * @return none
*/
void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
+ arm_pid_instance_f32 * S);
/**
@@ -1733,10 +1782,10 @@ extern "C" * @return none.
*/
void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
-
/**
* @brief Reset function for the Q31 PID Control.
* @param[in,out] *S points to an instance of the Q31 PID Control structure
@@ -1744,7 +1793,7 @@ extern "C" */
void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
+ arm_pid_instance_q31 * S);
/**
* @brief Initialization function for the Q15 PID Control.
@@ -1753,8 +1802,8 @@ extern "C" * @return none.
*/
void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
/**
* @brief Reset function for the Q15 PID Control.
@@ -1762,7 +1811,7 @@ extern "C" * @return none
*/
void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
+ arm_pid_instance_q15 * S);
/**
@@ -1770,9 +1819,9 @@ extern "C" */
typedef struct
{
- uint32_t nValues;
- float32_t x1;
- float32_t xSpacing;
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
float32_t *pYData; /**< pointer to the table of Y values */
} arm_linear_interp_instance_f32;
@@ -1782,9 +1831,9 @@ extern "C" typedef struct
{
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
} arm_bilinear_interp_instance_f32;
/**
@@ -1793,9 +1842,9 @@ extern "C" typedef struct
{
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
} arm_bilinear_interp_instance_q31;
/**
@@ -1804,9 +1853,9 @@ extern "C" typedef struct
{
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
} arm_bilinear_interp_instance_q15;
/**
@@ -1815,9 +1864,9 @@ extern "C" typedef struct
{
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
} arm_bilinear_interp_instance_q7;
@@ -1831,10 +1880,10 @@ extern "C" */
void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q15 vector multiplication.
@@ -1846,10 +1895,10 @@ extern "C" */
void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q31 vector multiplication.
@@ -1861,10 +1910,10 @@ extern "C" */
void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Floating-point vector multiplication.
@@ -1876,10 +1925,10 @@ extern "C" */
void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
@@ -1888,13 +1937,13 @@ extern "C" typedef struct
{
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q15;
/**
@@ -1903,31 +1952,80 @@ extern "C" typedef struct
{
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q31;
+
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
typedef struct
{
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
} arm_cfft_radix4_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+
/**
* @brief Processing function for the Q15 CFFT/CIFFT.
* @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
@@ -1936,8 +2034,19 @@ extern "C" */
void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
/**
* @brief Initialization function for the Q15 CFFT/CIFFT.
@@ -1949,10 +2058,25 @@ extern "C" */
arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Initialization function for the Q15 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
/**
* @brief Processing function for the Q31 CFFT/CIFFT.
@@ -1962,8 +2086,8 @@ extern "C" */
void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
/**
* @brief Initialization function for the Q31 CFFT/CIFFT.
@@ -1973,12 +2097,66 @@ extern "C" * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
*/
-
+
arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Radix-2 Q31 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+
+ /**
+ * @brief Processing function for the floating-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Initialization function for the floating-point CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
/**
* @brief Processing function for the floating-point CFFT/CIFFT.
@@ -1988,8 +2166,8 @@ extern "C" */
void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
/**
* @brief Initialization function for the floating-point CFFT/CIFFT.
@@ -1999,12 +2177,12 @@ extern "C" * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
*/
-
+
arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
@@ -2020,12 +2198,12 @@ extern "C" * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
-
+
void arm_radix4_butterfly_f32(
- float32_t * pSrc,
- uint16_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier);
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
/**
* @brief Core function for the floating-point CIFFT butterfly process.
@@ -2036,13 +2214,13 @@ extern "C" * @param[in] onebyfftLen value of 1/fftLen.
* @return none.
*/
-
+
void arm_radix4_butterfly_inverse_f32(
- float32_t * pSrc,
- uint16_t fftLen,
- float32_t * pCoef,
- uint16_t twidCoefModifier,
- float32_t onebyfftLen);
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
/**
* @brief In-place bit reversal function.
@@ -2054,27 +2232,119 @@ extern "C" */
void arm_bitreversal_f32(
- float32_t *pSrc,
- uint16_t fftSize,
- uint16_t bitRevFactor,
- uint16_t *pBitRevTab);
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
/**
* @brief Core function for the Q31 CFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
* @param[in] fftLen length of the FFT.
- * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
-
+
void arm_radix4_butterfly_q31(
- q31_t *pSrc,
- uint32_t fftLen,
- q31_t *pCoef,
- uint32_t twidCoefModifier);
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
/**
+ * @brief Core function for the f32 FFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of f32 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the f32 IFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of f32 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @param[in] onebyfftLen 1/fftLenfth
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+ /**
* @brief Core function for the Q31 CIFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
* @param[in] fftLen length of the FFT.
@@ -2082,13 +2352,13 @@ extern "C" * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
-
+
void arm_radix4_butterfly_inverse_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- q31_t * pCoef,
- uint32_t twidCoefModifier);
-
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
/**
* @brief In-place bit reversal function.
* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
@@ -2099,10 +2369,10 @@ extern "C" */
void arm_bitreversal_q31(
- q31_t * pSrc,
- uint32_t fftLen,
- uint16_t bitRevFactor,
- uint16_t *pBitRevTab);
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
/**
* @brief Core function for the Q15 CFFT butterfly process.
@@ -2114,10 +2384,11 @@ extern "C" */
void arm_radix4_butterfly_q15(
- q15_t *pSrc16,
- uint32_t fftLen,
- q15_t *pCoef16,
- uint32_t twidCoefModifier);
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
/**
* @brief Core function for the Q15 CIFFT butterfly process.
@@ -2129,10 +2400,10 @@ extern "C" */
void arm_radix4_butterfly_inverse_q15(
- q15_t *pSrc16,
- uint32_t fftLen,
- q15_t *pCoef16,
- uint32_t twidCoefModifier);
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
/**
* @brief In-place bit reversal function.
@@ -2144,10 +2415,11 @@ extern "C" */
void arm_bitreversal_q15(
- q15_t * pSrc,
- uint32_t fftLen,
- uint16_t bitRevFactor,
- uint16_t *pBitRevTab);
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
/**
* @brief Instance structure for the Q15 RFFT/RIFFT function.
@@ -2157,12 +2429,12 @@ extern "C" {
uint32_t fftLenReal; /**< length of the real FFT. */
uint32_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} arm_rfft_instance_q15;
/**
@@ -2173,11 +2445,11 @@ extern "C" {
uint32_t fftLenReal; /**< length of the real FFT. */
uint32_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} arm_rfft_instance_q31;
@@ -2187,11 +2459,11 @@ extern "C" typedef struct
{
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
@@ -2206,9 +2478,9 @@ extern "C" */
void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
/**
* @brief Initialization function for the Q15 RFFT/RIFFT.
@@ -2221,11 +2493,11 @@ extern "C" */
arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
/**
* @brief Processing function for the Q31 RFFT/RIFFT.
@@ -2236,9 +2508,9 @@ extern "C" */
void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
/**
* @brief Initialization function for the Q31 RFFT/RIFFT.
@@ -2251,11 +2523,11 @@ extern "C" */
arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
/**
* @brief Initialization function for the floating-point RFFT/RIFFT.
@@ -2268,11 +2540,11 @@ extern "C" */
arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
/**
* @brief Processing function for the floating-point RFFT/RIFFT.
@@ -2283,9 +2555,9 @@ extern "C" */
void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
/**
* @brief Instance structure for the floating-point DCT4/IDCT4 function.
@@ -2314,12 +2586,12 @@ extern "C" */
arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
/**
* @brief Processing function for the floating-point DCT4/IDCT4.
@@ -2330,9 +2602,9 @@ extern "C" */
void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
/**
* @brief Instance structure for the Q31 DCT4/IDCT4 function.
@@ -2361,12 +2633,12 @@ extern "C" */
arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
/**
* @brief Processing function for the Q31 DCT4/IDCT4.
@@ -2377,9 +2649,9 @@ extern "C" */
void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
/**
* @brief Instance structure for the Q15 DCT4/IDCT4 function.
@@ -2408,12 +2680,12 @@ extern "C" */
arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
/**
* @brief Processing function for the Q15 DCT4/IDCT4.
@@ -2424,9 +2696,9 @@ extern "C" */
void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
/**
* @brief Floating-point vector addition.
@@ -2438,10 +2710,10 @@ extern "C" */
void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q7 vector addition.
@@ -2453,10 +2725,10 @@ extern "C" */
void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q15 vector addition.
@@ -2468,10 +2740,10 @@ extern "C" */
void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q31 vector addition.
@@ -2483,10 +2755,10 @@ extern "C" */
void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Floating-point vector subtraction.
@@ -2498,10 +2770,10 @@ extern "C" */
void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q7 vector subtraction.
@@ -2513,10 +2785,10 @@ extern "C" */
void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q15 vector subtraction.
@@ -2528,10 +2800,10 @@ extern "C" */
void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q31 vector subtraction.
@@ -2543,10 +2815,10 @@ extern "C" */
void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Multiplies a floating-point vector by a scalar.
@@ -2558,10 +2830,10 @@ extern "C" */
void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Multiplies a Q7 vector by a scalar.
@@ -2574,11 +2846,11 @@ extern "C" */
void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Multiplies a Q15 vector by a scalar.
@@ -2591,11 +2863,11 @@ extern "C" */
void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Multiplies a Q31 vector by a scalar.
@@ -2608,11 +2880,11 @@ extern "C" */
void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q7 vector absolute value.
@@ -2623,9 +2895,9 @@ extern "C" */
void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Floating-point vector absolute value.
@@ -2636,9 +2908,9 @@ extern "C" */
void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q15 vector absolute value.
@@ -2649,9 +2921,9 @@ extern "C" */
void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Q31 vector absolute value.
@@ -2662,9 +2934,9 @@ extern "C" */
void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Dot product of floating-point vectors.
@@ -2676,10 +2948,10 @@ extern "C" */
void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
/**
* @brief Dot product of Q7 vectors.
@@ -2691,10 +2963,10 @@ extern "C" */
void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
/**
* @brief Dot product of Q15 vectors.
@@ -2706,10 +2978,10 @@ extern "C" */
void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
/**
* @brief Dot product of Q31 vectors.
@@ -2721,10 +2993,10 @@ extern "C" */
void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
/**
* @brief Shifts the elements of a Q7 vector a specified number of bits.
@@ -2736,10 +3008,10 @@ extern "C" */
void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Shifts the elements of a Q15 vector a specified number of bits.
@@ -2751,10 +3023,10 @@ extern "C" */
void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Shifts the elements of a Q31 vector a specified number of bits.
@@ -2766,10 +3038,10 @@ extern "C" */
void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Adds a constant offset to a floating-point vector.
@@ -2781,10 +3053,10 @@ extern "C" */
void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Adds a constant offset to a Q7 vector.
@@ -2796,10 +3068,10 @@ extern "C" */
void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Adds a constant offset to a Q15 vector.
@@ -2811,10 +3083,10 @@ extern "C" */
void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Adds a constant offset to a Q31 vector.
@@ -2826,10 +3098,10 @@ extern "C" */
void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Negates the elements of a floating-point vector.
@@ -2840,9 +3112,9 @@ extern "C" */
void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Negates the elements of a Q7 vector.
@@ -2853,9 +3125,9 @@ extern "C" */
void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Negates the elements of a Q15 vector.
@@ -2866,9 +3138,9 @@ extern "C" */
void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Negates the elements of a Q31 vector.
@@ -2879,9 +3151,9 @@ extern "C" */
void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Copies the elements of a floating-point vector.
* @param[in] *pSrc input pointer
@@ -2890,9 +3162,9 @@ extern "C" * @return none.
*/
void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Copies the elements of a Q7 vector.
@@ -2902,9 +3174,9 @@ extern "C" * @return none.
*/
void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Copies the elements of a Q15 vector.
@@ -2914,9 +3186,9 @@ extern "C" * @return none.
*/
void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Copies the elements of a Q31 vector.
@@ -2926,9 +3198,9 @@ extern "C" * @return none.
*/
void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Fills a constant value into a floating-point vector.
* @param[in] value input value to be filled
@@ -2937,9 +3209,9 @@ extern "C" * @return none.
*/
void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Fills a constant value into a Q7 vector.
@@ -2949,9 +3221,9 @@ extern "C" * @return none.
*/
void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Fills a constant value into a Q15 vector.
@@ -2961,9 +3233,9 @@ extern "C" * @return none.
*/
void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Fills a constant value into a Q31 vector.
@@ -2973,9 +3245,9 @@ extern "C" * @return none.
*/
void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Convolution of floating-point sequences.
@@ -2985,14 +3257,38 @@ extern "C" * @param[in] srcBLen length of the second input sequence.
* @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
* @return none.
- */
+ */
void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
/**
* @brief Convolution of Q15 sequences.
@@ -3005,11 +3301,11 @@ extern "C" */
void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
/**
* @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
@@ -3029,6 +3325,29 @@ extern "C" q15_t * pDst);
/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
* @brief Convolution of Q31 sequences.
* @param[in] *pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
@@ -3039,11 +3358,11 @@ extern "C" */
void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
/**
* @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
@@ -3056,11 +3375,35 @@ extern "C" */
void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
/**
* @brief Convolution of Q7 sequences.
@@ -3073,11 +3416,12 @@ extern "C" */
void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
/**
* @brief Partial convolution of floating-point sequences.
@@ -3092,15 +3436,41 @@ extern "C" */
arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
- /**
+
+/**
* @brief Partial convolution of Q15 sequences.
* @param[in] *pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
@@ -3113,13 +3483,13 @@ extern "C" */
arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
/**
* @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
@@ -3142,6 +3512,33 @@ extern "C" uint32_t firstIndex,
uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
/**
* @brief Partial convolution of Q31 sequences.
* @param[in] *pSrcA points to the first input sequence.
@@ -3155,13 +3552,13 @@ extern "C" */
arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
/**
@@ -3177,15 +3574,42 @@ extern "C" */
arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
- /**
+
+/**
* @brief Partial convolution of Q7 sequences.
* @param[in] *pSrcA points to the first input sequence.
* @param[in] srcALen length of the first input sequence.
@@ -3198,13 +3622,14 @@ extern "C" */
arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
/**
@@ -3257,10 +3682,10 @@ extern "C" */
void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
@@ -3276,12 +3701,12 @@ extern "C" */
arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q15 FIR decimator.
@@ -3293,10 +3718,10 @@ extern "C" */
void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
@@ -3308,10 +3733,10 @@ extern "C" */
void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
@@ -3328,12 +3753,12 @@ extern "C" */
arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR decimator.
@@ -3345,10 +3770,10 @@ extern "C" */
void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
@@ -3360,10 +3785,10 @@ extern "C" */
void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
@@ -3379,12 +3804,12 @@ extern "C" */
arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
@@ -3435,10 +3860,10 @@ extern "C" */
void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
@@ -3454,12 +3879,12 @@ extern "C" */
arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q31 FIR interpolator.
@@ -3471,10 +3896,10 @@ extern "C" */
void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q31 FIR interpolator.
@@ -3489,12 +3914,12 @@ extern "C" */
arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
/**
@@ -3507,10 +3932,10 @@ extern "C" */
void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the floating-point FIR interpolator.
@@ -3525,12 +3950,12 @@ extern "C" */
arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
/**
* @brief Instance structure for the high precision Q31 Biquad cascade filter.
@@ -3555,10 +3980,10 @@ extern "C" */
void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
@@ -3571,11 +3996,11 @@ extern "C" */
void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
@@ -3585,7 +4010,7 @@ extern "C" typedef struct
{
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
} arm_biquad_cascade_df2T_instance_f32;
@@ -3601,10 +4026,10 @@ extern "C" */
void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
@@ -3617,10 +4042,10 @@ extern "C" */
void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
@@ -3667,10 +4092,10 @@ extern "C" */
void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState);
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
/**
@@ -3682,10 +4107,10 @@ extern "C" * @return none.
*/
void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q31 FIR lattice filter.
@@ -3697,10 +4122,10 @@ extern "C" */
void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState);
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
/**
@@ -3713,10 +4138,10 @@ extern "C" */
void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the floating-point FIR lattice filter.
@@ -3728,10 +4153,10 @@ extern "C" */
void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
/**
* @brief Processing function for the floating-point FIR lattice filter.
@@ -3743,10 +4168,10 @@ extern "C" */
void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Instance structure for the Q15 IIR lattice filter.
@@ -3791,10 +4216,10 @@ extern "C" */
void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @brief Initialization function for the floating-point IIR lattice filter.
@@ -3808,12 +4233,12 @@ extern "C" */
void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t *pkCoeffs,
- float32_t *pvCoeffs,
- float32_t *pState,
- uint32_t blockSize);
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
/**
@@ -3826,10 +4251,10 @@ extern "C" */
void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
@@ -3844,12 +4269,12 @@ extern "C" */
void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t *pkCoeffs,
- q31_t *pvCoeffs,
- q31_t *pState,
- uint32_t blockSize);
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
/**
@@ -3862,10 +4287,10 @@ extern "C" */
void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
@@ -3880,12 +4305,12 @@ extern "C" */
void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t *pkCoeffs,
- q15_t *pvCoeffs,
- q15_t *pState,
- uint32_t blockSize);
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
/**
* @brief Instance structure for the floating-point LMS filter.
@@ -3911,12 +4336,12 @@ extern "C" */
void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
/**
* @brief Initialization function for floating-point LMS filter.
@@ -3930,12 +4355,12 @@ extern "C" */
void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
/**
* @brief Instance structure for the Q15 LMS filter.
@@ -3964,13 +4389,13 @@ extern "C" */
void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
/**
* @brief Processing function for Q15 LMS filter.
@@ -3984,12 +4409,12 @@ extern "C" */
void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
/**
@@ -4018,12 +4443,12 @@ extern "C" */
void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
/**
* @brief Initialization function for Q31 LMS filter.
@@ -4038,13 +4463,13 @@ extern "C" */
void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t *pCoeffs,
- q31_t *pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
/**
* @brief Instance structure for the floating-point normalized LMS filter.
@@ -4052,7 +4477,7 @@ extern "C" typedef struct
{
- uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
float32_t mu; /**< step size that control filter coefficient updates. */
@@ -4072,12 +4497,12 @@ extern "C" */
void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
/**
* @brief Initialization function for floating-point normalized LMS filter.
@@ -4091,12 +4516,12 @@ extern "C" */
void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
/**
@@ -4126,12 +4551,12 @@ extern "C" */
void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
/**
* @brief Initialization function for Q31 normalized LMS filter.
@@ -4146,13 +4571,13 @@ extern "C" */
void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
/**
* @brief Instance structure for the Q15 normalized LMS filter.
@@ -4182,12 +4607,12 @@ extern "C" */
void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
/**
@@ -4203,13 +4628,13 @@ extern "C" */
void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
/**
* @brief Correlation of floating-point sequences.
@@ -4222,11 +4647,31 @@ extern "C" */
void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
/**
* @brief Correlation of Q15 sequences.
@@ -4239,11 +4684,11 @@ extern "C" */
void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
/**
* @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
@@ -4262,6 +4707,27 @@ extern "C" uint32_t srcBLen,
q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
/**
* @brief Correlation of Q31 sequences.
* @param[in] *pSrcA points to the first input sequence.
@@ -4273,11 +4739,11 @@ extern "C" */
void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
/**
* @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
@@ -4290,11 +4756,35 @@ extern "C" */
void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
/**
* @brief Correlation of Q7 sequences.
@@ -4307,11 +4797,12 @@ extern "C" */
void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
/**
* @brief Instance structure for the floating-point sparse FIR filter.
@@ -4379,11 +4870,11 @@ extern "C" */
void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
/**
* @brief Initialization function for the floating-point sparse FIR filter.
@@ -4398,13 +4889,13 @@ extern "C" */
void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q31 sparse FIR filter.
@@ -4417,11 +4908,11 @@ extern "C" */
void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q31 sparse FIR filter.
@@ -4436,13 +4927,13 @@ extern "C" */
void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q15 sparse FIR filter.
@@ -4456,12 +4947,12 @@ extern "C" */
void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
/**
@@ -4477,13 +4968,13 @@ extern "C" */
void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
/**
* @brief Processing function for the Q7 sparse FIR filter.
@@ -4497,12 +4988,12 @@ extern "C" */
void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
/**
* @brief Initialization function for the Q7 sparse FIR filter.
@@ -4517,13 +5008,13 @@ extern "C" */
void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t *pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
/*
@@ -4535,9 +5026,9 @@ extern "C" */
void arm_sin_cos_f32(
- float32_t theta,
- float32_t *pSinVal,
- float32_t *pCcosVal);
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
/*
* @brief Q31 sin_cos function.
@@ -4548,9 +5039,9 @@ extern "C" */
void arm_sin_cos_q31(
- q31_t theta,
- q31_t *pSinVal,
- q31_t *pCosVal);
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
/**
@@ -4562,9 +5053,9 @@ extern "C" */
void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q31 complex conjugate.
@@ -4575,9 +5066,9 @@ extern "C" */
void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q15 complex conjugate.
@@ -4588,9 +5079,9 @@ extern "C" */
void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
@@ -4603,9 +5094,9 @@ extern "C" */
void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q31 complex magnitude squared
@@ -4616,9 +5107,9 @@ extern "C" */
void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q15 complex magnitude squared
@@ -4629,9 +5120,9 @@ extern "C" */
void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
/**
@@ -4708,9 +5199,9 @@ extern "C" */
- static __INLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
+ __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
{
float32_t out;
@@ -4743,12 +5234,12 @@ extern "C" * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
*/
- static __INLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
+ __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
{
q63_t acc;
- q31_t out;
+ q31_t out;
/* acc = A0 * x[n] */
acc = (q63_t) S->A0 * in;
@@ -4791,39 +5282,39 @@ extern "C" * Lastly, the accumulator is saturated to yield a result in 1.15 format.
*/
- static __INLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
+ __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
{
q63_t acc;
q15_t out;
/* Implementation of PID controller */
- #ifdef ARM_MATH_CM0
+#ifdef ARM_MATH_CM0
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0 )* in ;
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+#else
- #else
-
/* acc = A0 * x[n] */
acc = (q31_t) __SMUAD(S->A0, in);
-
- #endif
- #ifdef ARM_MATH_CM0
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0] ;
- acc += (q31_t) S->A2 * S->state[1] ;
+#endif
+
+#ifdef ARM_MATH_CM0
- #else
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+
+#else
/* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
+ acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc);
- #endif
+#endif
/* acc += y[n-1] */
acc += (q31_t) S->state[2] << 15;
@@ -4840,7 +5331,7 @@ extern "C" return (out);
}
-
+
/**
* @} end of PID group
*/
@@ -4855,11 +5346,11 @@ extern "C" */
arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
-
-
/**
* @ingroup groupController
*/
@@ -4902,17 +5393,18 @@ extern "C" * @return none.
*/
- static __INLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
+ __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
{
/* Calculate pIalpha using the equation, pIalpha = Ia */
*pIalpha = Ia;
/* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
}
@@ -4931,11 +5423,11 @@ extern "C" * There is saturation on the addition, hence there is no risk of overflow.
*/
- static __INLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
+ __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
@@ -4964,12 +5456,12 @@ extern "C" * @return none.
*/
void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
-
/**
* @ingroup groupController
@@ -5006,11 +5498,11 @@ extern "C" */
- static __INLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
+ __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
{
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
*pIa = Ialpha;
@@ -5035,11 +5527,11 @@ extern "C" * There is saturation on the subtraction, hence there is no risk of overflow.
*/
- static __INLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
+ __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
@@ -5069,11 +5561,11 @@ extern "C" * @return none.
*/
void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
-
/**
* @ingroup groupController
@@ -5122,13 +5614,13 @@ extern "C" *
*/
- static __INLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
+ __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
{
/* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
*pId = Ialpha * cosVal + Ibeta * sinVal;
@@ -5156,13 +5648,13 @@ extern "C" */
- static __INLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
+ __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
q31_t product3, product4; /* Temporary variables used to store intermediate results */
@@ -5199,11 +5691,11 @@ extern "C" * @return none.
*/
void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
-
/**
* @ingroup groupController
*/
@@ -5241,13 +5733,13 @@ extern "C" * @return none.
*/
- static __INLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
+ __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
{
/* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
*pIalpha = Id * cosVal - Iq * sinVal;
@@ -5276,13 +5768,13 @@ extern "C" */
- static __INLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
+ __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
{
q31_t product1, product2; /* Temporary variables used to store intermediate results */
q31_t product3, product4; /* Temporary variables used to store intermediate results */
@@ -5312,7 +5804,7 @@ extern "C" * @} end of Inverse park group
*/
-
+
/**
* @brief Converts the elements of the Q31 vector to floating-point vector.
* @param[in] *pSrc is input pointer
@@ -5321,9 +5813,9 @@ extern "C" * @return none.
*/
void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
* @ingroup groupInterpolation
@@ -5374,48 +5866,48 @@ extern "C" *
*/
- static __INLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
+ __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
{
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (x - S->x1) / xSpacing;
-
- if(i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if(i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues-1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i +1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));
-
- }
-
- /* returns output value */
- return (y);
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (x - S->x1) / xSpacing;
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if(i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
}
/**
@@ -5433,48 +5925,50 @@ extern "C" */
- static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
- q31_t x, uint32_t nValues)
+ __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
{
- q31_t y; /* output */
+ q31_t y; /* output */
q31_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
+ int32_t index; /* Index to read nearest output values */
+
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
index = ((x & 0xFFF00000) >> 20);
- if(index >= (nValues - 1))
- {
- return(pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return(pYData[0]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1u);
-
- }
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
}
@@ -5493,45 +5987,48 @@ extern "C" */
- static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
+ __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
{
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
- index = ((x & 0xFFF00000) >> 20u);
-
- if(index >= (nValues - 1))
- {
- return(pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return(pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (y >> 20);
- }
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
}
@@ -5550,13 +6047,16 @@ extern "C" */
- static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)
+ __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
{
- q31_t y; /* output */
+ q31_t y; /* output */
q7_t y0, y1; /* Nearest output values */
q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
+ int32_t index; /* Index to read nearest output values */
+
/* Input is in 12.20 format */
/* 12 bits for the table index */
/* Index value calculation */
@@ -5564,34 +6064,34 @@ extern "C" if(index >= (nValues - 1))
- {
- return(pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return(pYData[0]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (y >> 20u);
-
- }
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
}
/**
@@ -5605,7 +6105,7 @@ extern "C" */
float32_t arm_sin_f32(
- float32_t x);
+ float32_t x);
/**
* @brief Fast approximation to the trigonometric sine function for Q31 data.
@@ -5614,7 +6114,7 @@ extern "C" */
q31_t arm_sin_q31(
- q31_t x);
+ q31_t x);
/**
* @brief Fast approximation to the trigonometric sine function for Q15 data.
@@ -5623,7 +6123,7 @@ extern "C" */
q15_t arm_sin_q15(
- q15_t x);
+ q15_t x);
/**
* @brief Fast approximation to the trigonometric cosine function for floating-point data.
@@ -5632,7 +6132,7 @@ extern "C" */
float32_t arm_cos_f32(
- float32_t x);
+ float32_t x);
/**
* @brief Fast approximation to the trigonometric cosine function for Q31 data.
@@ -5641,7 +6141,7 @@ extern "C" */
q31_t arm_cos_q31(
- q31_t x);
+ q31_t x);
/**
* @brief Fast approximation to the trigonometric cosine function for Q15 data.
@@ -5650,7 +6150,7 @@ extern "C" */
q15_t arm_cos_q15(
- q15_t x);
+ q15_t x);
/**
@@ -5692,26 +6192,29 @@ extern "C" * <code>in</code> is negative value and returns zero output for negative values.
*/
- static __INLINE arm_status arm_sqrt_f32(
- float32_t in, float32_t *pOut)
+ __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
{
- if(in > 0)
- {
+ if(in > 0)
+ {
-// #if __FPU_USED
+// #if __FPU_USED
#if (__FPU_USED == 1) && defined ( __CC_ARM )
- *pOut = __sqrtf(in);
- #else
- *pOut = sqrtf(in);
- #endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
+ *pOut = __sqrtf(in);
+ #elif (__FPU_USED == 1) && defined ( __TMS_740 )
+ *pOut = __builtin_sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
}
@@ -5724,7 +6227,8 @@ extern "C" * <code>in</code> is negative value and returns zero output for negative values.
*/
arm_status arm_sqrt_q31(
- q31_t in, q31_t *pOut);
+ q31_t in,
+ q31_t * pOut);
/**
* @brief Q15 square root function.
@@ -5734,7 +6238,8 @@ extern "C" * <code>in</code> is negative value and returns zero output for negative values.
*/
arm_status arm_sqrt_q15(
- q15_t in, q15_t *pOut);
+ q15_t in,
+ q15_t * pOut);
/**
* @} end of SQRT group
@@ -5749,14 +6254,14 @@ extern "C" * @brief floating-point Circular write function.
*/
- static __INLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
+ __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
{
uint32_t i = 0u;
int32_t wOffset;
@@ -5769,21 +6274,21 @@ extern "C" i = blockSize;
while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
- /* Update the input pointer */
- src += srcInc;
+ /* Update the input pointer */
+ src += srcInc;
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
- /* Decrement the loop counter */
- i--;
- }
+ /* Decrement the loop counter */
+ i--;
+ }
/* Update the index pointer */
*writeOffset = wOffset;
@@ -5794,16 +6299,16 @@ extern "C" /**
* @brief floating-point Circular Read function.
*/
- static __INLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
+ __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
{
uint32_t i = 0u;
int32_t rOffset, dst_end;
@@ -5817,30 +6322,30 @@ extern "C" i = blockSize;
while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
- if(dst == (int32_t *) dst_end)
- {
- dst = dst_base;
- }
+ /* Update the input pointer */
+ dst += dstInc;
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
- if(rOffset >= L)
- {
- rOffset -= L;
- }
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
- /* Decrement the loop counter */
- i--;
+ if(rOffset >= L)
+ {
+ rOffset -= L;
}
+ /* Decrement the loop counter */
+ i--;
+ }
+
/* Update the index pointer */
*readOffset = rOffset;
}
@@ -5849,14 +6354,14 @@ extern "C" * @brief Q15 Circular write function.
*/
- static __INLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
+ __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
{
uint32_t i = 0u;
int32_t wOffset;
@@ -5869,21 +6374,21 @@ extern "C" i = blockSize;
while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
- /* Update the input pointer */
- src += srcInc;
+ /* Update the input pointer */
+ src += srcInc;
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
- /* Decrement the loop counter */
- i--;
- }
+ /* Decrement the loop counter */
+ i--;
+ }
/* Update the index pointer */
*writeOffset = wOffset;
@@ -5894,16 +6399,16 @@ extern "C" /**
* @brief Q15 Circular Read function.
*/
- static __INLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
+ __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
{
uint32_t i = 0;
int32_t rOffset, dst_end;
@@ -5918,30 +6423,30 @@ extern "C" i = blockSize;
while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
- if(dst == (q15_t *) dst_end)
- {
- dst = dst_base;
- }
+ /* Update the input pointer */
+ dst += dstInc;
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
- if(rOffset >= L)
- {
- rOffset -= L;
- }
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
- /* Decrement the loop counter */
- i--;
+ if(rOffset >= L)
+ {
+ rOffset -= L;
}
+ /* Decrement the loop counter */
+ i--;
+ }
+
/* Update the index pointer */
*readOffset = rOffset;
}
@@ -5951,14 +6456,14 @@ extern "C" * @brief Q7 Circular write function.
*/
- static __INLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
+ __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
{
uint32_t i = 0u;
int32_t wOffset;
@@ -5971,21 +6476,21 @@ extern "C" i = blockSize;
while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
- /* Update the input pointer */
- src += srcInc;
+ /* Update the input pointer */
+ src += srcInc;
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
- /* Decrement the loop counter */
- i--;
- }
+ /* Decrement the loop counter */
+ i--;
+ }
/* Update the index pointer */
*writeOffset = wOffset;
@@ -5996,16 +6501,16 @@ extern "C" /**
* @brief Q7 Circular Read function.
*/
- static __INLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
+ __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
{
uint32_t i = 0;
int32_t rOffset, dst_end;
@@ -6020,30 +6525,30 @@ extern "C" i = blockSize;
while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
- if(dst == (q7_t *) dst_end)
- {
- dst = dst_base;
- }
+ /* Update the input pointer */
+ dst += dstInc;
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
- if(rOffset >= L)
- {
- rOffset -= L;
- }
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
- /* Decrement the loop counter */
- i--;
+ if(rOffset >= L)
+ {
+ rOffset -= L;
}
+ /* Decrement the loop counter */
+ i--;
+ }
+
/* Update the index pointer */
*readOffset = rOffset;
}
@@ -6058,9 +6563,9 @@ extern "C" */
void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
/**
* @brief Sum of the squares of the elements of a floating-point vector.
@@ -6071,9 +6576,9 @@ extern "C" */
void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
/**
* @brief Sum of the squares of the elements of a Q15 vector.
@@ -6084,9 +6589,9 @@ extern "C" */
void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
/**
* @brief Sum of the squares of the elements of a Q7 vector.
@@ -6097,9 +6602,9 @@ extern "C" */
void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
/**
* @brief Mean value of a Q7 vector.
@@ -6110,9 +6615,9 @@ extern "C" */
void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
/**
* @brief Mean value of a Q15 vector.
@@ -6122,9 +6627,9 @@ extern "C" * @return none.
*/
void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
/**
* @brief Mean value of a Q31 vector.
@@ -6134,9 +6639,9 @@ extern "C" * @return none.
*/
void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
/**
* @brief Mean value of a floating-point vector.
@@ -6146,9 +6651,9 @@ extern "C" * @return none.
*/
void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
/**
* @brief Variance of the elements of a floating-point vector.
@@ -6159,9 +6664,9 @@ extern "C" */
void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
/**
* @brief Variance of the elements of a Q31 vector.
@@ -6172,9 +6677,9 @@ extern "C" */
void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
/**
* @brief Variance of the elements of a Q15 vector.
@@ -6185,9 +6690,9 @@ extern "C" */
void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
/**
* @brief Root Mean Square of the elements of a floating-point vector.
@@ -6198,9 +6703,9 @@ extern "C" */
void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
/**
* @brief Root Mean Square of the elements of a Q31 vector.
@@ -6211,9 +6716,9 @@ extern "C" */
void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
/**
* @brief Root Mean Square of the elements of a Q15 vector.
@@ -6224,9 +6729,9 @@ extern "C" */
void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
/**
* @brief Standard deviation of the elements of a floating-point vector.
@@ -6237,9 +6742,9 @@ extern "C" */
void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
/**
* @brief Standard deviation of the elements of a Q31 vector.
@@ -6250,9 +6755,9 @@ extern "C" */
void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
/**
* @brief Standard deviation of the elements of a Q15 vector.
@@ -6263,9 +6768,9 @@ extern "C" */
void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
/**
* @brief Floating-point complex magnitude
@@ -6276,9 +6781,9 @@ extern "C" */
void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q31 complex magnitude
@@ -6289,9 +6794,9 @@ extern "C" */
void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q15 complex magnitude
@@ -6302,9 +6807,9 @@ extern "C" */
void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q15 complex dot product
@@ -6317,11 +6822,11 @@ extern "C" */
void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
/**
* @brief Q31 complex dot product
@@ -6334,11 +6839,11 @@ extern "C" */
void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
/**
* @brief Floating-point complex dot product
@@ -6351,11 +6856,11 @@ extern "C" */
void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
/**
* @brief Q15 complex-by-real multiplication
@@ -6367,10 +6872,10 @@ extern "C" */
void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
/**
* @brief Q31 complex-by-real multiplication
@@ -6382,10 +6887,10 @@ extern "C" */
void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
/**
* @brief Floating-point complex-by-real multiplication
@@ -6397,10 +6902,10 @@ extern "C" */
void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
/**
* @brief Minimum value of a Q7 vector.
@@ -6412,10 +6917,10 @@ extern "C" */
void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
/**
* @brief Minimum value of a Q15 vector.
@@ -6427,10 +6932,10 @@ extern "C" */
void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
/**
* @brief Minimum value of a Q31 vector.
@@ -6441,10 +6946,10 @@ extern "C" * @return none.
*/
void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
/**
* @brief Minimum value of a floating-point vector.
@@ -6456,10 +6961,10 @@ extern "C" */
void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
/**
* @brief Maximum value of a Q7 vector.
@@ -6471,10 +6976,10 @@ extern "C" */
void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
/**
* @brief Maximum value of a Q15 vector.
@@ -6486,10 +6991,10 @@ extern "C" */
void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
/**
* @brief Maximum value of a Q31 vector.
@@ -6501,10 +7006,10 @@ extern "C" */
void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
/**
* @brief Maximum value of a floating-point vector.
@@ -6516,10 +7021,10 @@ extern "C" */
void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
/**
* @brief Q15 complex-by-complex multiplication
@@ -6531,10 +7036,10 @@ extern "C" */
void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
/**
* @brief Q31 complex-by-complex multiplication
@@ -6546,10 +7051,10 @@ extern "C" */
void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
/**
* @brief Floating-point complex-by-complex multiplication
@@ -6561,10 +7066,10 @@ extern "C" */
void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
/**
* @brief Converts the elements of the floating-point vector to Q31 vector.
@@ -6574,9 +7079,9 @@ extern "C" * @return none.
*/
void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
* @brief Converts the elements of the floating-point vector to Q15 vector.
@@ -6586,9 +7091,9 @@ extern "C" * @return none
*/
void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Converts the elements of the floating-point vector to Q7 vector.
@@ -6598,9 +7103,9 @@ extern "C" * @return none
*/
void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
@@ -6611,9 +7116,9 @@ extern "C" * @return none.
*/
void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
/**
* @brief Converts the elements of the Q31 vector to Q7 vector.
@@ -6623,9 +7128,9 @@ extern "C" * @return none.
*/
void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
* @brief Converts the elements of the Q15 vector to floating-point vector.
@@ -6635,9 +7140,9 @@ extern "C" * @return none.
*/
void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
/**
@@ -6648,9 +7153,9 @@ extern "C" * @return none.
*/
void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
/**
@@ -6661,9 +7166,9 @@ extern "C" * @return none.
*/
void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
/**
@@ -6736,11 +7241,11 @@ extern "C" * @return out interpolated value.
*/
-
- static __INLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
+
+ __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
{
float32_t out;
float32_t f00, f01, f10, f11;
@@ -6752,15 +7257,16 @@ extern "C" xIndex = (int32_t) X;
yIndex = (int32_t) Y;
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))
- {
- return(0);
- }
-
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
/* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex-1) * S->numCols ;
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
/* Read two nearest points in X-direction */
@@ -6768,7 +7274,7 @@ extern "C" f01 = pData[index + 1];
/* Calculation of index for two nearest points in Y-direction */
- index = (xIndex-1) + (yIndex) * S->numCols;
+ index = (xIndex - 1) + (yIndex) * S->numCols;
/* Read two nearest points in Y-direction */
@@ -6788,9 +7294,9 @@ extern "C" ydiff = Y - yIndex;
/* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
- /* return to application */
+ /* return to application */
return (out);
}
@@ -6804,16 +7310,16 @@ extern "C" * @return out interpolated value.
*/
- static __INLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
+ __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
{
q31_t out; /* Temporary output */
q31_t acc = 0; /* output */
q31_t xfract, yfract; /* X, Y fractional parts */
q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
+ int32_t rI, cI; /* Row and column indices */
q31_t *pYData = S->pData; /* pointer to output table values */
uint32_t nCols = S->numCols; /* num of rows */
@@ -6828,12 +7334,12 @@ extern "C" /* Index value calculation */
cI = ((Y & 0xFFF00000) >> 20u);
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
- {
- return(0);
- }
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
/* 20 bits for the fractional part */
/* shift left xfract by 11 to keep 1.31 format */
@@ -6880,16 +7386,16 @@ extern "C" * @return out interpolated value.
*/
- static __INLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
+ __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
{
q63_t acc = 0; /* output */
q31_t out; /* Temporary output */
q15_t x1, x2, y1, y2; /* Nearest output values */
q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
+ int32_t rI, cI; /* Row and column indices */
q15_t *pYData = S->pData; /* pointer to output table values */
uint32_t nCols = S->numCols; /* num of rows */
@@ -6903,12 +7409,12 @@ extern "C" /* Index value calculation */
cI = ((Y & 0xFFF00000) >> 20);
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
- {
- return(0);
- }
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
/* 20 bits for the fractional part */
/* xfract should be in 12.20 format */
@@ -6960,16 +7466,16 @@ extern "C" * @return out interpolated value.
*/
- static __INLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
+ __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
{
q63_t acc = 0; /* output */
q31_t out; /* Temporary output */
q31_t xfract, yfract; /* X, Y fractional parts */
q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
+ int32_t rI, cI; /* Row and column indices */
q7_t *pYData = S->pData; /* pointer to output table values */
uint32_t nCols = S->numCols; /* num of rows */
@@ -6983,12 +7489,12 @@ extern "C" /* Index value calculation */
cI = ((Y & 0xFFF00000) >> 20);
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
- {
- return(0);
- }
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
/* 20 bits for the fractional part */
/* xfract should be in 12.20 format */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h index edd522173..0d7cfd85e 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm0.h @@ -1,11 +1,11 @@ /**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V2.10
- * @date 19. July 2011
+ * @version V3.01
+ * @date 13. March 2012
*
* @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
@@ -31,79 +31,67 @@ #ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
-/** \mainpage CMSIS Cortex-M0
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
- This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
- It consists of:
-
- - Cortex-M Core Register Definitions
- - Cortex-M functions
- - Cortex-M instructions
-
- The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
- access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
- CMSIS violates following MISRA-C2004 Rules:
-
- - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
-
- - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core
- - Cortex-M core Revision Number
+/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-#define __CORTEX_M (0x00) /*!< Cortex core */
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
#endif
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -115,12 +103,14 @@ #endif
#elif defined ( __TASKING__ )
- /* add preprocessor checks */
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
-#include <stdint.h> /*!< standard types definitions */
-#include "core_cmInstr.h" /*!< Core Instruction Access */
-#include "core_cmFunc.h" /*!< Core Function Access */
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
@@ -148,32 +138,40 @@ #endif
/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
+ #define __I volatile /*!< Defines 'read only' permissions */
#else
- #define __I volatile const /*!< defines 'read only' permissions */
+ #define __I volatile const /*!< Defines 'read only' permissions */
#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
*/
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE CMSIS Core
- Type definitions for the Cortex-M Core Registers
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
@{
*/
@@ -256,9 +254,9 @@ typedef union /*@} end of group CMSIS_CORE */
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC CMSIS NVIC
- Type definitions for the Cortex-M NVIC Registers
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
@{
*/
@@ -282,8 +280,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB CMSIS SCB
- Type definitions for the Cortex-M System Control Block Registers
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
@{
*/
@@ -387,8 +385,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick CMSIS SysTick
- Type definitions for the Cortex-M System Timer Registers
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
@{
*/
@@ -437,21 +435,23 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug CMSIS Core Debug
- Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
- and not via processor. Therefore they are not covered by the Cortex-M0 header file.
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
@@ -467,20 +467,21 @@ typedef struct /*******************************************************************************
* Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
- @{
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
@@ -492,12 +493,11 @@ typedef struct /** \brief Enable External Interrupt
- This function enables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Number of the external interrupt to enable
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@@ -505,12 +505,11 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) /** \brief Disable External Interrupt
- This function disables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Number of the external interrupt to disable
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@@ -518,14 +517,15 @@ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) /** \brief Get Pending Interrupt
- This function reads the pending register in the NVIC and returns the pending bit
+ The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
- \param [in] IRQn Number of the interrupt for get pending
- \return 0 Interrupt status is not pending
- \return 1 Interrupt status is pending
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
*/
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
@@ -533,12 +533,11 @@ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) /** \brief Set Pending Interrupt
- This function sets the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
+ The function sets the pending bit of an external interrupt.
- \param [in] IRQn Number of the interrupt for set pending
+ \param [in] IRQn Interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@@ -546,12 +545,11 @@ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) /** \brief Clear Pending Interrupt
- This function clears the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
+ The function clears the pending bit of an external interrupt.
- \param [in] IRQn Number of the interrupt for clear pending
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
@@ -559,16 +557,14 @@ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** \brief Set Interrupt Priority
- This function sets the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
+ The function sets the priority of an interrupt.
- Note: The priority cannot be set for every core interrupt.
+ \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Number of the interrupt for set priority
- \param [in] priority Priority to set
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
*/
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
@@ -581,17 +577,16 @@ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) /** \brief Get Interrupt Priority
- This function reads the priority for the specified interrupt. The interrupt
+ The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
- The returned priority value is automatically aligned to the implemented
- priority bits of the microcontroller.
- \param [in] IRQn Number of the interrupt for get priority
- \return Interrupt Priority
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
*/
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
@@ -603,9 +598,9 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) /** \brief System Reset
- This function initiate a system reset request to reset the MCU.
+ The function initiates a system reset request to reset the MCU.
*/
-static __INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
@@ -621,7 +616,8 @@ static __INLINE void NVIC_SystemReset(void) /* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
@{
*/
@@ -629,19 +625,25 @@ static __INLINE void NVIC_SystemReset(void) /** \brief System Tick Configuration
- This function initialises the system tick timer and its interrupt and start the system tick timer.
- Counter is in free running mode to generate periodical interrupts.
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
- \param [in] ticks Number of ticks between two interrupts
- \return 0 Function succeeded
- \return 1 Function failed
*/
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h new file mode 100755 index 000000000..cf92fb7fe --- /dev/null +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm0plus.h @@ -0,0 +1,778 @@ +/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h index 0ced2caa5..db1716ad9 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm3.h @@ -1,11 +1,11 @@ /**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V2.11
- * @date 08. September 2011
+ * @version V3.01
+ * @date 22. March 2012
*
* @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
@@ -31,96 +31,95 @@ #ifndef __CORE_CM3_H_GENERIC
#define __CORE_CM3_H_GENERIC
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
-/** \mainpage CMSIS Cortex-M3
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
- This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
- It consists of:
-
- - Cortex-M Core Register Definitions
- - Cortex-M functions
- - Cortex-M instructions
-
- The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
- access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
- CMSIS violates following MISRA-C2004 Rules:
-
- - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
-
- - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core
- - Cortex-M core Revision Number
+/** \ingroup Cortex_M3
@{
*/
/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-#define __CORTEX_M (0x03) /*!< Cortex core */
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
#endif
-
-#define __FPU_USED 0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
- /* add preprocessor checks */
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
-#include <stdint.h> /*!< standard types definitions */
-#include "core_cmInstr.h" /*!< Core Instruction Access */
-#include "core_cmFunc.h" /*!< Core Function Access */
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM3_H_GENERIC */
@@ -153,22 +152,27 @@ #endif
/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
+ #define __I volatile /*!< Defines 'read only' permissions */
#else
- #define __I volatile const /*!< defines 'read only' permissions */
+ #define __I volatile const /*!< Defines 'read only' permissions */
#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M3 */
/*******************************************************************************
* Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
@@ -176,11 +180,14 @@ - Core SysTick Register
- Core Debug Register
- Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
*/
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE CMSIS Core
- Type definitions for the Cortex-M Core Registers
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
@{
*/
@@ -263,9 +270,9 @@ typedef union /*@} end of group CMSIS_CORE */
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC CMSIS NVIC
- Type definitions for the Cortex-M NVIC Registers
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
@{
*/
@@ -296,8 +303,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB CMSIS SCB
- Type definitions for the Cortex-M System Control Block Registers
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
@{
*/
@@ -521,8 +528,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
- Type definitions for the Cortex-M System Control and ID Register not in the SCB
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
@@ -558,8 +565,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick CMSIS SysTick
- Type definitions for the Cortex-M System Timer Registers
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
@{
*/
@@ -608,8 +615,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM CMSIS ITM
- Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
@@ -629,47 +636,387 @@ typedef struct __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU CMSIS MPU
- Type definitions for the Cortex-M Memory Protection Unit (MPU)
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
@@ -728,6 +1075,24 @@ typedef struct #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
@@ -742,8 +1107,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug CMSIS Core Debug
- Type definitions for the Cortex-M Core Debug Registers
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
@{
*/
@@ -844,13 +1209,17 @@ typedef struct /*@} end of group CMSIS_CoreDebug */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
@@ -861,6 +1230,8 @@ typedef struct #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1)
@@ -874,34 +1245,35 @@ typedef struct /*******************************************************************************
* Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
- @{
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
*/
/** \brief Set Priority Grouping
- This function sets the priority grouping field using the required unlock sequence.
+ The function sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field
+ \param [in] PriorityGroup Priority grouping field.
*/
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
@@ -917,12 +1289,11 @@ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** \brief Get Priority Grouping
- This function gets the priority grouping from NVIC Interrupt Controller.
- Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
@@ -930,12 +1301,11 @@ static __INLINE uint32_t NVIC_GetPriorityGrouping(void) /** \brief Enable External Interrupt
- This function enables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Number of the external interrupt to enable
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
@@ -943,12 +1313,11 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) /** \brief Disable External Interrupt
- This function disables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Number of the external interrupt to disable
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
@@ -956,14 +1325,15 @@ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) /** \brief Get Pending Interrupt
- This function reads the pending register in the NVIC and returns the pending bit
+ The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
- \param [in] IRQn Number of the interrupt for get pending
- \return 0 Interrupt status is not pending
- \return 1 Interrupt status is pending
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
*/
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
@@ -971,12 +1341,11 @@ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) /** \brief Set Pending Interrupt
- This function sets the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
+ The function sets the pending bit of an external interrupt.
- \param [in] IRQn Number of the interrupt for set pending
+ \param [in] IRQn Interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
@@ -984,12 +1353,11 @@ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) /** \brief Clear Pending Interrupt
- This function clears the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
+ The function clears the pending bit of an external interrupt.
- \param [in] IRQn Number of the interrupt for clear pending
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
@@ -997,12 +1365,14 @@ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** \brief Get Active Interrupt
- This function reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Number of the interrupt for get active
- \return 0 Interrupt status is not active
- \return 1 Interrupt status is active
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
*/
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
@@ -1010,16 +1380,14 @@ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) /** \brief Set Interrupt Priority
- This function sets the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
+ The function sets the priority of an interrupt.
- Note: The priority cannot be set for every core interrupt.
+ \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Number of the interrupt for set priority
- \param [in] priority Priority to set
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
*/
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
@@ -1030,17 +1398,16 @@ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) /** \brief Get Interrupt Priority
- This function reads the priority for the specified interrupt. The interrupt
+ The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
- The returned priority value is automatically aligned to the implemented
- priority bits of the microcontroller.
- \param [in] IRQn Number of the interrupt for get priority
- \return Interrupt Priority
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
*/
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
@@ -1052,19 +1419,17 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) /** \brief Encode Priority
- This function encodes the priority for an interrupt with the given priority group,
- preemptive priority value and sub priority value.
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
- The returned priority value can be used for NVIC_SetPriority(...) function
-
- \param [in] PriorityGroup Used priority group
- \param [in] PreemptPriority Preemptive priority value (starting from 0)
- \param [in] SubPriority Sub priority value (starting from 0)
- \return Encoded priority for the interrupt
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1082,19 +1447,17 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P /** \brief Decode Priority
- This function decodes an interrupt priority value with the given priority group to
- preemptive priority value and sub priority value.
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- The priority value can be retrieved with NVIC_GetPriority(...) function
-
- \param [in] Priority Priority value
- \param [in] PriorityGroup Used priority group
- \param [out] pPreemptPriority Preemptive priority value (starting from 0)
- \param [out] pSubPriority Sub priority value (starting from 0)
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
*/
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1110,9 +1473,9 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr /** \brief System Reset
- This function initiate a system reset request to reset the MCU.
+ The function initiates a system reset request to reset the MCU.
*/
-static __INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
@@ -1129,7 +1492,8 @@ static __INLINE void NVIC_SystemReset(void) /* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
@{
*/
@@ -1137,19 +1501,25 @@ static __INLINE void NVIC_SystemReset(void) /** \brief System Tick Configuration
- This function initialises the system tick timer and its interrupt and start the system tick timer.
- Counter is in free running mode to generate periodical interrupts.
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
- \param [in] ticks Number of ticks between two interrupts
- \return 0 Function succeeded
- \return 1 Function failed
*/
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
@@ -1165,27 +1535,28 @@ static __INLINE uint32_t SysTick_Config(uint32_t ticks) /* ##################################### Debug In/Output function ########################################### */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
@{
*/
-extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** \brief ITM Send Character
- This function transmits a character via the ITM channel 0.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
- \param [in] ch Character to transmit
- \return Character to transmit
+ \returns Character to transmit.
*/
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
@@ -1197,14 +1568,12 @@ static __INLINE uint32_t ITM_SendChar (uint32_t ch) /** \brief ITM Receive Character
- This function inputs a character via external variable ITM_RxBuffer.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character
- \return -1 No character received
+ \return Received character.
+ \return -1 No character pending.
*/
-static __INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
@@ -1218,13 +1587,12 @@ static __INLINE int32_t ITM_ReceiveChar (void) { /** \brief ITM Check Character
- This function checks external variable ITM_RxBuffer whether a character is available or not.
- It returns '1' if a character is available and '0' if no character is available.
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available
- \return 1 Character available
+ \return 0 No character available.
+ \return 1 Character available.
*/
-static __INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h index 76bf8292a..024302e4a 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm4.h @@ -1,11 +1,11 @@ /**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V2.10
- * @date 19. July 2011
+ * @version V3.01
+ * @date 22. March 2012
*
* @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
@@ -31,74 +31,64 @@ #ifndef __CORE_CM4_H_GENERIC
#define __CORE_CM4_H_GENERIC
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
-/** \mainpage CMSIS Cortex-M4
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
- This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
- It consists of:
-
- - Cortex-M Core Register Definitions
- - Cortex-M functions
- - Cortex-M instructions
- - Cortex-M SIMD instructions
-
- The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
- access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
- CMSIS violates following MISRA-C2004 Rules:
-
- - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
-
- - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core
- - Cortex-M core Revision Number
+/** \ingroup Cortex_M4
@{
*/
/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-#define __CORTEX_M (0x04) /*!< Cortex core */
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
#endif
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#if (__FPU_PRESENT == 1)
@@ -123,6 +113,18 @@ #define __FPU_USED 0
#endif
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if (__FPU_PRESENT == 1)
@@ -136,14 +138,22 @@ #endif
#elif defined ( __TASKING__ )
- /* add preprocessor checks to define __FPU_USED */
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
#define __FPU_USED 0
+ #endif
#endif
-#include <stdint.h> /*!< standard types definitions */
-#include <core_cmInstr.h> /*!< Core Instruction Access */
-#include <core_cmFunc.h> /*!< Core Function Access */
-#include <core_cm4_simd.h> /*!< Compiler specific SIMD Intrinsics */
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
#endif /* __CORE_CM4_H_GENERIC */
@@ -181,22 +191,27 @@ #endif
/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
+ #define __I volatile /*!< Defines 'read only' permissions */
#else
- #define __I volatile const /*!< defines 'read only' permissions */
+ #define __I volatile const /*!< Defines 'read only' permissions */
#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
-/*@} end of group CMSIS_core_definitions */
+/*@} end of group Cortex_M4 */
/*******************************************************************************
* Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
@@ -205,11 +220,14 @@ - Core Debug Register
- Core MPU Register
- Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
*/
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE CMSIS Core
- Type definitions for the Cortex-M Core Registers
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
@{
*/
@@ -292,9 +310,9 @@ typedef union /*@} end of group CMSIS_CORE */
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC CMSIS NVIC
- Type definitions for the Cortex-M NVIC Registers
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
@{
*/
@@ -325,8 +343,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB CMSIS SCB
- Type definitions for the Cortex-M System Control Block Registers
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
@{
*/
@@ -542,8 +560,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
- Type definitions for the Cortex-M System Control and ID Register not in the SCB
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
@@ -580,8 +598,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick CMSIS SysTick
- Type definitions for the Cortex-M System Timer Registers
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
@{
*/
@@ -630,8 +648,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM CMSIS ITM
- Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
@{
*/
@@ -651,47 +669,387 @@ typedef struct __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU CMSIS MPU
- Type definitions for the Cortex-M Memory Protection Unit (MPU)
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
@@ -750,6 +1108,24 @@ typedef struct #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
@@ -765,8 +1141,8 @@ typedef struct #if (__FPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU CMSIS FPU
- Type definitions for the Cortex-M Floating Point Unit (FPU)
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
@{
*/
@@ -870,8 +1246,8 @@ typedef struct /** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug CMSIS Core Debug
- Type definitions for the Cortex-M Core Debug Registers
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
@{
*/
@@ -972,13 +1348,17 @@ typedef struct /*@} end of group CMSIS_CoreDebug */
-/** \ingroup CMSIS_core_register
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M4 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
@@ -989,6 +1369,8 @@ typedef struct #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1)
@@ -1007,34 +1389,35 @@ typedef struct /*******************************************************************************
* Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
- @{
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
*/
/** \brief Set Priority Grouping
- This function sets the priority grouping field using the required unlock sequence.
+ The function sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field
+ \param [in] PriorityGroup Priority grouping field.
*/
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
@@ -1050,12 +1433,11 @@ static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** \brief Get Priority Grouping
- This function gets the priority grouping from NVIC Interrupt Controller.
- Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
@@ -1063,12 +1445,11 @@ static __INLINE uint32_t NVIC_GetPriorityGrouping(void) /** \brief Enable External Interrupt
- This function enables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Number of the external interrupt to enable
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
@@ -1077,12 +1458,11 @@ static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) /** \brief Disable External Interrupt
- This function disables a device specific interrupt in the NVIC interrupt controller.
- The interrupt number cannot be a negative value.
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Number of the external interrupt to disable
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
@@ -1090,14 +1470,15 @@ static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) /** \brief Get Pending Interrupt
- This function reads the pending register in the NVIC and returns the pending bit
+ The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
- \param [in] IRQn Number of the interrupt for get pending
- \return 0 Interrupt status is not pending
- \return 1 Interrupt status is pending
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
*/
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
@@ -1105,12 +1486,11 @@ static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) /** \brief Set Pending Interrupt
- This function sets the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
+ The function sets the pending bit of an external interrupt.
- \param [in] IRQn Number of the interrupt for set pending
+ \param [in] IRQn Interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
@@ -1118,12 +1498,11 @@ static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) /** \brief Clear Pending Interrupt
- This function clears the pending bit for the specified interrupt.
- The interrupt number cannot be a negative value.
+ The function clears the pending bit of an external interrupt.
- \param [in] IRQn Number of the interrupt for clear pending
+ \param [in] IRQn External interrupt number. Value cannot be negative.
*/
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
@@ -1131,12 +1510,14 @@ static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) /** \brief Get Active Interrupt
- This function reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Number of the interrupt for get active
- \return 0 Interrupt status is not active
- \return 1 Interrupt status is active
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
*/
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
@@ -1144,16 +1525,14 @@ static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) /** \brief Set Interrupt Priority
- This function sets the priority for the specified interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
+ The function sets the priority of an interrupt.
- Note: The priority cannot be set for every core interrupt.
+ \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Number of the interrupt for set priority
- \param [in] priority Priority to set
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
*/
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
@@ -1164,17 +1543,16 @@ static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) /** \brief Get Interrupt Priority
- This function reads the priority for the specified interrupt. The interrupt
+ The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
- The returned priority value is automatically aligned to the implemented
- priority bits of the microcontroller.
- \param [in] IRQn Number of the interrupt for get priority
- \return Interrupt Priority
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
*/
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
@@ -1186,19 +1564,17 @@ static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) /** \brief Encode Priority
- This function encodes the priority for an interrupt with the given priority group,
- preemptive priority value and sub priority value.
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
- The returned priority value can be used for NVIC_SetPriority(...) function
-
- \param [in] PriorityGroup Used priority group
- \param [in] PreemptPriority Preemptive priority value (starting from 0)
- \param [in] SubPriority Sub priority value (starting from 0)
- \return Encoded priority for the interrupt
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1216,19 +1592,17 @@ static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P /** \brief Decode Priority
- This function decodes an interrupt priority value with the given priority group to
- preemptive priority value and sub priority value.
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- The priority value can be retrieved with NVIC_GetPriority(...) function
-
- \param [in] Priority Priority value
- \param [in] PriorityGroup Used priority group
- \param [out] pPreemptPriority Preemptive priority value (starting from 0)
- \param [out] pSubPriority Sub priority value (starting from 0)
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
*/
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
@@ -1244,9 +1618,9 @@ static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr /** \brief System Reset
- This function initiate a system reset request to reset the MCU.
+ The function initiates a system reset request to reset the MCU.
*/
-static __INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
@@ -1263,7 +1637,8 @@ static __INLINE void NVIC_SystemReset(void) /* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
@{
*/
@@ -1271,19 +1646,25 @@ static __INLINE void NVIC_SystemReset(void) /** \brief System Tick Configuration
- This function initialises the system tick timer and its interrupt and start the system tick timer.
- Counter is in free running mode to generate periodical interrupts.
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
- \param [in] ticks Number of ticks between two interrupts
- \return 0 Function succeeded
- \return 1 Function failed
*/
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
@@ -1299,27 +1680,28 @@ static __INLINE uint32_t SysTick_Config(uint32_t ticks) /* ##################################### Debug In/Output function ########################################### */
/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
@{
*/
-extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** \brief ITM Send Character
- This function transmits a character via the ITM channel 0.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
- \param [in] ch Character to transmit
- \return Character to transmit
+ \returns Character to transmit.
*/
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
@@ -1331,14 +1713,12 @@ static __INLINE uint32_t ITM_SendChar (uint32_t ch) /** \brief ITM Receive Character
- This function inputs a character via external variable ITM_RxBuffer.
- It just returns when no debugger is connected that has booked the output.
- It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character
- \return -1 No character received
+ \return Received character.
+ \return -1 No character pending.
*/
-static __INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
@@ -1352,13 +1732,12 @@ static __INLINE int32_t ITM_ReceiveChar (void) { /** \brief ITM Check Character
- This function checks external variable ITM_RxBuffer whether a character is available or not.
- It returns '1' if a character is available and '0' if no character is available.
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available
- \return 1 Character available
+ \return 0 No character available.
+ \return 1 Character available.
*/
-static __INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h b/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h index 479188696..b5140073f 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cm4_simd.h @@ -1,16 +1,16 @@ /**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
- * @version V2.10
- * @date 19. July 2011
+ * @version V3.01
+ * @date 06. March 2012
*
* @note
- * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -23,7 +23,7 @@ #ifdef __cplusplus
extern "C" {
-#endif
+#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
@@ -43,7 +43,7 @@ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
-/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
@@ -118,70 +118,18 @@ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h>
-/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
-/* intrinsic __SADD8 see intrinsics.h */
-/* intrinsic __QADD8 see intrinsics.h */
-/* intrinsic __SHADD8 see intrinsics.h */
-/* intrinsic __UADD8 see intrinsics.h */
-/* intrinsic __UQADD8 see intrinsics.h */
-/* intrinsic __UHADD8 see intrinsics.h */
-/* intrinsic __SSUB8 see intrinsics.h */
-/* intrinsic __QSUB8 see intrinsics.h */
-/* intrinsic __SHSUB8 see intrinsics.h */
-/* intrinsic __USUB8 see intrinsics.h */
-/* intrinsic __UQSUB8 see intrinsics.h */
-/* intrinsic __UHSUB8 see intrinsics.h */
-/* intrinsic __SADD16 see intrinsics.h */
-/* intrinsic __QADD16 see intrinsics.h */
-/* intrinsic __SHADD16 see intrinsics.h */
-/* intrinsic __UADD16 see intrinsics.h */
-/* intrinsic __UQADD16 see intrinsics.h */
-/* intrinsic __UHADD16 see intrinsics.h */
-/* intrinsic __SSUB16 see intrinsics.h */
-/* intrinsic __QSUB16 see intrinsics.h */
-/* intrinsic __SHSUB16 see intrinsics.h */
-/* intrinsic __USUB16 see intrinsics.h */
-/* intrinsic __UQSUB16 see intrinsics.h */
-/* intrinsic __UHSUB16 see intrinsics.h */
-/* intrinsic __SASX see intrinsics.h */
-/* intrinsic __QASX see intrinsics.h */
-/* intrinsic __SHASX see intrinsics.h */
-/* intrinsic __UASX see intrinsics.h */
-/* intrinsic __UQASX see intrinsics.h */
-/* intrinsic __UHASX see intrinsics.h */
-/* intrinsic __SSAX see intrinsics.h */
-/* intrinsic __QSAX see intrinsics.h */
-/* intrinsic __SHSAX see intrinsics.h */
-/* intrinsic __USAX see intrinsics.h */
-/* intrinsic __UQSAX see intrinsics.h */
-/* intrinsic __UHSAX see intrinsics.h */
-/* intrinsic __USAD8 see intrinsics.h */
-/* intrinsic __USADA8 see intrinsics.h */
-/* intrinsic __SSAT16 see intrinsics.h */
-/* intrinsic __USAT16 see intrinsics.h */
-/* intrinsic __UXTB16 see intrinsics.h */
-/* intrinsic __SXTB16 see intrinsics.h */
-/* intrinsic __UXTAB16 see intrinsics.h */
-/* intrinsic __SXTAB16 see intrinsics.h */
-/* intrinsic __SMUAD see intrinsics.h */
-/* intrinsic __SMUADX see intrinsics.h */
-/* intrinsic __SMLAD see intrinsics.h */
-/* intrinsic __SMLADX see intrinsics.h */
-/* intrinsic __SMLALD see intrinsics.h */
-/* intrinsic __SMLALDX see intrinsics.h */
-/* intrinsic __SMUSD see intrinsics.h */
-/* intrinsic __SMUSDX see intrinsics.h */
-/* intrinsic __SMLSD see intrinsics.h */
-/* intrinsic __SMLSDX see intrinsics.h */
-/* intrinsic __SMLSLD see intrinsics.h */
-/* intrinsic __SMLSLDX see intrinsics.h */
-/* intrinsic __SEL see intrinsics.h */
-/* intrinsic __QADD see intrinsics.h */
-/* intrinsic __QSUB see intrinsics.h */
-/* intrinsic __PKHBT see intrinsics.h */
-/* intrinsic __PKHTB see intrinsics.h */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
@@ -191,308 +139,308 @@ /* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
-
+
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
@@ -503,7 +451,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
-
+
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
@@ -511,66 +459,66 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op __RES; \
})
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
-
+
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
-
+
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
-
+
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
-
+
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
@@ -589,34 +537,34 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t o (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
-
+
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
-
+
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
@@ -635,15 +583,15 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t o (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
@@ -651,10 +599,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, return(result);
}
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
-
+
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
@@ -671,7 +619,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
+ else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h b/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h index ecf22a6bf..adb07b5d3 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cmFunc.h @@ -1,16 +1,16 @@ /**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
- * @version V2.10
- * @date 26. July 2011
+ * @version V3.01
+ * @date 06. March 2012
*
* @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -26,7 +26,7 @@ /* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
+/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
@@ -47,7 +47,7 @@ \return Control Register value
*/
-static __INLINE uint32_t __get_CONTROL(void)
+__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
@@ -60,20 +60,20 @@ static __INLINE uint32_t __get_CONTROL(void) \param [in] control Control Register value to set
*/
-static __INLINE void __set_CONTROL(uint32_t control)
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
-/** \brief Get ISPR Register
+/** \brief Get IPSR Register
- This function returns the content of the ISPR Register.
+ This function returns the content of the IPSR Register.
- \return ISPR Register value
+ \return IPSR Register value
*/
-static __INLINE uint32_t __get_IPSR(void)
+__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
@@ -86,7 +86,7 @@ static __INLINE uint32_t __get_IPSR(void) \return APSR Register value
*/
-static __INLINE uint32_t __get_APSR(void)
+__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
@@ -99,7 +99,7 @@ static __INLINE uint32_t __get_APSR(void) \return xPSR Register value
*/
-static __INLINE uint32_t __get_xPSR(void)
+__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
@@ -112,7 +112,7 @@ static __INLINE uint32_t __get_xPSR(void) \return PSP Register value
*/
-static __INLINE uint32_t __get_PSP(void)
+__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
@@ -125,7 +125,7 @@ static __INLINE uint32_t __get_PSP(void) \param [in] topOfProcStack Process Stack Pointer value to set
*/
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
@@ -138,7 +138,7 @@ static __INLINE void __set_PSP(uint32_t topOfProcStack) \return MSP Register value
*/
-static __INLINE uint32_t __get_MSP(void)
+__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
@@ -151,7 +151,7 @@ static __INLINE uint32_t __get_MSP(void) \param [in] topOfMainStack Main Stack Pointer value to set
*/
-static __INLINE void __set_MSP(uint32_t topOfMainStack)
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
@@ -164,7 +164,7 @@ static __INLINE void __set_MSP(uint32_t topOfMainStack) \return Priority Mask value
*/
-static __INLINE uint32_t __get_PRIMASK(void)
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
@@ -177,12 +177,12 @@ static __INLINE uint32_t __get_PRIMASK(void) \param [in] priMask Priority Mask
*/
-static __INLINE void __set_PRIMASK(uint32_t priMask)
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
-
+
#if (__CORTEX_M >= 0x03)
@@ -208,7 +208,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask) \return Base Priority register value
*/
-static __INLINE uint32_t __get_BASEPRI(void)
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
@@ -221,12 +221,12 @@ static __INLINE uint32_t __get_BASEPRI(void) \param [in] basePri Base Priority value to set
*/
-static __INLINE void __set_BASEPRI(uint32_t basePri)
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
-
+
/** \brief Get Fault Mask
@@ -234,7 +234,7 @@ static __INLINE void __set_BASEPRI(uint32_t basePri) \return Fault Mask register value
*/
-static __INLINE uint32_t __get_FAULTMASK(void)
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
@@ -247,7 +247,7 @@ static __INLINE uint32_t __get_FAULTMASK(void) \param [in] faultMask Fault Mask value to set
*/
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
@@ -264,7 +264,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask) \return Floating Point Status/Control register value
*/
-static __INLINE uint32_t __get_FPSCR(void)
+__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
@@ -281,7 +281,7 @@ static __INLINE uint32_t __get_FPSCR(void) \param [in] fpscr Floating Point Status/Control value to set
*/
-static __INLINE void __set_FPSCR(uint32_t fpscr)
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
@@ -297,6 +297,13 @@ static __INLINE void __set_FPSCR(uint32_t fpscr) #include <cmsis_iar.h>
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
@@ -305,7 +312,7 @@ static __INLINE void __set_FPSCR(uint32_t fpscr) This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
@@ -316,7 +323,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
@@ -328,7 +335,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) \return Control Register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
@@ -343,19 +350,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) \param [in] control Control Register value to set
*/
-__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
-/** \brief Get ISPR Register
+/** \brief Get IPSR Register
- This function returns the content of the ISPR Register.
+ This function returns the content of the IPSR Register.
- \return ISPR Register value
+ \return IPSR Register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
@@ -370,7 +377,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) \return APSR Register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
@@ -385,7 +392,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) \return xPSR Register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
@@ -400,14 +407,14 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) \return PSP Register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
-
+
/** \brief Set Process Stack Pointer
@@ -415,7 +422,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) \param [in] topOfProcStack Process Stack Pointer value to set
*/
-__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
@@ -427,14 +434,14 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOf \return MSP Register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
-
+
/** \brief Set Main Stack Pointer
@@ -442,7 +449,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) \param [in] topOfMainStack Main Stack Pointer value to set
*/
-__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
@@ -454,7 +461,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOf \return Priority Mask value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
@@ -469,11 +476,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) \param [in] priMask Priority Mask
*/
-__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
-
+
#if (__CORTEX_M >= 0x03)
@@ -482,7 +489,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
@@ -493,7 +500,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
@@ -505,10 +512,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void \return Base Priority register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
-
+
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
@@ -520,7 +527,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) \param [in] basePri Base Priority value to set
*/
-__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
@@ -532,10 +539,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v \return Fault Mask register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
-
+
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
@@ -547,7 +554,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void \param [in] faultMask Fault Mask value to set
*/
-__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
@@ -563,7 +570,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t \return Floating Point Status/Control register value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
@@ -582,13 +589,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) \param [in] fpscr Floating Point Status/Control value to set
*/
-__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#else
-/* CHIBIOS FIX */
- (void)fpscr;
#endif
}
diff --git a/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h b/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h index ceb4f8756..624c175fd 100644 --- a/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h +++ b/os/ports/common/ARMCMx/CMSIS/include/core_cmInstr.h @@ -1,16 +1,16 @@ /**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V2.10
- * @date 19. July 2011
+ * @version V3.01
+ * @date 06. March 2012
*
* @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -71,8 +71,8 @@ /** \brief Instruction Synchronization Barrier
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
@@ -80,7 +80,7 @@ /** \brief Data Synchronization Barrier
- This function acts as a special kind of Data Memory Barrier.
+ This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
@@ -88,7 +88,7 @@ /** \brief Data Memory Barrier
- This function ensures the apparent order of the explicit memory operations before
+ This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
@@ -111,7 +111,7 @@ \param [in] value Value to reverse
\return Reversed value
*/
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
@@ -125,13 +125,24 @@ static __INLINE __ASM uint32_t __REV16(uint32_t value) \param [in] value Value to reverse
\return Reversed value
*/
-static __INLINE __ASM int32_t __REVSH(int32_t value)
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
@@ -247,7 +258,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value) \param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
-#define __CLZ __clz
+#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
@@ -259,6 +270,12 @@ static __INLINE __ASM int32_t __REVSH(int32_t value) #include <cmsis_iar.h>
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
@@ -266,7 +283,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value) No Operation does nothing. This instruction can be used for code alignment purposes.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
@@ -277,7 +294,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __NOP(void) Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
@@ -288,7 +305,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void) Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
@@ -298,7 +315,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void) Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
@@ -306,11 +323,11 @@ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void) /** \brief Instruction Synchronization Barrier
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
@@ -318,10 +335,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void) /** \brief Data Synchronization Barrier
- This function acts as a special kind of Data Memory Barrier.
+ This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
@@ -329,10 +346,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void) /** \brief Data Memory Barrier
- This function ensures the apparent order of the explicit memory operations before
+ This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
@@ -345,10 +362,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void) \param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
-
+
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -361,10 +378,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value \param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
-
+
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -377,15 +394,31 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t val \param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
-
+
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
@@ -395,10 +428,10 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value \param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
-
+
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -411,10 +444,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t valu \param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
-
+
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
@@ -427,10 +460,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uin \param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
-
+
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
@@ -443,10 +476,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile ui \param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
-
+
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
@@ -461,11 +494,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile ui \return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@@ -479,11 +512,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t val \return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@@ -497,11 +530,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t va \return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@@ -511,7 +544,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t va This function removes the exclusive lock which is created by LDREX.
*/
-__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
@@ -556,10 +589,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) \param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
-
+
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
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