Added demo for STM32L496 and various support stuff.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12270 110e8d01-0319-4d1e-a829-52ad28d1bb01

1 files changed, 77 insertions, 24 deletions

diff --git a/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl
index 07985e4e2..4756baaa9 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32l496xx/mcuconf.h.ftl
@@ -43,7 +43,7 @@
 #define MCUCONF_H

 

 #define STM32L4xx_MCUCONF

-#define STM32L4R5_MCUCONF

+#define STM32L496_MCUCONF

 

 /*

  * HAL driver system settings.

@@ -67,11 +67,11 @@
 #define STM32_SW                            ${doc.STM32_SW!"STM32_SW_PLL"}

 #define STM32_PLLSRC                        ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}

 #define STM32_PLLM_VALUE                    ${doc.STM32_PLLM_VALUE!"1"}

-#define STM32_PLLN_VALUE                    ${doc.STM32_PLLN_VALUE!"60"}

+#define STM32_PLLN_VALUE                    ${doc.STM32_PLLN_VALUE!"80"}

 #define STM32_PLLPDIV_VALUE                 ${doc.STM32_PLLPDIV_VALUE!"0"}

 #define STM32_PLLP_VALUE                    ${doc.STM32_PLLP_VALUE!"7"}

-#define STM32_PLLQ_VALUE                    ${doc.STM32_PLLQ_VALUE!"4"}

-#define STM32_PLLR_VALUE                    ${doc.STM32_PLLR_VALUE!"2"}

+#define STM32_PLLQ_VALUE                    ${doc.STM32_PLLQ_VALUE!"6"}

+#define STM32_PLLR_VALUE                    ${doc.STM32_PLLR_VALUE!"4"}

 #define STM32_HPRE                          ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}

 #define STM32_PPRE1                         ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}

 #define STM32_PPRE2                         ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}

@@ -132,16 +132,26 @@
  */

 #define STM32_ADC_COMPACT_SAMPLES           ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}

 #define STM32_ADC_USE_ADC1                  ${doc.STM32_ADC_USE_ADC1!"FALSE"}

-#define STM32_ADC_ADC1_DMA_CHANNEL          ${doc.STM32_ADC_ADC1_DMA_CHANNEL!"10"}

+#define STM32_ADC_USE_ADC2                  ${doc.STM32_ADC_USE_ADC1!"FALSE"}

+#define STM32_ADC_USE_ADC3                  ${doc.STM32_ADC_USE_ADC1!"FALSE"}

+#define STM32_ADC_ADC1_DMA_STREAM           ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}

+#define STM32_ADC_ADC2_DMA_STREAM           ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}

+#define STM32_ADC_ADC3_DMA_STREAM           ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}

 #define STM32_ADC_ADC1_DMA_PRIORITY         ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}

+#define STM32_ADC_ADC2_DMA_PRIORITY         ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}

+#define STM32_ADC_ADC3_DMA_PRIORITY         ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}

 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}

-#define STM32_ADC_ADC123_CLOCK_MODE         ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV2"}

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"}

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"5"}

+#define STM32_ADC_ADC123_CLOCK_MODE         ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}

 

 /*

  * CAN driver system settings.

  */

 #define STM32_CAN_USE_CAN1                  ${doc.STM32_CAN_USE_CAN1!"FALSE"}

+#define STM32_CAN_USE_CAN2                  ${doc.STM32_CAN_USE_CAN2!"FALSE"}

 #define STM32_CAN_CAN1_IRQ_PRIORITY         ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}

+#define STM32_CAN_CAN2_IRQ_PRIORITY         ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}

 

 /*

  * DAC driver system settings.

@@ -153,8 +163,8 @@
 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}

 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}

 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}

-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL      ${doc.STM32_DAC_DAC1_CH1_DMA_CHANNEL!"11"}

-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL      ${doc.STM32_DAC_DAC1_CH2_DMA_CHANNEL!"12"}

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}

 

 /*

  * GPT driver system settings.

@@ -183,12 +193,12 @@
 #define STM32_I2C_USE_I2C2                  ${doc.STM32_I2C_USE_I2C2!"FALSE"}

 #define STM32_I2C_USE_I2C3                  ${doc.STM32_I2C_USE_I2C3!"FALSE"}

 #define STM32_I2C_BUSY_TIMEOUT              ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}

-#define STM32_I2C_I2C1_RX_DMA_CHANNEL       ${doc.STM32_I2C_I2C1_RX_DMA_CHANNEL!"6"}

-#define STM32_I2C_I2C1_TX_DMA_CHANNEL       ${doc.STM32_I2C_I2C1_TX_DMA_CHANNEL!"7"}

-#define STM32_I2C_I2C2_RX_DMA_CHANNEL       ${doc.STM32_I2C_I2C2_RX_DMA_CHANNEL!"8"}

-#define STM32_I2C_I2C2_TX_DMA_CHANNEL       ${doc.STM32_I2C_I2C2_TX_DMA_CHANNEL!"9"}

-#define STM32_I2C_I2C3_RX_DMA_CHANNEL       ${doc.STM32_I2C_I2C3_RX_DMA_CHANNEL!"8"}

-#define STM32_I2C_I2C3_TX_DMA_CHANNEL       ${doc.STM32_I2C_I2C3_TX_DMA_CHANNEL!"9"}

+#define STM32_I2C_I2C1_RX_DMA_STREAM        ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}

+#define STM32_I2C_I2C1_TX_DMA_STREAM        ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}

+#define STM32_I2C_I2C2_RX_DMA_STREAM        ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}

+#define STM32_I2C_I2C2_TX_DMA_STREAM        ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}

+#define STM32_I2C_I2C3_RX_DMA_STREAM        ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}

+#define STM32_I2C_I2C3_TX_DMA_STREAM        ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}

 #define STM32_I2C_I2C1_IRQ_PRIORITY         ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}

 #define STM32_I2C_I2C2_IRQ_PRIORITY         ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}

 #define STM32_I2C_I2C3_IRQ_PRIORITY         ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}

@@ -231,8 +241,22 @@
 #define STM32_PWM_TIM8_IRQ_PRIORITY         ${doc.STM32_PWM_TIM8_IRQ_PRIORITY!"7"}

 

 /*

+ * QSPI driver system settings.

+ */

+#define STM32_QSPI_USE_QUADSPI1             ${doc.STM32_QSPI_USE_QUADSPI1!"FALSE"}

+#define STM32_QSPI_QUADSPI1_DMA_STREAM      ${doc.STM32_QSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}

+

+/*

  * SDC driver system settings.

  */

+#define STM32_SDC_USE_SDMMC1                ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}

+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}

+#define STM32_SDC_SDMMC_WRITE_TIMEOUT       ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}

+#define STM32_SDC_SDMMC_READ_TIMEOUT        ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}

+#define STM32_SDC_SDMMC_CLOCK_DELAY         ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}

+#define STM32_SDC_SDMMC1_DMA_PRIORITY       ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}

+#define STM32_SDC_SDMMC1_IRQ_PRIORITY       ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}

+#define STM32_SDC_SDMMC1_DMA_STREAM         ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}

 

 /*

  * SERIAL driver system settings.

@@ -256,12 +280,12 @@
 #define STM32_SPI_USE_SPI1                  ${doc.STM32_SPI_USE_SPI1!"FALSE"}

 #define STM32_SPI_USE_SPI2                  ${doc.STM32_SPI_USE_SPI2!"FALSE"}

 #define STM32_SPI_USE_SPI3                  ${doc.STM32_SPI_USE_SPI3!"FALSE"}

-#define STM32_SPI_SPI1_RX_DMA_CHANNEL       ${doc.STM32_SPI_SPI1_RX_DMA_CHANNEL!"0"}

-#define STM32_SPI_SPI1_TX_DMA_CHANNEL       ${doc.STM32_SPI_SPI1_TX_DMA_CHANNEL!"1"}

-#define STM32_SPI_SPI2_RX_DMA_CHANNEL       ${doc.STM32_SPI_SPI2_RX_DMA_CHANNEL!"2"}

-#define STM32_SPI_SPI2_TX_DMA_CHANNEL       ${doc.STM32_SPI_SPI2_TX_DMA_CHANNEL!"3"}

-#define STM32_SPI_SPI3_RX_DMA_CHANNEL       ${doc.STM32_SPI_SPI3_RX_DMA_CHANNEL!"4"}

-#define STM32_SPI_SPI3_TX_DMA_CHANNEL       ${doc.STM32_SPI_SPI3_TX_DMA_CHANNEL!"5"}

+#define STM32_SPI_SPI1_RX_DMA_STREAM        ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}

+#define STM32_SPI_SPI1_TX_DMA_STREAM        ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}

+#define STM32_SPI_SPI2_RX_DMA_STREAM        ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}

+#define STM32_SPI_SPI2_TX_DMA_STREAM        ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}

+#define STM32_SPI_SPI3_RX_DMA_STREAM        ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}

+#define STM32_SPI_SPI3_TX_DMA_STREAM        ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}

 #define STM32_SPI_SPI1_DMA_PRIORITY         ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}

 #define STM32_SPI_SPI2_DMA_PRIORITY         ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}

 #define STM32_SPI_SPI3_DMA_PRIORITY         ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}

@@ -279,18 +303,47 @@
 /*

  * UART driver system settings.

  */

+#define STM32_UART_USE_USART1               ${doc.STM32_UART_USE_USART1!"FALSE"}

+#define STM32_UART_USE_USART2               ${doc.STM32_UART_USE_USART2!"FALSE"}

+#define STM32_UART_USE_USART3               ${doc.STM32_UART_USE_USART3!"FALSE"}

+#define STM32_UART_USE_UART4                ${doc.STM32_UART_USE_UART4!"FALSE"}

+#define STM32_UART_USE_UART5                ${doc.STM32_UART_USE_UART5!"FALSE"}

+#define STM32_UART_USE_LPUART1              ${doc.STM32_UART_USE_LPUART1!"FALSE"}

+#define STM32_UART_USART1_RX_DMA_STREAM     ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}

+#define STM32_UART_USART1_TX_DMA_STREAM     ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}

+#define STM32_UART_USART2_RX_DMA_STREAM     ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}

+#define STM32_UART_USART2_TX_DMA_STREAM     ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}

+#define STM32_UART_USART3_RX_DMA_STREAM     ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}

+#define STM32_UART_USART3_TX_DMA_STREAM     ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}

+#define STM32_UART_UART4_RX_DMA_STREAM      ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}

+#define STM32_UART_UART4_TX_DMA_STREAM      ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}

+#define STM32_UART_UART5_RX_DMA_STREAM      ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}

+#define STM32_UART_UART5_TX_DMA_STREAM      ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}

+#define STM32_UART_LPUART1_RX_DMA_STREAM    ${doc.STM32_UART_LPUART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}

+#define STM32_UART_LPUART1_TX_DMA_STREAM    ${doc.STM32_UART_LPUART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}

+#define STM32_UART_USART1_IRQ_PRIORITY      ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART2_IRQ_PRIORITY      ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART3_IRQ_PRIORITY      ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}

+#define STM32_UART_UART4_IRQ_PRIORITY       ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}

+#define STM32_UART_UART5_IRQ_PRIORITY       ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART1_DMA_PRIORITY      ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}

+#define STM32_UART_USART2_DMA_PRIORITY      ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}

+#define STM32_UART_USART3_DMA_PRIORITY      ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}

+#define STM32_UART_UART4_DMA_PRIORITY       ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}

+#define STM32_UART_UART5_DMA_PRIORITY       ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}

+#define STM32_UART_LPUART1_DMA_PRIORITY     ${doc.STM32_UART_LPUART1_DMA_PRIORITY!"0"}

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}

 

 /*

  * USB driver system settings.

  */

+#define STM32_USB_USE_OTG1                  ${doc.STM32_USB_USE_OTG1!"FALSE"}

+#define STM32_USB_OTG1_IRQ_PRIORITY         ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}

+#define STM32_USB_OTG1_RX_FIFO_SIZE         ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}

 

 /*

  * WDG driver system settings.

  */

 #define STM32_WDG_USE_IWDG                  ${doc.STM32_WDG_USE_IWDG!"FALSE"}

 

-/*

- * WSPI driver system settings.

- */

-

 #endif /* MCUCONF_H */