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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-08-28 13:39:56 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-08-28 13:39:56 +0000
commitfc492c6d190610cc9537360edf44d6dc5d072a2c (patch)
tree53fb1786e058f872671fb3adca4e73c708716d54 /testhal
parentda23780899ae4b9ce1bbe0cb9109da1c87fe0fa1 (diff)
parent663214d0e6728d153fd4118324e69c75c574327c (diff)
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I2C. Merge code from trunk.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3263 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal')
-rw-r--r--testhal/STM32F1xx/ADC/chconf.h12
-rw-r--r--testhal/STM32F1xx/SDIO/chconf.h12
-rw-r--r--testhal/STM32F1xx/SPI/chconf.h12
-rw-r--r--testhal/STM32F1xx/SPI/mcuconf.h2
-rw-r--r--testhal/STM32F1xx/UART/chconf.h12
-rw-r--r--testhal/STM32F1xx/UART/main.c4
-rw-r--r--testhal/STM32F1xx/UART/mcuconf.h4
-rw-r--r--testhal/STM32F1xx/USB_CDC/chconf.h12
-rw-r--r--testhal/STM32F1xx/USB_CDC/main.c12
9 files changed, 40 insertions, 42 deletions
diff --git a/testhal/STM32F1xx/ADC/chconf.h b/testhal/STM32F1xx/ADC/chconf.h
index 9dd831c96..a5d129956 100644
--- a/testhal/STM32F1xx/ADC/chconf.h
+++ b/testhal/STM32F1xx/ADC/chconf.h
@@ -361,7 +361,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif
/**
@@ -372,7 +372,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
+#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
@@ -384,7 +384,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
+#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
@@ -395,7 +395,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
+#define CH_DBG_ENABLE_TRACE TRUE
#endif
/**
@@ -409,7 +409,7 @@
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
@@ -421,7 +421,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS FALSE
+#define CH_DBG_FILL_THREADS TRUE
#endif
/**
diff --git a/testhal/STM32F1xx/SDIO/chconf.h b/testhal/STM32F1xx/SDIO/chconf.h
index 9dd831c96..a5d129956 100644
--- a/testhal/STM32F1xx/SDIO/chconf.h
+++ b/testhal/STM32F1xx/SDIO/chconf.h
@@ -361,7 +361,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif
/**
@@ -372,7 +372,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
+#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
@@ -384,7 +384,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
+#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
@@ -395,7 +395,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
+#define CH_DBG_ENABLE_TRACE TRUE
#endif
/**
@@ -409,7 +409,7 @@
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
@@ -421,7 +421,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS FALSE
+#define CH_DBG_FILL_THREADS TRUE
#endif
/**
diff --git a/testhal/STM32F1xx/SPI/chconf.h b/testhal/STM32F1xx/SPI/chconf.h
index 9dd831c96..a5d129956 100644
--- a/testhal/STM32F1xx/SPI/chconf.h
+++ b/testhal/STM32F1xx/SPI/chconf.h
@@ -361,7 +361,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif
/**
@@ -372,7 +372,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
+#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
@@ -384,7 +384,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
+#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
@@ -395,7 +395,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
+#define CH_DBG_ENABLE_TRACE TRUE
#endif
/**
@@ -409,7 +409,7 @@
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
@@ -421,7 +421,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS FALSE
+#define CH_DBG_FILL_THREADS TRUE
#endif
/**
diff --git a/testhal/STM32F1xx/SPI/mcuconf.h b/testhal/STM32F1xx/SPI/mcuconf.h
index ab96d8eef..558c0773d 100644
--- a/testhal/STM32F1xx/SPI/mcuconf.h
+++ b/testhal/STM32F1xx/SPI/mcuconf.h
@@ -127,7 +127,7 @@
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
-#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
diff --git a/testhal/STM32F1xx/UART/chconf.h b/testhal/STM32F1xx/UART/chconf.h
index 9dd831c96..a5d129956 100644
--- a/testhal/STM32F1xx/UART/chconf.h
+++ b/testhal/STM32F1xx/UART/chconf.h
@@ -361,7 +361,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif
/**
@@ -372,7 +372,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
+#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
@@ -384,7 +384,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
+#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
@@ -395,7 +395,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
+#define CH_DBG_ENABLE_TRACE TRUE
#endif
/**
@@ -409,7 +409,7 @@
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
@@ -421,7 +421,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS FALSE
+#define CH_DBG_FILL_THREADS TRUE
#endif
/**
diff --git a/testhal/STM32F1xx/UART/main.c b/testhal/STM32F1xx/UART/main.c
index 924338a77..b3ccd35fd 100644
--- a/testhal/STM32F1xx/UART/main.c
+++ b/testhal/STM32F1xx/UART/main.c
@@ -26,9 +26,7 @@ static VirtualTimer vt1, vt2;
static void restart(void *p) {
(void)p;
- chSysLockFromIsr();
uartStartSendI(&UARTD2, 14, "Hello World!\r\n");
- chSysUnlockFromIsr();
}
static void ledoff(void *p) {
@@ -48,7 +46,7 @@ static void txend1(UARTDriver *uartp) {
}
/*
- * This callback is invoked when a transmission has phisically completed.
+ * This callback is invoked when a transmission has physically completed.
*/
static void txend2(UARTDriver *uartp) {
diff --git a/testhal/STM32F1xx/UART/mcuconf.h b/testhal/STM32F1xx/UART/mcuconf.h
index 558c0773d..c8dd60ca1 100644
--- a/testhal/STM32F1xx/UART/mcuconf.h
+++ b/testhal/STM32F1xx/UART/mcuconf.h
@@ -140,9 +140,9 @@
/*
* UART driver system settings.
*/
-#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART1 TRUE
#define STM32_UART_USE_USART2 TRUE
-#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_USART3 TRUE
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
diff --git a/testhal/STM32F1xx/USB_CDC/chconf.h b/testhal/STM32F1xx/USB_CDC/chconf.h
index 9dd831c96..a5d129956 100644
--- a/testhal/STM32F1xx/USB_CDC/chconf.h
+++ b/testhal/STM32F1xx/USB_CDC/chconf.h
@@ -361,7 +361,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
#endif
/**
@@ -372,7 +372,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_CHECKS FALSE
+#define CH_DBG_ENABLE_CHECKS TRUE
#endif
/**
@@ -384,7 +384,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_ASSERTS FALSE
+#define CH_DBG_ENABLE_ASSERTS TRUE
#endif
/**
@@ -395,7 +395,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_TRACE FALSE
+#define CH_DBG_ENABLE_TRACE TRUE
#endif
/**
@@ -409,7 +409,7 @@
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
-#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
#endif
/**
@@ -421,7 +421,7 @@
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
-#define CH_DBG_FILL_THREADS FALSE
+#define CH_DBG_FILL_THREADS TRUE
#endif
/**
diff --git a/testhal/STM32F1xx/USB_CDC/main.c b/testhal/STM32F1xx/USB_CDC/main.c
index a0a965bba..601b6ce0b 100644
--- a/testhal/STM32F1xx/USB_CDC/main.c
+++ b/testhal/STM32F1xx/USB_CDC/main.c
@@ -114,7 +114,7 @@ static const uint8_t vcom_configuration_descriptor_data[67] = {
USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
Interface). */
/* Endpoint 2 Descriptor.*/
- USB_DESC_ENDPOINT (INTERRUPT_REQUEST_EP|0x80, /* bEndpointAddress. */
+ USB_DESC_ENDPOINT (USB_CDC_INTERRUPT_REQUEST_EP|0x80,
0x03, /* bmAttributes (Interrupt). */
0x0008, /* wMaxPacketSize. */
0xFF), /* bInterval. */
@@ -130,12 +130,12 @@ static const uint8_t vcom_configuration_descriptor_data[67] = {
4.7). */
0x00), /* iInterface. */
/* Endpoint 3 Descriptor.*/
- USB_DESC_ENDPOINT (DATA_AVAILABLE_EP, /* bEndpointAddress. */
+ USB_DESC_ENDPOINT (USB_CDC_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00), /* bInterval. */
/* Endpoint 1 Descriptor.*/
- USB_DESC_ENDPOINT (DATA_REQUEST_EP|0x80, /* bEndpointAddress. */
+ USB_DESC_ENDPOINT (USB_CDC_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00) /* bInterval. */
@@ -282,9 +282,9 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
Note, this callback is invoked from an ISR so I-Class functions
must be used.*/
chSysLockFromIsr();
- usbInitEndpointI(usbp, DATA_REQUEST_EP, &ep1config);
- usbInitEndpointI(usbp, INTERRUPT_REQUEST_EP, &ep2config);
- usbInitEndpointI(usbp, DATA_AVAILABLE_EP, &ep3config);
+ usbInitEndpointI(usbp, USB_CDC_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USB_CDC_INTERRUPT_REQUEST_EP, &ep2config);
+ usbInitEndpointI(usbp, USB_CDC_DATA_AVAILABLE_EP, &ep3config);
chSysUnlockFromIsr();
return;
case USB_EVENT_SUSPEND: