I2C. Added simple test for STM32F4x.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3697 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 1480 insertions, 0 deletions

diff --git a/testhal/STM32F4xx/I2C/Makefile b/testhal/STM32F4xx/I2C/Makefile
new file mode 100644
index 000000000..3eb661a33
--- /dev/null
+++ b/testhal/STM32F4xx/I2C/Makefile
@@ -0,0 +1,207 @@
+##############################################################################

+# Build global options

+# NOTE: Can be overridden externally.

+#

+

+# Compiler options here.

+ifeq ($(USE_OPT),)

+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant

+endif

+

+# C specific options here (added to USE_OPT).

+ifeq ($(USE_COPT),)

+  USE_COPT = 

+endif

+

+# C++ specific options here (added to USE_OPT).

+ifeq ($(USE_CPPOPT),)

+  USE_CPPOPT = -fno-rtti

+endif

+

+# Enable this if you want the linker to remove unused code and data

+ifeq ($(USE_LINK_GC),)

+  USE_LINK_GC = yes

+endif

+

+# If enabled, this option allows to compile the application in THUMB mode.

+ifeq ($(USE_THUMB),)

+  USE_THUMB = yes

+endif

+

+# Enable this if you want to see the full log while compiling.

+ifeq ($(USE_VERBOSE_COMPILE),)

+  USE_VERBOSE_COMPILE = no

+endif

+

+#

+# Build global options

+##############################################################################

+

+##############################################################################

+# Architecture or project specific options

+#

+

+# Enable this if you really want to use the STM FWLib.

+ifeq ($(USE_FWLIB),)

+  USE_FWLIB = no

+endif

+

+#

+# Architecture or project specific options

+##############################################################################

+

+##############################################################################

+# Project, sources and paths

+#

+

+# Define project name here

+PROJECT = ch

+

+# Imported source files and paths

+CHIBIOS = ../../..

+include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk

+include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk

+include $(CHIBIOS)/os/hal/hal.mk

+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk

+include $(CHIBIOS)/os/kernel/kernel.mk

+#include $(CHIBIOS)/test/test.mk

+

+# Define linker script file here

+LDSCRIPT= $(PORTLD)/STM32F407xG.ld

+

+# C sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CSRC = $(PORTSRC) \

+       $(KERNSRC) \

+       $(TESTSRC) \

+       $(HALSRC) \

+       $(PLATFORMSRC) \

+       $(BOARDSRC) \

+       main.c

+

+# C++ sources that can be compiled in ARM or THUMB mode depending on the global

+# setting.

+CPPSRC =

+

+# C sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACSRC =

+

+# C++ sources to be compiled in ARM mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+ACPPSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCSRC =

+

+# C sources to be compiled in THUMB mode regardless of the global setting.

+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler

+#       option that results in lower performance and larger code size.

+TCPPSRC =

+

+# List ASM source files here

+ASMSRC = $(PORTASM)

+

+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \

+         $(HALINC) $(PLATFORMINC) $(BOARDINC) \

+         $(CHIBIOS)/os/various

+

+#

+# Project, sources and paths

+##############################################################################

+

+##############################################################################

+# Compiler settings

+#

+

+MCU  = cortex-m4

+

+#TRGT = arm-elf-

+TRGT = arm-none-eabi-

+CC   = $(TRGT)gcc

+CPPC = $(TRGT)g++

+# Enable loading with g++ only if you need C++ runtime support.

+# NOTE: You can use C++ even without C++ support if you are careful. C++

+#       runtime support makes code size explode.

+LD   = $(TRGT)gcc

+#LD   = $(TRGT)g++

+CP   = $(TRGT)objcopy

+AS   = $(TRGT)gcc -x assembler-with-cpp

+OD   = $(TRGT)objdump

+HEX  = $(CP) -O ihex

+BIN  = $(CP) -O binary

+

+# ARM-specific options here

+AOPT =

+

+# THUMB-specific options here

+TOPT = -mthumb -DTHUMB

+

+# Define C warning options here

+CWARN = -Wall -Wextra -Wstrict-prototypes

+

+# Define C++ warning options here

+CPPWARN = -Wall -Wextra

+

+#

+# Compiler settings

+##############################################################################

+

+##############################################################################

+# Start of default section

+#

+

+# List all default C defines here, like -D_DEBUG=1

+DDEFS =

+

+# List all default ASM defines here, like -D_DEBUG=1

+DADEFS =

+

+# List all default directories to look for include files here

+DINCDIR =

+

+# List the default directory to look for the libraries here

+DLIBDIR =

+

+# List all default libraries here

+DLIBS =

+

+#

+# End of default section

+##############################################################################

+

+##############################################################################

+# Start of user section

+#

+

+# List all user C define here, like -D_DEBUG=1

+UDEFS =

+

+# Define ASM defines here

+UADEFS =

+

+# List all user directories here

+UINCDIR =

+

+# List the user directory to look for the libraries here

+ULIBDIR =

+

+# List all user libraries here

+ULIBS =

+

+#

+# End of user defines

+##############################################################################

+

+ifeq ($(USE_FWLIB),yes)

+  include $(CHIBIOS)/ext/stm32lib/stm32lib.mk

+  CSRC += $(STM32SRC)

+  INCDIR += $(STM32INC)

+  USE_OPT += -DUSE_STDPERIPH_DRIVER

+endif

+

+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk

diff --git a/testhal/STM32F4xx/I2C/chconf.h b/testhal/STM32F4xx/I2C/chconf.h
new file mode 100644
index 000000000..26784ccfd
--- /dev/null
+++ b/testhal/STM32F4xx/I2C/chconf.h
@@ -0,0 +1,513 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    templates/chconf.h

+ * @brief   Configuration file template.

+ * @details A copy of this file must be placed in each project directory, it

+ *          contains the application specific kernel settings.

+ *

+ * @addtogroup config

+ * @details Kernel related settings and hooks.

+ * @{

+ */

+

+#ifndef _CHCONF_H_

+#define _CHCONF_H_

+

+//#define CORTEX_VTOR_INIT       0x000E0000

+#define CORTEX_VTOR_INIT  0x00000000

+#define CORTEX_USE_FPU    TRUE

+

+/*===========================================================================*/

+/* Kernel parameters.                                                        */

+/*===========================================================================*/

+

+/**

+ * @brief   System tick frequency.

+ * @details Frequency of the system timer that drives the system ticks. This

+ *          setting also defines the system tick time unit.

+ */

+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)

+#define CH_FREQUENCY                    1000

+#endif

+

+/**

+ * @brief   Round robin interval.

+ * @details This constant is the number of system ticks allowed for the

+ *          threads before preemption occurs. Setting this value to zero

+ *          disables the preemption for threads with equal priority and the

+ *          round robin becomes cooperative. Note that higher priority

+ *          threads can still preempt, the kernel is always preemptive.

+ *

+ * @note    Disabling the round robin preemption makes the kernel more compact

+ *          and generally faster.

+ */

+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)

+#define CH_TIME_QUANTUM                 0//20

+#endif

+

+/**

+ * @brief   Managed RAM size.

+ * @details Size of the RAM area to be managed by the OS. If set to zero

+ *          then the whole available RAM is used. The core memory is made

+ *          available to the heap allocator and/or can be used directly through

+ *          the simplified core memory allocator.

+ *

+ * @note    In order to let the OS manage the whole RAM the linker script must

+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.

+ * @note    Requires @p CH_USE_MEMCORE.

+ */

+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)

+#define CH_MEMCORE_SIZE                 0

+#endif

+

+/**

+ * @brief   Idle thread automatic spawn suppression.

+ * @details When this option is activated the function @p chSysInit()

+ *          does not spawn the idle thread automatically. The application has

+ *          then the responsibility to do one of the following:

+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.

+ *          - Change the main() thread priority to @p IDLEPRIO then enter

+ *            an endless loop. In this scenario the @p main() thread acts as

+ *            the idle thread.

+ *          .

+ * @note    Unless an idle thread is spawned the @p main() thread must not

+ *          enter a sleep state.

+ */

+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)

+#define CH_NO_IDLE_THREAD               FALSE

+#endif

+

+/*===========================================================================*/

+/* Performance options.                                                      */

+/*===========================================================================*/

+

+/**

+ * @brief   OS optimization.

+ * @details If enabled then time efficient rather than space efficient code

+ *          is used when two possible implementations exist.

+ *

+ * @note    This is not related to the compiler optimization options.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)

+#define CH_OPTIMIZE_SPEED               FALSE

+#endif

+

+/*===========================================================================*/

+/* Subsystem options.                                                        */

+/*===========================================================================*/

+

+/**

+ * @brief   Threads registry APIs.

+ * @details If enabled then the registry APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)

+#define CH_USE_REGISTRY                 TRUE

+#endif

+

+/**

+ * @brief   Threads synchronization APIs.

+ * @details If enabled then the @p chThdWait() function is included in

+ *          the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)

+#define CH_USE_WAITEXIT                 TRUE

+#endif

+

+/**

+ * @brief   Semaphores APIs.

+ * @details If enabled then the Semaphores APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)

+#define CH_USE_SEMAPHORES               TRUE

+#endif

+

+/**

+ * @brief   Semaphores queuing mode.

+ * @details If enabled then the threads are enqueued on semaphores by

+ *          priority rather than in FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special requirements.

+ * @note    Requires @p CH_USE_SEMAPHORES.

+ */

+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)

+#define CH_USE_SEMAPHORES_PRIORITY      FALSE

+#endif

+

+/**

+ * @brief   Atomic semaphore API.

+ * @details If enabled then the semaphores the @p chSemSignalWait() API

+ *          is included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_USE_SEMAPHORES.

+ */

+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)

+#define CH_USE_SEMSW                    TRUE

+#endif

+

+/**

+ * @brief   Mutexes APIs.

+ * @details If enabled then the mutexes APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)

+#define CH_USE_MUTEXES                  TRUE

+#endif

+

+/**

+ * @brief   Conditional Variables APIs.

+ * @details If enabled then the conditional variables APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_USE_MUTEXES.

+ */

+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)

+#define CH_USE_CONDVARS                 FALSE

+#endif

+

+/**

+ * @brief   Conditional Variables APIs with timeout.

+ * @details If enabled then the conditional variables APIs with timeout

+ *          specification are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_USE_CONDVARS.

+ */

+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)

+#define CH_USE_CONDVARS_TIMEOUT         TRUE

+#endif

+

+/**

+ * @brief   Events Flags APIs.

+ * @details If enabled then the event flags APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)

+#define CH_USE_EVENTS                   TRUE

+#endif

+

+/**

+ * @brief   Events Flags APIs with timeout.

+ * @details If enabled then the events APIs with timeout specification

+ *          are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_USE_EVENTS.

+ */

+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)

+#define CH_USE_EVENTS_TIMEOUT           FALSE

+#endif

+

+/**

+ * @brief   Synchronous Messages APIs.

+ * @details If enabled then the synchronous messages APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)

+#define CH_USE_MESSAGES                 TRUE

+#endif

+

+/**

+ * @brief   Synchronous Messages queuing mode.

+ * @details If enabled then messages are served by priority rather than in

+ *          FIFO order.

+ *

+ * @note    The default is @p FALSE. Enable this if you have special requirements.

+ * @note    Requires @p CH_USE_MESSAGES.

+ */

+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)

+#define CH_USE_MESSAGES_PRIORITY        FALSE

+#endif

+

+/**

+ * @brief   Mailboxes APIs.

+ * @details If enabled then the asynchronous messages (mailboxes) APIs are

+ *          included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_USE_SEMAPHORES.

+ */

+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)

+#define CH_USE_MAILBOXES                TRUE

+#endif

+

+/**

+ * @brief   I/O Queues APIs.

+ * @details If enabled then the I/O queues APIs are included in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)

+#define CH_USE_QUEUES                   TRUE

+#endif

+

+/**

+ * @brief   Core Memory Manager APIs.

+ * @details If enabled then the core memory manager APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)

+#define CH_USE_MEMCORE                  TRUE

+#endif

+

+/**

+ * @brief   Heap Allocator APIs.

+ * @details If enabled then the memory heap allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or

+ *          @p CH_USE_SEMAPHORES.

+ * @note    Mutexes are recommended.

+ */

+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)

+#define CH_USE_HEAP                     FALSE

+#endif

+

+/**

+ * @brief   C-runtime allocator.

+ * @details If enabled the the heap allocator APIs just wrap the C-runtime

+ *          @p malloc() and @p free() functions.

+ *

+ * @note    The default is @p FALSE.

+ * @note    Requires @p CH_USE_HEAP.

+ * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the

+ *          appropriate documentation.

+ */

+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)

+#define CH_USE_MALLOC_HEAP              FALSE

+#endif

+

+/**

+ * @brief   Memory Pools Allocator APIs.

+ * @details If enabled then the memory pools allocator APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ */

+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)

+#define CH_USE_MEMPOOLS                 TRUE

+#endif

+

+/**

+ * @brief   Dynamic Threads APIs.

+ * @details If enabled then the dynamic threads creation APIs are included

+ *          in the kernel.

+ *

+ * @note    The default is @p TRUE.

+ * @note    Requires @p CH_USE_WAITEXIT.

+ * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.

+ */

+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)

+#define CH_USE_DYNAMIC                  FALSE

+#endif

+

+/*===========================================================================*/

+/* Debug options.                                                            */

+/*===========================================================================*/

+/**

+ * @brief   Debug option, system state check.

+ * @details If enabled the correct call protocol for system APIs is checked

+ *          at runtime.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)

+#define CH_DBG_SYSTEM_STATE_CHECK       TRUE

+#endif

+

+/**

+ * @brief   Debug option, parameters checks.

+ * @details If enabled then the checks on the API functions input

+ *          parameters are activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)

+#define CH_DBG_ENABLE_CHECKS            TRUE

+#endif

+

+/**

+ * @brief   Debug option, consistency checks.

+ * @details If enabled then all the assertions in the kernel code are

+ *          activated. This includes consistency checks inside the kernel,

+ *          runtime anomalies and port-defined checks.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)

+#define CH_DBG_ENABLE_ASSERTS           TRUE

+#endif

+

+/**

+ * @brief   Debug option, trace buffer.

+ * @details If enabled then the context switch circular trace buffer is

+ *          activated.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)

+#define CH_DBG_ENABLE_TRACE             TRUE

+#endif

+

+/**

+ * @brief   Debug option, stack checks.

+ * @details If enabled then a runtime stack check is performed.

+ *

+ * @note    The default is @p FALSE.

+ * @note    The stack check is performed in a architecture/port dependent way.

+ *          It may not be implemented or some ports.

+ * @note    The default failure mode is to halt the system with the global

+ *          @p panic_msg variable set to @p NULL.

+ */

+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)

+#define CH_DBG_ENABLE_STACK_CHECK       TRUE

+#endif

+

+/**

+ * @brief   Debug option, stacks initialization.

+ * @details If enabled then the threads working area is filled with a byte

+ *          value when a thread is created. This can be useful for the

+ *          runtime measurement of the used stack.

+ *

+ * @note    The default is @p FALSE.

+ */

+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)

+#define CH_DBG_FILL_THREADS             TRUE

+#endif

+

+/**

+ * @brief   Debug option, threads profiling.

+ * @details If enabled then a field is added to the @p Thread structure that

+ *          counts the system ticks occurred while executing the thread.

+ *

+ * @note    The default is @p TRUE.

+ * @note    This debug option is defaulted to TRUE because it is required by

+ *          some test cases into the test suite.

+ */

+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)

+#define CH_DBG_THREADS_PROFILING        TRUE

+#endif

+

+/*===========================================================================*/

+/* Kernel hooks.                                                             */

+/*===========================================================================*/

+

+/**

+ * @brief   Threads descriptor structure extension.

+ * @details User fields added to the end of the @p Thread structure.

+ */

+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)

+#define THREAD_EXT_FIELDS                                                   \

+  /* Add threads custom fields here.*/

+#endif

+

+/**

+ * @brief   Threads initialization hook.

+ * @details User initialization code added to the @p chThdInit() API.

+ *

+ * @note    It is invoked from within @p chThdInit() and implicitily from all

+ *          the threads creation APIs.

+ */

+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)

+#define THREAD_EXT_INIT_HOOK(tp) {                                          \

+  /* Add threads initialization code here.*/                                \

+}

+#endif

+

+/**

+ * @brief   Threads finalization hook.

+ * @details User finalization code added to the @p chThdExit() API.

+ *

+ * @note    It is inserted into lock zone.

+ * @note    It is also invoked when the threads simply return in order to

+ *          terminate.

+ */

+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)

+#define THREAD_EXT_EXIT_HOOK(tp) {                                          \

+  /* Add threads finalization code here.*/                                  \

+}

+#endif

+

+/**

+ * @brief   Context switch hook.

+ * @details This hook is invoked just before switching between threads.

+ */

+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)

+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \

+  /* System halt code here.*/                                               \

+}

+#endif

+

+/**

+ * @brief   Idle Loop hook.

+ * @details This hook is continuously invoked by the idle thread loop.

+ */

+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)

+#define IDLE_LOOP_HOOK() {                                                  \

+  /* Idle loop code here.*/                                                 \

+}

+#endif

+

+/**

+ * @brief   System tick event hook.

+ * @details This hook is invoked in the system tick handler immediately

+ *          after processing the virtual timers queue.

+ */

+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)

+#define SYSTEM_TICK_EVENT_HOOK() {                                          \

+  /* System tick event code here.*/                                         \

+}

+#endif

+

+/**

+ * @brief   System halt hook.

+ * @details This hook is invoked in case to a system halting error before

+ *          the system is halted.

+ */

+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)

+#define SYSTEM_HALT_HOOK() {                                                \

+  /* System halt code here.*/                                               \

+}

+#endif

+

+/*===========================================================================*/

+/* Port-specific settings (override port settings defaulted in chcore.h).    */

+/*===========================================================================*/

+

+#endif  /* _CHCONF_H_ */

+

+/** @} */

diff --git a/testhal/STM32F4xx/I2C/halconf.h b/testhal/STM32F4xx/I2C/halconf.h
new file mode 100644
index 000000000..5e8e3fc98
--- /dev/null
+++ b/testhal/STM32F4xx/I2C/halconf.h
@@ -0,0 +1,349 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    templates/halconf.h

+ * @brief   HAL configuration header.

+ * @details HAL configuration file, this file allows to enable or disable the

+ *          various device drivers from your application. You may also use

+ *          this file in order to override the device drivers default settings.

+ *

+ * @addtogroup HAL_CONF

+ * @{

+ */

+

+#ifndef _HALCONF_H_

+#define _HALCONF_H_

+

+#include "mcuconf.h"

+

+/**

+ * @brief   Enables the PAL subsystem.

+ */

+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)

+#define HAL_USE_PAL                 TRUE

+#endif

+

+/**

+ * @brief   Enables the ADC subsystem.

+ */

+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)

+#define HAL_USE_ADC                 TRUE

+#endif

+

+/**

+ * @brief   Enables the CAN subsystem.

+ */

+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)

+#define HAL_USE_CAN                 FALSE

+#endif

+

+/**

+ * @brief   Enables the EXT subsystem.

+ */

+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)

+#define HAL_USE_EXT                 TRUE

+#endif

+

+/**

+ * @brief   Enables the GPT subsystem.

+ */

+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)

+#define HAL_USE_GPT                 FALSE

+#endif

+

+/**

+ * @brief   Enables the I2C subsystem.

+ */

+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)

+#define HAL_USE_I2C                 TRUE

+#endif

+

+/**

+ * @brief   Enables the ICU subsystem.

+ */

+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)

+#define HAL_USE_ICU                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MAC subsystem.

+ */

+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)

+#define HAL_USE_MAC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the MMC_SPI subsystem.

+ */

+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_MMC_SPI             FALSE

+#endif

+

+/**

+ * @brief   Enables the PWM subsystem.

+ */

+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)

+#define HAL_USE_PWM                 TRUE

+#endif

+

+/**

+ * @brief   Enables the SDC subsystem.

+ */

+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)

+#define HAL_USE_SDC                 FALSE

+#endif

+

+/**

+ * @brief   Enables the SERIAL subsystem.

+ */

+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL              TRUE

+#endif

+

+/**

+ * @brief   Enables the SERIAL over USB subsystem.

+ */

+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)

+#define HAL_USE_SERIAL_USB          FALSE

+#endif

+

+/**

+ * @brief   Enables the SPI subsystem.

+ */

+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)

+#define HAL_USE_SPI                 FALSE

+#endif

+

+/**

+ * @brief   Enables the UART subsystem.

+ */

+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)

+#define HAL_USE_UART                FALSE

+#endif

+

+/**

+ * @brief   Enables the USB subsystem.

+ */

+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)

+#define HAL_USE_USB                 FALSE

+#endif

+

+/**

+ * @brief   Enables the RTC subsystem.

+ */

+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)

+#define HAL_USE_RTC                 TRUE

+#endif

+

+/**

+ * @brief   Enables the RTC subsystem.

+ */

+#if !defined(RTC_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__)

+#define RTC_SUPPORTS_CALLBACKS      FLASE

+#endif

+

+/*===========================================================================*/

+/* ADC driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)

+#define ADC_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define ADC_USE_MUTUAL_EXCLUSION    FALSE

+#endif

+

+/*===========================================================================*/

+/* CAN driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Sleep mode related APIs inclusion switch.

+ */

+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)

+#define CAN_USE_SLEEP_MODE          TRUE

+#endif

+

+/*===========================================================================*/

+/* I2C driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the mutual exclusion APIs on the I2C bus.

+ */

+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define I2C_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* RTC driver related settings.                                              */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* MAC driver related settings.                                              */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* MMC_SPI driver related settings.                                          */

+/*===========================================================================*/

+

+/**

+ * @brief   Block size for MMC transfers.

+ */

+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)

+#define MMC_SECTOR_SIZE             512

+#endif

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ *          This option is recommended also if the SPI driver does not

+ *          use a DMA channel and heavily loads the CPU.

+ */

+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)

+#define MMC_NICE_WAITING            TRUE

+#endif

+

+/**

+ * @brief   Number of positive insertion queries before generating the

+ *          insertion event.

+ */

+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)

+#define MMC_POLLING_INTERVAL        10

+#endif

+

+/**

+ * @brief   Interval, in milliseconds, between insertion queries.

+ */

+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)

+#define MMC_POLLING_DELAY           10

+#endif

+

+/**

+ * @brief   Uses the SPI polled API for small data transfers.

+ * @details Polled transfers usually improve performance because it

+ *          saves two context switches and interrupt servicing. Note

+ *          that this option has no effect on large transfers which

+ *          are always performed using DMAs/IRQs.

+ */

+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)

+#define MMC_USE_SPI_POLLING         TRUE

+#endif

+

+/*===========================================================================*/

+/* PAL driver related settings.                                              */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* PWM driver related settings.                                              */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* SDC driver related settings.                                              */

+/*===========================================================================*/

+/**

+ * @brief   Number of initialization attempts before rejecting the card.

+ * @note    Attempts are performed at 10mS intevals.

+ */

+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)

+#define SDC_INIT_RETRY              100

+#endif

+

+/**

+ * @brief   Include support for MMC cards.

+ * @note    MMC support is not yet implemented so this option must be kept

+ *          at @p FALSE.

+ */

+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)

+#define SDC_MMC_SUPPORT             FALSE

+#endif

+

+/**

+ * @brief   Delays insertions.

+ * @details If enabled this options inserts delays into the MMC waiting

+ *          routines releasing some extra CPU time for the threads with

+ *          lower priority, this may slow down the driver a bit however.

+ */

+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)

+#define SDC_NICE_WAITING            TRUE

+#endif

+

+/*===========================================================================*/

+/* SERIAL driver related settings.                                           */

+/*===========================================================================*/

+

+/**

+ * @brief   Default bit rate.

+ * @details Configuration parameter, this is the baud rate selected for the

+ *          default configuration.

+ */

+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)

+#define SERIAL_DEFAULT_BITRATE      115200

+#endif

+

+/**

+ * @brief   Serial buffers size.

+ * @details Configuration parameter, you can change the depth of the queue

+ *          buffers depending on the requirements of your application.

+ * @note    The default is 64 bytes for both the transmission and receive

+ *          buffers.

+ */

+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)

+#define SERIAL_BUFFERS_SIZE         16

+#endif

+

+/*===========================================================================*/

+/* SPI driver related settings.                                              */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables synchronous APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)

+#define SPI_USE_WAIT                TRUE

+#endif

+

+/**

+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.

+ * @note    Disabling this option saves both code and data space.

+ */

+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define SPI_USE_MUTUAL_EXCLUSION    FALSE

+#endif

+

+/*===========================================================================*/

+/* UART driver related settings.                                             */

+/*===========================================================================*/

+

+#endif /* _HALCONF_H_ */

+

+/** @} */

diff --git a/testhal/STM32F4xx/I2C/main.c b/testhal/STM32F4xx/I2C/main.c
new file mode 100644
index 000000000..9caff15ec
--- /dev/null
+++ b/testhal/STM32F4xx/I2C/main.c
@@ -0,0 +1,167 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+#include <stdlib.h>

+

+#include "ch.h"

+#include "hal.h"

+

+/* buffers depth */

+#define ACCEL_RX_DEPTH 6

+#define ACCEL_TX_DEPTH 4

+

+/* mma8451q specific addresses */

+#define ACCEL_OUT_DATA    0x01

+#define ACCEL_CTRL_REG1   0x2A

+

+static uint8_t rxbuf[ACCEL_RX_DEPTH];

+static uint8_t txbuf[ACCEL_TX_DEPTH];

+static i2cflags_t errors = 0;

+static int16_t acceleration_x, acceleration_y, acceleration_z;

+#define mma8451_addr 0b0011100

+

+/**

+ *

+ */

+static void print(char *p) {

+

+  while (*p) {

+    chIOPut(&SD2, *p++);

+  }

+}

+

+/**

+ *

+ */

+static void println(char *p) {

+

+  while (*p) {

+    chIOPut(&SD2, *p++);

+  }

+  chIOWriteTimeout(&SD2, (uint8_t *)"\r\n", 2, TIME_INFINITE);

+}

+

+/**

+ *

+ */

+static void printn(int16_t n) {

+  char buf[16], *p;

+

+  if (n > 0)

+    chIOPut(&SD2, '+');

+  else{

+    chIOPut(&SD2, '-');

+    n = abs(n);

+  }

+

+  if (!n)

+    chIOPut(&SD2, '0');

+  else {

+    p = buf;

+    while (n)

+      *p++ = (n % 10) + '0', n /= 10;

+    while (p > buf)

+      chIOPut(&SD2, *--p);

+  }

+}

+

+/**

+ * Converts data from 2complemented representation to signed integer

+ */

+int16_t complement2signed(uint8_t msb, uint8_t lsb){

+  uint16_t word = 0;

+  word = (msb << 8) + lsb;

+  if (msb > 0x7F){

+    return -1 * ((int16_t)((~word) + 1));

+  }

+  return (int16_t)word;

+}

+

+/*

+ * Application entry point.

+ */

+int main(void) {

+  msg_t status = RDY_OK;

+

+  /*

+   * System initializations.

+   * - HAL initialization, this also initializes the configured device drivers

+   *   and performs the board-specific initializations.

+   * - Kernel initialization, the main() function becomes a thread and the

+   *   RTOS is active.

+   */

+  halInit();

+  chSysInit();

+

+  /*

+   * Prepares the Serial driver 2

+   */

+  sdStart(&SD2, NULL);          /* Default is 38400-8-N-1.*/

+  palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7));

+  palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7));

+

+  /* I2C interface #2 */

+  static const I2CConfig i2cfg2 = {

+      OPMODE_I2C,

+      400000,

+      FAST_DUTY_CYCLE_16_9,

+  };

+  i2cStart(&I2CD2, &i2cfg2);

+

+  /**

+   * Prepares the accelerometer

+   */

+  txbuf[0] = ACCEL_CTRL_REG1; // register address

+  txbuf[1] = 0x1;

+  i2cAcquireBus(&I2CD2);

+  i2cMasterTransmitTimeout(&I2CD2, mma8451_addr, txbuf, 2, rxbuf, 0, TIME_INFINITE);

+  i2cReleaseBus(&I2CD2);

+

+  /*

+   * Normal main() thread activity, nothing in this test.

+   */

+  while (TRUE) {

+    chThdSleepMilliseconds(100);

+

+    txbuf[0] = ACCEL_OUT_DATA; // register address

+    i2cAcquireBus(&I2CD2);

+    status = i2cMasterTransmitTimeout(&I2CD2, mma8451_addr, txbuf, 1, rxbuf, 6, TIME_INFINITE);

+    i2cReleaseBus(&I2CD2);

+

+    if (status != RDY_OK){

+      errors = i2cGetErrors(&I2CD2);

+    }

+

+    acceleration_x = complement2signed(rxbuf[0], rxbuf[1]);

+    acceleration_y = complement2signed(rxbuf[2], rxbuf[3]);

+    acceleration_z = complement2signed(rxbuf[4], rxbuf[5]);

+

+    print("x: ");

+    printn(acceleration_x);

+    print(" y: ");

+    printn(acceleration_y);

+    print(" z: ");

+    printn(acceleration_z);

+    println("");

+  }

+}

+

+

+

diff --git a/testhal/STM32F4xx/I2C/mcuconf.h b/testhal/STM32F4xx/I2C/mcuconf.h
new file mode 100644
index 000000000..ccfb67fdf
--- /dev/null
+++ b/testhal/STM32F4xx/I2C/mcuconf.h
@@ -0,0 +1,244 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/*

+ * STM32F4xx drivers configuration.

+ * The following settings override the default settings present in

+ * the various device driver implementation headers.

+ * Note that the settings for each driver only have effect if the whole

+ * driver is enabled in halconf.h.

+ *

+ * IRQ priorities:

+ * 15...0       Lowest...Highest.

+ *

+ * DMA priorities:

+ * 0...3        Lowest...Highest.

+ */

+

+/*

+ * HAL driver system settings.

+ */

+#define STM32_NO_INIT                       FALSE

+#define STM32_VOS                           STM32_VOS_HIGH

+#define STM32_PLS                           STM32_PLS_LEV0

+#define STM32_PVD_ENABLE                    TRUE

+#define STM32_HSI_ENABLED                   TRUE

+#define STM32_LSI_ENABLED                   FALSE

+#define STM32_HSE_ENABLED                   TRUE

+#define STM32_LSE_ENABLED                   TRUE

+#define STM32_CLOCK48_REQUIRED              TRUE

+#define STM32_SW                            STM32_SW_PLL

+#define STM32_PLLSRC                        STM32_PLLSRC_HSE

+#define STM32_PLLM_VALUE                    8

+#define STM32_PLLN_VALUE                    336

+#define STM32_PLLP_VALUE                    2

+#define STM32_PLLQ_VALUE                    7

+#define STM32_HPRE                          STM32_HPRE_DIV1

+#define STM32_PPRE1                         STM32_PPRE1_DIV4

+#define STM32_PPRE2                         STM32_PPRE2_DIV2

+#define STM32_RTCSEL                        STM32_RTCSEL_LSE

+#define STM32_RTCPRE_VALUE                  8

+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI

+#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1

+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK

+#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5

+#define STM32_I2SSRC                        STM32_I2CSRC_CKIN

+#define STM32_PLLI2SN_VALUE                 192

+#define STM32_PLLI2SR_VALUE                 5

+#define STM32_RTC                           STM32_RTC_LSE

+

+

+/*

+ * ADC driver system settings.

+ */

+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV2

+#define STM32_ADC_USE_ADC1                  TRUE

+#define STM32_ADC_USE_ADC2                  TRUE

+#define STM32_ADC_USE_ADC3                  TRUE

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)

+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)

+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)

+#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_ADC3_DMA_PRIORITY         2

+#define STM32_ADC_IRQ_PRIORITY              5

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

+

+/*

+ * CAN driver system settings.

+ */

+#define STM32_CAN_USE_CAN1                  FLASE

+#define STM32_CAN_CAN1_IRQ_PRIORITY         11

+

+/*

+ * EXT driver system settings.

+ */

+#define STM32_EXT_EXTI0_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI1_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI2_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI3_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI4_IRQ_PRIORITY        6

+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6

+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6

+#define STM32_EXT_EXTI16_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI17_IRQ_PRIORITY       15 // RTC alarm

+#define STM32_EXT_EXTI18_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI19_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI20_IRQ_PRIORITY       6

+#define STM32_EXT_EXTI21_IRQ_PRIORITY       15 // RTC tamper-timestamp

+#define STM32_EXT_EXTI22_IRQ_PRIORITY       15 // RTC wakeup

+

+/*

+ * GPT driver system settings.

+ */

+#define STM32_GPT_USE_TIM1                  FALSE

+#define STM32_GPT_USE_TIM2                  FALSE

+#define STM32_GPT_USE_TIM3                  FALSE

+#define STM32_GPT_USE_TIM4                  FALSE

+#define STM32_GPT_USE_TIM5                  FALSE

+#define STM32_GPT_USE_TIM8                  FALSE

+#define STM32_GPT_USE_TIM9                  FALSE

+#define STM32_GPT_USE_TIM10                 FALSE

+#define STM32_GPT_USE_TIM11                 FALSE

+#define STM32_GPT_USE_TIM12                 FALSE

+#define STM32_GPT_USE_TIM12                 FALSE

+#define STM32_GPT_USE_TIM14                 FALSE

+

+#define STM32_GPT_TIM1_IRQ_PRIORITY         7

+#define STM32_GPT_TIM2_IRQ_PRIORITY         7

+#define STM32_GPT_TIM3_IRQ_PRIORITY         7

+#define STM32_GPT_TIM4_IRQ_PRIORITY         7

+#define STM32_GPT_TIM5_IRQ_PRIORITY         7

+#define STM32_GPT_TIM8_IRQ_PRIORITY         7

+

+/*

+ * ICU driver system settings.

+ */

+#define STM32_ICU_USE_TIM1                  FALSE

+#define STM32_ICU_USE_TIM2                  FALSE

+#define STM32_ICU_USE_TIM3                  FALSE

+#define STM32_ICU_USE_TIM4                  FALSE

+#define STM32_ICU_USE_TIM5                  FALSE

+#define STM32_ICU_USE_TIM8                  FALSE

+#define STM32_ICU_TIM1_IRQ_PRIORITY         7

+#define STM32_ICU_TIM2_IRQ_PRIORITY         7

+#define STM32_ICU_TIM3_IRQ_PRIORITY         7

+#define STM32_ICU_TIM4_IRQ_PRIORITY         7

+#define STM32_ICU_TIM5_IRQ_PRIORITY         7

+#define STM32_ICU_TIM8_IRQ_PRIORITY         7

+

+/*

+ * PWM driver system settings.

+ */

+#define STM32_PWM_USE_ADVANCED              FALSE

+#define STM32_PWM_USE_TIM1                  FALSE

+#define STM32_PWM_USE_TIM2                  FALSE

+#define STM32_PWM_USE_TIM3                  TRUE

+#define STM32_PWM_USE_TIM4                  TRUE

+#define STM32_PWM_USE_TIM5                  FALSE

+#define STM32_PWM_USE_TIM8                  FLASE

+#define STM32_PWM_TIM1_IRQ_PRIORITY         7

+#define STM32_PWM_TIM2_IRQ_PRIORITY         7

+#define STM32_PWM_TIM3_IRQ_PRIORITY         7

+#define STM32_PWM_TIM4_IRQ_PRIORITY         7

+#define STM32_PWM_TIM5_IRQ_PRIORITY         7

+#define STM32_PWM_TIM8_IRQ_PRIORITY         7

+

+/*

+ * SERIAL driver system settings.

+ */

+#define STM32_SERIAL_USE_USART1             TRUE

+#define STM32_SERIAL_USE_USART2             TRUE

+#define STM32_SERIAL_USE_USART3             FALSE

+#define STM32_SERIAL_USE_UART4              FALSE

+#define STM32_SERIAL_USE_UART5              FALSE

+#define STM32_SERIAL_USE_USART6             FALSE

+#define STM32_SERIAL_USART1_PRIORITY        12

+#define STM32_SERIAL_USART2_PRIORITY        12

+#define STM32_SERIAL_USART3_PRIORITY        12

+#define STM32_SERIAL_UART4_PRIORITY         12

+#define STM32_SERIAL_UART5_PRIORITY         12

+#define STM32_SERIAL_USART6_PRIORITY        12

+

+/*

+ * SPI driver system settings.

+ */

+#define STM32_SPI_USE_SPI1                  FLASE

+#define STM32_SPI_USE_SPI2                  FLASE

+#define STM32_SPI_USE_SPI3                  FLASE

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

+#define STM32_SPI_SPI1_DMA_PRIORITY         1

+#define STM32_SPI_SPI2_DMA_PRIORITY         1

+#define STM32_SPI_SPI3_DMA_PRIORITY         1

+#define STM32_SPI_SPI1_IRQ_PRIORITY         10

+#define STM32_SPI_SPI2_IRQ_PRIORITY         10

+#define STM32_SPI_SPI3_IRQ_PRIORITY         10

+#define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()

+

+/*

+ * UART driver system settings.

+ */

+#define STM32_UART_USE_USART1               FALSE

+#define STM32_UART_USE_USART2               FALSE

+#define STM32_UART_USE_USART3               FALSE

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

+#define STM32_UART_USART1_IRQ_PRIORITY      12

+#define STM32_UART_USART2_IRQ_PRIORITY      12

+#define STM32_UART_USART3_IRQ_PRIORITY      12

+#define STM32_UART_USART1_DMA_PRIORITY      0

+#define STM32_UART_USART2_DMA_PRIORITY      0

+#define STM32_UART_USART3_DMA_PRIORITY      0

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()

+

+

+/*

+ * I2C driver system settings.

+ */

+#define STM32_I2C_USE_I2C1                  FALSE

+#define STM32_I2C_USE_I2C2                  TRUE

+#define STM32_I2C_USE_I2C3                  FALSE

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_I2C_I2C1_IRQ_PRIORITY         6

+#define STM32_I2C_I2C2_IRQ_PRIORITY         6

+#define STM32_I2C_I2C3_IRQ_PRIORITY         6

+#define STM32_I2C_I2C1_DMA_PRIORITY         1

+#define STM32_I2C_I2C2_DMA_PRIORITY         1

+#define STM32_I2C_I2C3_DMA_PRIORITY         1

+#define STM32_I2C_I2C1_DMA_ERROR_HOOK()     chSysHalt()

+#define STM32_I2C_I2C2_DMA_ERROR_HOOK()     chSysHalt()

+#define STM32_I2C_I2C3_DMA_ERROR_HOOK()     chSysHalt()

+