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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-10-13 11:45:07 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-10-13 11:45:07 +0000
commit4fab7c06d1b0c9e61f6106b5b2a5c2c0b5694c34 (patch)
treee7fdadc85d78aa2143d0082d26351da49f7f2d53 /testhal
parentec7455babe131ee0b8a4c228ed00a02396619a7d (diff)
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ADC, SPI, PWM driver enhancements.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2254 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal')
-rw-r--r--testhal/STM32/PWM/main.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/testhal/STM32/PWM/main.c b/testhal/STM32/PWM/main.c
index 287c6c43d..7f66a114e 100644
--- a/testhal/STM32/PWM/main.c
+++ b/testhal/STM32/PWM/main.c
@@ -54,8 +54,8 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL},
{PWM_OUTPUT_DISABLED, NULL}
},
- (uint16_t)(STM32_TIMCLK2 / 10000 - 1), /* 100 uS clock.*/
- (uint16_t)(10000 - 1), /* Period 1S.*/
+ PWM_COMPUTE_PSC(STM32_TIMCLK2, 100000), /* 100000 nS clock cycle. */
+ PWM_COMPUTE_ARR(100000, 1000000000), /* PWM period 1S. */
0
};
@@ -81,15 +81,15 @@ int main(int argc, char **argv) {
chThdSleepMilliseconds(2000);
/*
- * Starts the channel 0 with 50% duty cycle.
+ * Starts the channel 0 using 50% duty cycle.
*/
- pwmEnableChannel(&PWMD1, 0, 4999); /* 50% */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000));
chThdSleepMilliseconds(5000);
/*
- * Changes the channel 0 with 75% duty cycle.
+ * Changes the channel 0 to 75% duty cycle.
*/
- pwmEnableChannel(&PWMD1, 0, 7499); /* 75% */
+ pwmEnableChannel(&PWMD1, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500));
chThdSleepMilliseconds(5000);
/*