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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-06-17 07:01:48 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-06-17 07:01:48 +0000
commit1a76b0008ff6dabc22e1f7b07dcee8f1c38c7b2c (patch)
tree50fa62b7a6cc4d11bcaed5f68bdd3e91c5172f65 /testhal
parente02105736dcf810de5855bc5a5fd40bf7727c852 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5863 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal')
-rw-r--r--testhal/SPC560Dxx/SPI/mcuconf.h6
-rw-r--r--testhal/SPC560Pxx/PWM-ICU/mcuconf.h15
-rw-r--r--testhal/SPC560Pxx/SPI/mcuconf.h15
-rw-r--r--testhal/SPC56ELxx/PWM-ICU/mcuconf.h9
-rw-r--r--testhal/SPC56ELxx/SPI/mcuconf.h9
5 files changed, 54 insertions, 0 deletions
diff --git a/testhal/SPC560Dxx/SPI/mcuconf.h b/testhal/SPC560Dxx/SPI/mcuconf.h
index 166be874b..320ca274b 100644
--- a/testhal/SPC560Dxx/SPI/mcuconf.h
+++ b/testhal/SPC560Dxx/SPI/mcuconf.h
@@ -215,6 +215,12 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI0_IRQ_PRIO 10
diff --git a/testhal/SPC560Pxx/PWM-ICU/mcuconf.h b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h
index ae770ef86..1fb614e35 100644
--- a/testhal/SPC560Pxx/PWM-ICU/mcuconf.h
+++ b/testhal/SPC560Pxx/PWM-ICU/mcuconf.h
@@ -265,6 +265,21 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15
+#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 1
+#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 2
+#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 3
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
diff --git a/testhal/SPC560Pxx/SPI/mcuconf.h b/testhal/SPC560Pxx/SPI/mcuconf.h
index ba5720366..ebb8f6420 100644
--- a/testhal/SPC560Pxx/SPI/mcuconf.h
+++ b/testhal/SPC560Pxx/SPI/mcuconf.h
@@ -265,6 +265,21 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15
+#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 1
+#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 2
+#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 3
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
diff --git a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h
index 221ad245e..688a5def2 100644
--- a/testhal/SPC56ELxx/PWM-ICU/mcuconf.h
+++ b/testhal/SPC56ELxx/PWM-ICU/mcuconf.h
@@ -259,6 +259,15 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
diff --git a/testhal/SPC56ELxx/SPI/mcuconf.h b/testhal/SPC56ELxx/SPI/mcuconf.h
index 322a9be56..6f22f2d18 100644
--- a/testhal/SPC56ELxx/SPI/mcuconf.h
+++ b/testhal/SPC56ELxx/SPI/mcuconf.h
@@ -259,6 +259,15 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10