diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-08-21 16:09:14 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-08-21 16:09:14 +0000 |
| commit | 35cae2a2900298061c197a19e0b6eace8eaa9312 (patch) | |
| tree | 839366768dd7adc1a6687818cd59a76c55956359 /testhal/STM32F4xx/RTC/mcuconf.h | |
| parent | 79ec800cb608672f38f013ed8302aa6ad72016d0 (diff) | |
| download | ChibiOS-35cae2a2900298061c197a19e0b6eace8eaa9312.tar.gz ChibiOS-35cae2a2900298061c197a19e0b6eace8eaa9312.tar.bz2 ChibiOS-35cae2a2900298061c197a19e0b6eace8eaa9312.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4607 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/STM32F4xx/RTC/mcuconf.h')
| -rw-r--r-- | testhal/STM32F4xx/RTC/mcuconf.h | 68 |
1 files changed, 43 insertions, 25 deletions
diff --git a/testhal/STM32F4xx/RTC/mcuconf.h b/testhal/STM32F4xx/RTC/mcuconf.h index bf75a124c..b95361bad 100644 --- a/testhal/STM32F4xx/RTC/mcuconf.h +++ b/testhal/STM32F4xx/RTC/mcuconf.h @@ -32,12 +32,14 @@ * 0...3 Lowest...Highest.
*/
+#define STM32F4xx_MCUCONF
+
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
-#define STM32_LSI_ENABLED FALSE
+#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_CLOCK48_REQUIRED TRUE
@@ -84,8 +86,10 @@ /*
* CAN driver system settings.
*/
-#define STM32_CAN_USE_CAN1 FLASE
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* EXT driver system settings.
@@ -122,6 +126,28 @@ #define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
+
+/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
@@ -146,7 +172,7 @@ #define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
-#define STM32_PWM_USE_TIM8 FLASE
+#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
@@ -173,9 +199,9 @@ /*
* SPI driver system settings.
*/
-#define STM32_SPI_USE_SPI1 FLASE
-#define STM32_SPI_USE_SPI2 FLASE
-#define STM32_SPI_USE_SPI3 FLASE
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
@@ -216,24 +242,16 @@ #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
/*
- * I2C driver system settings.
+ * USB driver system settings.
*/
-#define STM32_I2C_USE_I2C1 FALSE
-#define STM32_I2C_USE_I2C2 FALSE
-#define STM32_I2C_USE_I2C3 FALSE
-#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
-#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
-#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_I2C_I2C1_IRQ_PRIORITY 5
-#define STM32_I2C_I2C2_IRQ_PRIORITY 5
-#define STM32_I2C_I2C3_IRQ_PRIORITY 5
-#define STM32_I2C_I2C1_DMA_PRIORITY 3
-#define STM32_I2C_I2C2_DMA_PRIORITY 3
-#define STM32_I2C_I2C3_DMA_PRIORITY 3
-#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
-#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
-#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
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