aboutsummaryrefslogtreecommitdiffstats
path: root/testhal/STM32
diff options
context:
space:
mode:
authorGiovanni Di Sirio <gdisirio@gmail.com>2015-12-14 11:40:18 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2015-12-14 11:40:18 +0000
commitd0487d83cf9d96baae56c100ee5f930367756a32 (patch)
tree9522bdebdff347f758b3d4b92459dc66ca797dd9 /testhal/STM32
parent5c2d8efab35edb7051d63a05fb473a3d28ead047 (diff)
downloadChibiOS-d0487d83cf9d96baae56c100ee5f930367756a32.tar.gz
ChibiOS-d0487d83cf9d96baae56c100ee5f930367756a32.tar.bz2
ChibiOS-d0487d83cf9d96baae56c100ee5f930367756a32.zip
ADCv3 working on L4 in single mode.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8598 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/STM32')
-rw-r--r--testhal/STM32/STM32L4xx/GPT-ADC/main.c23
-rw-r--r--testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h3
2 files changed, 4 insertions, 22 deletions
diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/main.c b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
index ca691c205..bc695e55a 100644
--- a/testhal/STM32/STM32L4xx/GPT-ADC/main.c
+++ b/testhal/STM32/STM32L4xx/GPT-ADC/main.c
@@ -17,10 +17,6 @@
#include "ch.h"
#include "hal.h"
-/* TRUE means that DMA-accessible buffers are placed in a non-cached RAM
- area and that no cache management is required.*/
-#define DMA_BUFFERS_COHERENCE TRUE
-
/*===========================================================================*/
/* GPT driver related. */
/*===========================================================================*/
@@ -42,16 +38,7 @@ static const GPTConfig gpt4cfg1 = {
#define ADC_GRP1_NUM_CHANNELS 2
#define ADC_GRP1_BUF_DEPTH 64
-#if !DMA_BUFFERS_COHERENCE
-/* Note, the buffer is aligned to a 32 bytes boundary because limitations
- imposed by the data cache. Note, this is GNU specific, it must be
- handled differently for other compilers.
- Only required if the ADC buffer is placed in a cache-able area.*/
-#if defined(__GNUC__)
-__attribute__((aligned (32)))
-#endif
-#endif
-static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
+adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
/*
* ADC streaming callback.
@@ -59,15 +46,7 @@ static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
size_t nx = 0, ny = 0;
static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
-#if !DMA_BUFFERS_COHERENCE
- /* DMA buffer invalidation because data cache, only invalidating the
- half buffer just filled.
- Only required if the ADC buffer is placed in a cache-able area.*/
- dmaBufferInvalidate(buffer,
- n * adcp->grpp->num_channels * sizeof (adcsample_t));
-#else
(void)adcp;
-#endif
/* Updating counters.*/
if (samples1 == buffer) {
diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
index 37c92b087..eb0ce6b18 100644
--- a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
+++ b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h
@@ -99,6 +99,9 @@
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2