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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-12-30 13:04:09 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-12-30 13:04:09 +0000 |
| commit | afec43446f5210546490f4289e15bdd78405c94a (patch) | |
| tree | 41cd47d03c749868f4d9f818250d19f9c833d59a /testhal/STM32 | |
| parent | 13d1d184c8ca5120895935366b21ded41c850177 (diff) | |
| download | ChibiOS-afec43446f5210546490f4289e15bdd78405c94a.tar.gz ChibiOS-afec43446f5210546490f4289e15bdd78405c94a.tar.bz2 ChibiOS-afec43446f5210546490f4289e15bdd78405c94a.zip | |
Fixed H7 ADC clock settings.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12495 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'testhal/STM32')
4 files changed, 4 insertions, 4 deletions
diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h index 87b28c672..da2d83264 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/ADC/cfg/stm32h743_nucleo144/mcuconf.h @@ -92,7 +92,7 @@ #define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0
-#define STM32_PLL2_DIVP_VALUE 8
+#define STM32_PLL2_DIVP_VALUE 40
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL3_ENABLED TRUE
diff --git a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h index 5f1c781a7..0037a4d90 100644 --- a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h @@ -92,7 +92,7 @@ #define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0
-#define STM32_PLL2_DIVP_VALUE 8
+#define STM32_PLL2_DIVP_VALUE 40
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL3_ENABLED TRUE
diff --git a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h index e22dd7fe7..18662c782 100644 --- a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h @@ -92,7 +92,7 @@ #define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0
-#define STM32_PLL2_DIVP_VALUE 8
+#define STM32_PLL2_DIVP_VALUE 40
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL3_ENABLED TRUE
diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h index e642c6301..3920704a5 100644 --- a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h @@ -92,7 +92,7 @@ #define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0
-#define STM32_PLL2_DIVP_VALUE 8
+#define STM32_PLL2_DIVP_VALUE 40
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL3_ENABLED TRUE
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