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| author | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-10-28 16:52:55 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-10-28 16:52:55 +0000 |
| commit | beef652b8946a5fbf4245a0c3a07a411247614ad (patch) | |
| tree | c7cab34905b9286a79fbfb1941c8ee9f7a05b63f /testhal/STM32/multi | |
| parent | 5ead6ec5ff24af03222994d7d1971adeb0e209db (diff) | |
| download | ChibiOS-beef652b8946a5fbf4245a0c3a07a411247614ad.tar.gz ChibiOS-beef652b8946a5fbf4245a0c3a07a411247614ad.tar.bz2 ChibiOS-beef652b8946a5fbf4245a0c3a07a411247614ad.zip | |
Fixed a problem in L4+ PLLSAIx initialization, added options to mcuconf.h, updated mcuconf generator tool.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12397 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'testhal/STM32/multi')
3 files changed, 32 insertions, 0 deletions
diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h index f0aa00c67..62efdd30d 100644 --- a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h @@ -69,11 +69,13 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
+#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
@@ -321,5 +323,18 @@ /*
* WSPI driver system settings.
*/
+#define STM32_WSPI_USE_OCTOSPI1 TRUE
+#define STM32_WSPI_USE_OCTOSPI2 TRUE
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
+#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
#endif /* MCUCONF_H */
diff --git a/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h index 2890bff59..19d359b1a 100644 --- a/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h @@ -69,11 +69,13 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
+#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
@@ -321,5 +323,18 @@ /*
* WSPI driver system settings.
*/
+#define STM32_WSPI_USE_OCTOSPI1 TRUE
+#define STM32_WSPI_USE_OCTOSPI2 TRUE
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL 9
+#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL 10
+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
+#define STM32_WSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
#endif /* MCUCONF_H */
diff --git a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h index b8bbc1345..a54969cb4 100644 --- a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h +++ b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h @@ -69,11 +69,13 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1M_VALUE 1
#define STM32_PLLSAI1N_VALUE 72
#define STM32_PLLSAI1PDIV_VALUE 6
#define STM32_PLLSAI1P_VALUE 7
#define STM32_PLLSAI1Q_VALUE 6
#define STM32_PLLSAI1R_VALUE 6
+#define STM32_PLLSAI2M_VALUE 1
#define STM32_PLLSAI2N_VALUE 72
#define STM32_PLLSAI2PDIV_VALUE 6
#define STM32_PLLSAI2P_VALUE 7
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