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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-08-08 13:51:03 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-08-08 13:51:03 +0000 |
| commit | 2d1ded91fe36fbfa8427ce854d82cc3947789b31 (patch) | |
| tree | 9cfe0386efaa886501ec595de29aa72f0d9ee1bc /testhal/STM32/SPI/main.c | |
| parent | a2cfd2054ad5da4dbf8b583a7eaf164d9dac6006 (diff) | |
| download | ChibiOS-2d1ded91fe36fbfa8427ce854d82cc3947789b31.tar.gz ChibiOS-2d1ded91fe36fbfa8427ce854d82cc3947789b31.tar.bz2 ChibiOS-2d1ded91fe36fbfa8427ce854d82cc3947789b31.zip | |
Added STM32 SPI demo.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2121 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/STM32/SPI/main.c')
| -rw-r--r-- | testhal/STM32/SPI/main.c | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/testhal/STM32/SPI/main.c b/testhal/STM32/SPI/main.c new file mode 100644 index 000000000..1ebf1b45e --- /dev/null +++ b/testhal/STM32/SPI/main.c @@ -0,0 +1,118 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).
+ */
+static const SPIConfig hs_spicfg = {
+ GPIOA,
+ GPIOA_SPI1NSS,
+ 0
+};
+
+/*
+ * Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).
+ */
+static const SPIConfig ls_spicfg = {
+ GPIOA,
+ GPIOA_SPI1NSS,
+ SPI_CR1_BR_2 | SPI_CR1_BR_1
+};
+
+/*
+ * SPI TX and RX buffers. + */
+static uint8_t txbuf[512];
+static uint8_t rxbuf[512];
+
+/*
+ * SPI bus contender 1.
+ */
+static WORKING_AREA(spi_thread_1_wa, 256);
+static msg_t spi_thread_1(void *p) {
+
+ (void)p;
+ while (TRUE) {
+ spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */
+ palClearPad(IOPORT3, GPIOC_LED); /* LED ON. */
+ spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */
+ spiSelect(&SPID1); /* Slave Select assertion. */
+ spiExchange(&SPID1, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
+ spiUnselect(&SPID1); /* Slave Select de-assertion. */
+ spiReleaseBus(&SPID1); /* Ownership release. */
+ }
+ return 0;
+}
+
+/*
+ * SPI bus contender 2.
+ */
+static WORKING_AREA(spi_thread_2_wa, 256);
+static msg_t spi_thread_2(void *p) {
+
+ (void)p;
+ while (TRUE) {
+ spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */
+ palSetPad(IOPORT3, GPIOC_LED); /* LED OFF. */
+ spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */
+ spiSelect(&SPID1); /* Slave Select assertion. */
+ spiExchange(&SPID1, 512,
+ txbuf, rxbuf); /* Atomic transfer operations. */
+ spiUnselect(&SPID1); /* Slave Select de-assertion. */
+ spiReleaseBus(&SPID1); /* Ownership release. */
+ }
+ return 0;
+}
+
+/*
+ * Entry point, note, the main() function is already a thread in the system
+ * on entry.
+ */
+int main(int argc, char **argv) {
+ unsigned i;
+
+ (void)argc;
+ (void)argv;
+
+ /*
+ * Prepare transmit pattern. + */
+ for (i = 0; i < sizeof(txbuf); i++)
+ txbuf[i] = (uint8_t)i;
+
+ /*
+ * Starting the transmitter and receiver threads. + */
+ chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa),
+ NORMALPRIO + 1, spi_thread_1, NULL);
+ chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
+ NORMALPRIO + 1, spi_thread_2, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
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