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| author | isiora <none@example.com> | 2017-10-22 21:46:02 +0000 |
|---|---|---|
| committer | isiora <none@example.com> | 2017-10-22 21:46:02 +0000 |
| commit | d3e3f1d87b9cecc9298c5163b42b6622f5be0856 (patch) | |
| tree | a9764862f55443d83e59f701413c1674a57e215e /testhal/ATSAMA5D2/MATRIX/main.c | |
| parent | afe8d1ee875e5c933efa1494d2dc8fda55e4ed65 (diff) | |
| download | ChibiOS-d3e3f1d87b9cecc9298c5163b42b6622f5be0856.tar.gz ChibiOS-d3e3f1d87b9cecc9298c5163b42b6622f5be0856.tar.bz2 ChibiOS-d3e3f1d87b9cecc9298c5163b42b6622f5be0856.zip | |
Reintegrate sama5d2_dev branch
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10876 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/ATSAMA5D2/MATRIX/main.c')
| -rwxr-xr-x | testhal/ATSAMA5D2/MATRIX/main.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/testhal/ATSAMA5D2/MATRIX/main.c b/testhal/ATSAMA5D2/MATRIX/main.c new file mode 100755 index 000000000..4005a8705 --- /dev/null +++ b/testhal/ATSAMA5D2/MATRIX/main.c @@ -0,0 +1,40 @@ +#include "ch.h"
+#include "hal.h"
+
+/*
+ * @brief Fragment to turn execution into non-secure mode
+ */
+void go2ns(void) {
+ /* Configure SRAM0 as not secure Read and not secure write */
+ mtxConfigSlaveSec(MATRIX0,H64MX_SLAVE_SRAM, LOWER_AREA_SECURABLE,
+ NOT_SECURE_READ, NOT_SECURE_WRITE);
+ /* Configure SRAM1 upper area as not secure Read and secure write */
+ mtxConfigSlaveSec(MATRIX0, H64MX_SLAVE_L2C_SRAM, UPPER_AREA_SECURABLE,
+ NOT_SECURE_READ, SECURE_WRITE);
+ asm(
+ "mrc p15, 0, r0, c1, c1, 0\n\t" /* Set NS bit into SCR register */
+ "orr r0, r0, #1\n\t" /* bit 0 is the NS bit */
+ "mcr p15, 0, r0, c1, c1, 0\n\t"
+ );
+}
+/*
+ * Application entry point.
+ */
+int main(void) {
+ /* SRAM1 split at 64K */
+ mtxSetSlaveSplitAddr(MATRIX0, H64MX_SLAVE_L2C_SRAM, MATRIX_AREA_SIZE_64K,
+ REGION_0);
+
+ uint32_t *writeNotSecureSRAM1 = (uint32_t *)(0x220000 + 61 * 1024); /* Lower area region SRAM1 */
+ uint32_t *writeSecureSRAM1 = (uint32_t *)(0x220000 + 65 * 1024); /* Upper area region SRAM1 */
+ /* Go into Not Secure Mode*/
+ go2ns();
+ /* Writing in SRAM1 Lower Area */
+ *writeNotSecureSRAM1 = 0xAA55AA55; /* writing succeeded*/
+ /* Writing in SRAM1 Upper Area */
+ *writeSecureSRAM1 = 0xAA55AA55; /* writing not succeeded*/
+
+ while (true) {
+ ;
+ }
+}
|