avr/qmk/ChibiOS - [no description]

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author	gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>	2008-04-23 10:37:10 +0000
committer	gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>	2008-04-23 10:37:10 +0000
commit	0bc89b33d90203ab80056da972f5aa3ec762cd81 (patch)
tree	2af7ae2972d717083815aa1b2a94b53c2a6bf19a /src/chthreads.c
parent	25d517877dd7725e67c2d094031a023c41ec6f05 (diff)
download	ChibiOS-0bc89b33d90203ab80056da972f5aa3ec762cd81.tar.gz ChibiOS-0bc89b33d90203ab80056da972f5aa3ec762cd81.tar.bz2 ChibiOS-0bc89b33d90203ab80056da972f5aa3ec762cd81.zip

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@276 35acf78f-673a-0410-8e92-d51de3d6d3f4

Diffstat (limited to 'src/chthreads.c')

0 files changed, 0 insertions, 0 deletions

From 32bb743195e1e48c48fc5cefd7c6ecdce56046a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar> Date: Fri, 18 Jul 2014 15:58:44 -0300 Subject: [PATCH] ARM: sunxi: Add PLL2 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the PLL2 definition to the sun4i, sun5i and sun7i device trees. PLL2 is used to clock audio devices. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i.dtsi | 8 ++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -162,6 +162,14 @@ clock-output-names = "pll1"; }; + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -136,6 +136,14 @@ clock-output-names = "pll1"; }; + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -203,6 +203,14 @@ clock-output-names = "pll1"; }; + pll2: clk@01c20008 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-b-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk";


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