git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@142 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 10 insertions, 3 deletions

diff --git a/readme.txt b/readme.txt
index 18ba71eb5..f6692c623 100644
--- a/readme.txt
+++ b/readme.txt
@@ -43,13 +43,20 @@ AVR-AT90CANx-GCC       - Port on AVR AT90CAN128, not complete yet.
 - NEW: Binary Mutexes, the new mechanism provides a complete implementation

   of the "priority inheritance" algorithm as a tool for work around the

   priority inversion problem.

-  The Mutexes are not meant to replace the Semaphores that are still the best

-  mechanism for synchronization between interrupt handlers and high level

-  code, something Mutexes cannot do.

+  The Mutexes are not meant to replace the Semaphores that still are the best

+  synchronization mechanism between interrupt handlers and high level

+  code, something that Mutexes cannot do.

   Soon an article will be added to the wiki describing pro and cons of the

   various mechanisms and the correct use cases.

 - RT Semaphores subsystem removed, the Mutexes implements a better solution

   for the same problem.

+- Modified the test suite in order to have each test case to have the same

+  alignment enforced on functions. This is done to reduce MAM/Cache alignment

+  effects on the measurement.

+- IRQ entry/exit code is now encapsulated into two new macros, see chcore.h

+  for details.

+- Most of the asm code previously in chcore2.s is now inline asm code in

+  chcore.c (ARM port).

 

 *** 0.4.5 ***

 - Moved the serial IRQ handlers and VIC vectors initialization inside the