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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-03-13 20:53:08 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-03-13 20:53:08 +0000 |
| commit | 196ea509176fbb4f1341b9f7f1fbaed2ee286047 (patch) | |
| tree | 4da3641bd8c1df9c4ce9289931c68c04d6776cf5 /ports | |
| parent | b4357c2bf7e538ec6513892555c5cf0968b95efe (diff) | |
| download | ChibiOS-196ea509176fbb4f1341b9f7f1fbaed2ee286047.tar.gz ChibiOS-196ea509176fbb4f1341b9f7f1fbaed2ee286047.tar.bz2 ChibiOS-196ea509176fbb4f1341b9f7f1fbaed2ee286047.zip | |
Space optimization for Cortex-M3 port.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@844 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'ports')
| -rw-r--r-- | ports/ARMCM3/chcore.c | 12 | ||||
| -rw-r--r-- | ports/ARMCM3/chcore.h | 16 |
2 files changed, 28 insertions, 0 deletions
diff --git a/ports/ARMCM3/chcore.c b/ports/ARMCM3/chcore.c index b075ec27c..0159ee71f 100644 --- a/ports/ARMCM3/chcore.c +++ b/ports/ARMCM3/chcore.c @@ -42,6 +42,18 @@ void port_halt(void) { }
}
+#if !CH_OPTIMIZE_SPEED
+void _port_lock(void) {
+ register uint32_t tmp asm ("r3") = BASEPRI_KERNEL;
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp));
+}
+
+void _port_unlock(void) {
+ register uint32_t tmp asm ("r3") = BASEPRI_USER;
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp));
+}
+#endif
+
/**
* System Timer vector.
* This interrupt is used as system tick.
diff --git a/ports/ARMCM3/chcore.h b/ports/ARMCM3/chcore.h index 477e2fede..5ef44a09f 100644 --- a/ports/ARMCM3/chcore.h +++ b/ports/ARMCM3/chcore.h @@ -221,18 +221,30 @@ struct context { /**
* Raises the base priority to kernel level. */
+#if CH_OPTIMIZE_SPEED
#define port_lock() { \
register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
+#else
+#define port_lock() { \
+ asm volatile ("bl _port_lock" : : : "r3", "lr"); \
+}
+#endif
/**
* Lowers the base priority to user level.
*/
+#if CH_OPTIMIZE_SPEED
#define port_unlock() { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
+#else
+#define port_unlock() { \
+ asm volatile ("bl _port_unlock" : : : "r3", "lr"); \
+}
+#endif
/**
* Same as @p port_lock() in this port.
@@ -303,6 +315,10 @@ struct context { extern "C" {
#endif
void port_halt(void);
+#if !CH_OPTIMIZE_SPEED
+ void _port_lock(void);
+ void _port_unlock(void);
+#endif
#ifdef __cplusplus
}
#endif
|