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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2009-06-14 13:10:38 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2009-06-14 13:10:38 +0000
commit6ab7ea31f114af0e0d98494156d456279dd5ecd4 (patch)
treeeea62185afe26a8428a5d6b42c40910ec1e6aeba /ports/MSP430
parent03aef59589a44aec94456526a9e207c27149a750 (diff)
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PAL support for MSP430, various other fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1037 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'ports/MSP430')
-rw-r--r--ports/MSP430/pal_lld.h192
-rw-r--r--ports/MSP430/port.dox25
2 files changed, 207 insertions, 10 deletions
diff --git a/ports/MSP430/pal_lld.h b/ports/MSP430/pal_lld.h
new file mode 100644
index 000000000..cf8a8a62f
--- /dev/null
+++ b/ports/MSP430/pal_lld.h
@@ -0,0 +1,192 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ports/MSP430/pal_lld.h
+ * @brief MSP430 Digital I/O low level driver
+ * @addtogroup MSP430_PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#include <msp430x16x.h>
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic MSP430 I/O port.
+ */
+union __ioport {
+ struct {
+ ioregister_t in;
+ ioregister_t out;
+ ioregister_t dir;
+ } iop_common;
+ struct port_simple_t iop_simple;
+ struct port_full_t iop_full;
+};
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 8
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint8_t ioportmask_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef union __ioport * ioportid_t;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief I/O port A identifier.
+ * @details This port identifier is mapped on the MSP430 port 1 (P1).
+ */
+#if defined(__MSP430_HAS_PORT1__) || \
+ defined(__MSP430_HAS_PORT1_R__) || \
+ defined(__DOXYGEN__)
+#define IOPORT_A ((ioportid_t)0x0020)
+#endif
+
+/**
+ * @brief I/O port B identifier.
+ * @details This port identifier is mapped on the MSP430 port 2 (P2).
+ */
+#if defined(__MSP430_HAS_PORT2__) || \
+ defined(__MSP430_HAS_PORT2_R__) || \
+ defined(__DOXYGEN__)
+#define IOPORT_B ((ioportid_t)0x0028)
+#endif
+
+/**
+ * @brief I/O port C identifier.
+ * @details This port identifier is mapped on the MSP430 port 3 (P3).
+ */
+#if defined(__MSP430_HAS_PORT3__) || \
+ defined(__MSP430_HAS_PORT3_R__) || \
+ defined(__DOXYGEN__)
+#define IOPORT_C ((ioportid_t)0x0018)
+#endif
+
+/**
+ * @brief I/O port D identifier.
+ * @details This port identifier is mapped on the MSP430 port 4 (P4).
+ */
+#if defined(__MSP430_HAS_PORT4__) || \
+ defined(__MSP430_HAS_PORT4_R__) || \
+ defined(__DOXYGEN__)
+#define IOPORT_D ((ioportid_t)0x001c)
+#endif
+
+/**
+ * @brief I/O port E identifier.
+ * @details This port identifier is mapped on the MSP430 port 5 (P5).
+ */
+#if defined(__MSP430_HAS_PORT5__) || \
+ defined(__MSP430_HAS_PORT5_R__) || \
+ defined(__DOXYGEN__)
+#define IOPORT_E ((ioportid_t)0x0030)
+#endif
+
+/**
+ * @brief I/O port F identifier.
+ * @details This port identifier is mapped on the MSP430 port 6 (P6).
+ */
+#if defined(__MSP430_HAS_PORT6__) || \
+ defined(__MSP430_HAS_PORT6_R__) || \
+ defined(__DOXYGEN__)
+#define IOPORT_F ((ioportid_t)0x0034)
+#endif
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in a file named pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ */
+#define pal_lld_init()
+
+/**
+ * @brief Reads the physical I/O port states.
+ * @details This function is implemented by reading the PxIN register, the
+ * implementation has no side effects.
+ *
+ * @param[in] port the port identifier
+ * @return The port bits.
+ *
+ * @note This function is not meant to be invoked directly by the application
+ * code.
+ */
+#define pal_lld_readport(port) ((port)->iop_common.in.reg_p)
+
+/**
+ * @brief Reads the output latch.
+ * @details This function is implemented by reading the PxOUT register, the
+ * implementation has no side effects.
+ *
+ * @param[in] port the port identifier
+ * @return The latched logical states.
+ *
+ * @note This function is not meant to be invoked directly by the application
+ * code.
+ */
+#define pal_lld_readlatch(port) ((port)->iop_common.out.reg_p)
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ * @details This function is implemented by writing the PxOUT register, the
+ * implementation has no side effects.
+ *
+ * @param[in] port the port identifier
+ * @param[in] bits the bits to be written on the specified port
+ *
+ * @note This function is not meant to be invoked directly by the application
+ * code.
+ */
+#define pal_lld_writeport(port, bits) { \
+ (port)->iop_common.out.reg_p = (bits); \
+}
+
+/**
+ * @brief Set pins direction.
+ * @details This function programs the pins direction within a port.
+ */
+#define pal_lld_msp430_set_direction(port, dirmask) { \
+ (port)->iop_common.dir.reg_p = (dirmask); \
+}
+
+#endif /* _PAL_LLD_H_ */
+
+/** @} */
diff --git a/ports/MSP430/port.dox b/ports/MSP430/port.dox
index 8ea8efcda..6aa5c6c30 100644
--- a/ports/MSP430/port.dox
+++ b/ports/MSP430/port.dox
@@ -19,7 +19,6 @@
/**
* @defgroup MSP430 MSP430
- * @{
* @details MSP430 port details. This section how the ChibiOS/RT features are
* implemented on this architecture.
*
@@ -59,11 +58,9 @@
*
* @ingroup Ports
*/
-/** @} */
/**
* @defgroup MSP430_CONF Configuration Options
- * @{
* @brief MSP430 Configuration Options.
* @details The MSP430 port allows some architecture-specific configurations
* settings that can be specified externally, as example on the compiler
@@ -76,33 +73,41 @@
*
* @ingroup MSP430
*/
-/** @} */
/**
* @defgroup MSP430_CORE Core Port Implementation
- * @{
* @brief MSP430 specific port code, structures and macros.
*
* @ingroup MSP430
*/
-/** @} */
/**
* @defgroup MSP430_DRIVERS MSP430 Drivers
- * @{
* @brief Device drivers included in the MSP430 support.
*
* @ingroup MSP430
*/
-/** @} */
+
+/**
+ * @defgroup MSP430_PAL I/O Ports Support
+ * @brief I/O Ports peripherals support.
+ * @details This module supports the MSP430 Digital I/O controller. The
+ * controller supports the following features (see @ref PAL):
+ * - 8 bits wide ports.
+ * - Atomic set/reset/toggle functions because special MSP430 instruction set.
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * The only non atomic operations are bus/group writing.
+ *
+ * @ingroup MSP430_DRIVERS
+ */
/**
* @defgroup MSP430_SERIAL USART Support
- * @{
* @brief USART support.
* @details The serial driver supports both the MSP430 USARTs in asynchronous
* mode.
*
* @ingroup MSP430_DRIVERS
*/
-/** @} */