git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@201 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 404 insertions, 0 deletions

diff --git a/ports/ARM7/chcore.h b/ports/ARM7/chcore.h
new file mode 100644
index 000000000..2917428f3
--- /dev/null
+++ b/ports/ARM7/chcore.h
@@ -0,0 +1,132 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+#ifndef _CHCORE_H_

+#define _CHCORE_H_

+

+typedef void *regarm;

+

+/*

+ * Interrupt saved context.

+ */

+struct extctx {

+  regarm  spsr_irq;

+  regarm  lr_irq;

+  regarm  r0;

+  regarm  r1;

+  regarm  r2;

+  regarm  r3;

+  regarm  r12;

+};

+

+/*

+ * System saved context.

+ */

+struct intctx {

+  regarm  r4;

+  regarm  r5;

+  regarm  r6;

+#ifndef CH_CURRP_REGISTER_CACHE

+  regarm  r7;

+#endif

+  regarm  r8;

+  regarm  r9;

+  regarm  r10;

+  regarm  r11;

+  regarm  lr;

+};

+

+/*

+ * Port dependent part of the Thread structure, you may add fields in

+ * this structure.

+ */

+typedef struct {

+  struct intctx *r13;

+} Context;

+

+/*

+ * Platform dependent part of the \p chThdCreate() API.

+ */

+#define SETUP_CONTEXT(workspace, wsize, pf, arg) {                      \

+  tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace +                \

+                                     wsize -                            \

+                                     sizeof(struct intctx));            \

+  tp->p_ctx.r13->r4 = pf;                                               \

+  tp->p_ctx.r13->r5 = arg;                                              \

+  tp->p_ctx.r13->lr = threadstart;                                      \

+}

+

+#ifdef THUMB

+extern void chSysLock(void);

+extern void chSysUnlock(void);

+#else /* !THUMB */

+#define chSysLock() asm("msr     CPSR_c, #0x9F")

+#define chSysUnlock() asm("msr     CPSR_c, #0x1F")

+#endif /* THUMB */

+

+#ifdef THUMB

+#define INT_REQUIRED_STACK 0x10

+#else /* !THUMB */

+#define INT_REQUIRED_STACK 0

+#endif /* !THUMB */

+#define StackAlign(n) ((((n) - 1) | 3) + 1)

+#define UserStackSize(n) StackAlign(sizeof(Thread) +                    \

+                                    sizeof(struct intctx) +             \

+                                    sizeof(struct extctx) +             \

+                                    (n) +                               \

+                                    INT_REQUIRED_STACK)

+#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2];

+

+#ifdef THUMB

+#define chSysIRQEnterI() {                                              \

+  asm(".code 32                                 \n\t"                   \

+      "stmfd    sp!, {r0-r3, r12, lr}           \n\t"                   \

+      "add      r0, pc, #1                      \n\t"                   \

+      "bx       r0                              \n\t"                   \

+      ".code 16                                 \n\t");                 \

+}

+

+#define chSysIRQExitI() {                                               \

+  asm("ldr      r0, =IrqCommon                  \n\t"                   \

+      "bx       r0                              \n\t");                 \

+}

+#else /* !THUMB */

+#define chSysIRQEnterI() {                                              \

+  asm("stmfd    sp!, {r0-r3, r12, lr}           \n\t");                 \

+}

+

+#define chSysIRQExitI() {                                               \

+  asm("b        IrqCommon                       \n\t");                 \

+}

+#endif /* !THUMB */

+

+#ifdef THUMB

+#define chSysSwitchI chSysSwitchI_thumb

+#endif /* THUMB */

+

+/* It requires zero bytes, but better be safe.*/

+#define IDLE_THREAD_STACK_SIZE 8

+void _IdleThread(void *p) __attribute__((noreturn));

+

+void chSysHalt(void);

+void chSysSwitchI(Thread *otp, Thread *ntp);

+void chSysPuts(char *msg);

+void threadstart(void);

+

+#endif /* _CHCORE_H_ */

diff --git a/ports/ARM7/chsys.s b/ports/ARM7/chsys.s
new file mode 100644
index 000000000..770edaaec
--- /dev/null
+++ b/ports/ARM7/chsys.s
@@ -0,0 +1,225 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/*

+ * ARM7 port system code.

+ */

+

+#include <chconf.h>

+

+.set    MODE_USR, 0x10

+.set    MODE_FIQ, 0x11

+.set    MODE_IRQ, 0x12

+.set    MODE_SVC, 0x13

+.set    MODE_ABT, 0x17

+.set    MODE_UND, 0x1B

+.set    MODE_SYS, 0x1F

+

+.equ    I_BIT, 0x80

+.equ    F_BIT, 0x40

+

+.text

+

+/*

+ * Interrupt enable/disable functions, only present if there is THUMB code in

+ * the system because those are inlined in ARM code.

+ */

+#ifdef THUMB_PRESENT

+.balign 16

+.code 16

+.thumb_func

+.global chSysLock

+chSysLock:

+        mov     r0, pc

+        bx      r0

+.code 32

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        bx      lr

+

+.balign 16

+.code 16

+.thumb_func

+.global chSysUnlock

+chSysUnlock:

+        mov     r0, pc

+        bx      r0

+.code 32

+        msr     CPSR_c, #MODE_SYS

+        bx      lr

+#endif

+

+.balign 16

+#ifdef THUMB_PRESENT

+.code 16

+.thumb_func

+.global chSysSwitchI_thumb

+chSysSwitchI_thumb:

+        mov     r2, pc

+        bx      r2

+        // Jumps into chSysSwitchI in ARM mode

+#endif

+.code 32

+.global chSysSwitchI

+chSysSwitchI:

+#ifdef CH_CURRP_REGISTER_CACHE

+        stmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, lr}

+        str     sp, [r0, #16]

+        ldr     sp, [r1, #16]

+#ifdef THUMB_PRESENT

+        ldmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, lr}

+        bx      lr

+#else /* !THUMB_PRESENT */

+        ldmfd   sp!, {r4, r5, r6, r8, r9, r10, r11, pc}

+#endif /* !THUMB_PRESENT */

+#else /* !CH_CURRP_REGISTER_CACHE */

+        stmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}

+        str     sp, [r0, #16]

+        ldr     sp, [r1, #16]

+#ifdef THUMB_PRESENT

+        ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}

+        bx      lr

+#else /* !THUMB_PRESENT */

+        ldmfd   sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}

+#endif /* !THUMB_PRESENT */

+#endif /* !CH_CURRP_REGISTER_CACHE */

+

+/*

+ * Common exit point for all IRQ routines, it performs the rescheduling if

+ * required.

+ * System stack frame structure after a context switch in the

+ * interrupt handler:

+ *

+ * High +------------+

+ *      |   LR_USR   | -+

+ *      |     R12    |  |

+ *      |     R3     |  |

+ *      |     R2     |  | External context: IRQ handler frame

+ *      |     R1     |  |

+ *      |     R0     |  |

+ *      |   LR_IRQ   |  |   (user code return address)

+ *      |    SPSR    | -+   (user code status)

+ *      |    ....    | <- mk_DoRescheduleI() stack frame, optimize it for space

+ *      |     LR     | -+   (system code return address)

+ *      |     R11    |  |

+ *      |     R10    |  |

+ *      |     R9     |  |

+ *      |     R8     |  | Internal context: mk_SwitchI() frame

+ *      |    (R7)    |  |   (optional, see CH_CURRP_REGISTER_CACHE)

+ *      |     R6     |  |

+ *      |     R5     |  |

+ * SP-> |     R4     | -+

+ * Low  +------------+

+ */

+.balign 16

+#ifdef THUMB_NO_INTERWORKING

+.code 16

+.thumb_func

+.globl IrqCommon

+IrqCommon:

+        bl      chSchRescRequiredI

+        mov     lr, pc

+        bx      lr

+.code 32

+#else /* !THUMB_NO_INTERWORKING */

+.code 32

+.globl IrqCommon

+IrqCommon:

+        bl      chSchRescRequiredI

+#endif /* !THUMB_NO_INTERWORKING */

+        cmp     r0, #0                          // Simply returns if a

+        ldmeqfd sp!, {r0-r3, r12, lr}           // reschedule is not

+        subeqs  pc, lr, #4                      // required.

+

+        // Saves the IRQ mode registers in the system stack.

+        ldmfd   sp!, {r0-r3, r12, lr}           // IRQ stack now empty.

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        stmfd   sp!, {r0-r3, r12, lr}           // Registers on System Stack.

+        msr     CPSR_c, #MODE_IRQ | I_BIT

+        mrs     r0, SPSR

+        mov     r1, lr

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        stmfd   sp!, {r0, r1}                   // Push R0=SPSR, R1=LR_IRQ.

+

+        // Context switch.

+#ifdef THUMB_NO_INTERWORKING

+        add     r0, pc, #1

+        bx      r0

+.code 16

+        bl      chSchDoRescheduleI

+        mov     lr, pc

+        bx      lr

+.code 32

+#else /* !THUMB_NO_INTERWORKING */

+        bl      chSchDoRescheduleI

+#endif /* !THUMB_NO_INTERWORKING */

+

+        // Re-establish the IRQ conditions again.

+        ldmfd   sp!, {r0, r1}                   // Pop R0=SPSR, R1=LR_IRQ.

+        msr     CPSR_c, #MODE_IRQ | I_BIT

+        msr     SPSR_fsxc, r0

+        mov     lr, r1

+        msr     CPSR_c, #MODE_SYS | I_BIT

+        ldmfd   sp!, {r0-r3, r12, lr}

+        msr     CPSR_c, #MODE_IRQ | I_BIT

+        subs    pc, lr, #4

+

+/*

+ * Threads trampoline code.

+ * NOTE: The threads always start in ARM mode then switch to the thread-function mode.

+ */

+.balign 16

+.code 32

+.globl threadstart

+threadstart:

+        msr     CPSR_c, #MODE_SYS

+#ifndef THUMB_NO_INTERWORKING

+        mov     r0, r5

+        mov     lr, pc

+        bx      r4

+        bl      chThdExit

+#else /* !THUMB_NO_INTERWORKING */

+        add     r0, pc, #1

+        bx      r0

+.code 16

+        mov     r0, r5

+        bl      jmpr4

+        bl      chThdExit

+jmpr4:

+        bx      r4

+#endif /* !THUMB_NO_INTERWORKING */

+

+/*

+ * System stop code.

+ */

+.code 16

+.p2align 2,,

+.thumb_func

+.weak _halt16

+.globl _halt16

+_halt16:

+       mov      r0, pc

+       bx       r0

+.code 32

+.weak _halt32

+.globl _halt32

+_halt32:

+       mrs      r0, CPSR

+       orr      r0, #I_BIT | F_BIT

+       msr      CPSR_c, r0

+.loop: b        .loop

diff --git a/ports/ARM7/chtypes.h b/ports/ARM7/chtypes.h
new file mode 100644
index 000000000..2ac219148
--- /dev/null
+++ b/ports/ARM7/chtypes.h
@@ -0,0 +1,47 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+#ifndef _CHTYPES_H_

+#define _CHTYPES_H_

+

+/*

+ * Generic types often dependant on the compiler.

+ */

+#define BOOL        char

+#define BYTE8       unsigned char

+#define SBYTE8      char

+#define WORD16      short

+#define UWORD16     unsigned short

+#define LONG32      int

+#define ULONG32     unsigned int

+

+typedef BYTE8       t_tmode;

+typedef BYTE8       t_tstate;

+typedef UWORD16     t_tid;

+typedef ULONG32     t_prio;

+typedef LONG32      t_msg;

+typedef LONG32      t_eventid;

+typedef ULONG32     t_eventmask;

+typedef ULONG32     t_time;

+typedef LONG32      t_cnt;

+typedef ULONG32     t_size;

+

+#define INLINE      inline

+

+#endif /* _CHTYPES_H_ */