diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2008-02-06 14:41:28 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2008-02-06 14:41:28 +0000 |
| commit | 4fb21e032efb6898b89328daa3d6e4c0d4b6bbef (patch) | |
| tree | 3a9f2a170bc4302c37b39a6f91a58a9406ebd196 /ports/ARM7-AT91SAM7X | |
| parent | eb82df9b16865867b0e053d4e240acde0c4bdee2 (diff) | |
| download | ChibiOS-4fb21e032efb6898b89328daa3d6e4c0d4b6bbef.tar.gz ChibiOS-4fb21e032efb6898b89328daa3d6e4c0d4b6bbef.tar.bz2 ChibiOS-4fb21e032efb6898b89328daa3d6e4c0d4b6bbef.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@190 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'ports/ARM7-AT91SAM7X')
| -rw-r--r-- | ports/ARM7-AT91SAM7X/GCC/chcore.c | 235 | ||||
| -rw-r--r-- | ports/ARM7-AT91SAM7X/GCC/chcore.h | 129 | ||||
| -rw-r--r-- | ports/ARM7-AT91SAM7X/GCC/chtypes.h | 47 | ||||
| -rw-r--r-- | ports/ARM7-AT91SAM7X/GCC/crt0.s | 178 |
4 files changed, 589 insertions, 0 deletions
diff --git a/ports/ARM7-AT91SAM7X/GCC/chcore.c b/ports/ARM7-AT91SAM7X/GCC/chcore.c new file mode 100644 index 000000000..795fcd792 --- /dev/null +++ b/ports/ARM7-AT91SAM7X/GCC/chcore.c @@ -0,0 +1,235 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <ch.h>
+
+#include "at91lib/AT91SAM7X256.h"
+
+/*
+ * System idle thread loop.
+ */
+void _IdleThread(void *p) {
+
+ while (TRUE) {
+// Note, it is disabled because it causes trouble with the JTAG probe.
+// Enable it in the final code only.
+// PCON = 1;
+ }
+}
+
+/*
+ * The following functions are present only if there is in the system any
+ * code compiled as THUMB that may invoke them.
+ * NOTE: The undefs are there in case this module is compiled in ARM mode but
+ * there are THUMB modules in the system.
+ */
+#ifdef THUMB_PRESENT
+#undef chSysLock
+void chSysLock(void) {
+
+#ifdef THUMB
+ asm(".p2align 2,, \n\t" \
+ "mov r0, pc \n\t" \
+ "bx r0 \n\t" \
+ ".code 32 \n\t");
+#endif
+
+ asm("msr CPSR_c, #0x9F \n\t" \
+ "bx lr \n\t");
+}
+
+#undef chSysUnlock
+void chSysUnlock(void) {
+
+#ifdef THUMB
+ asm(".p2align 2,, \n\t" \
+ "mov r0, pc \n\t" \
+ "bx r0 \n\t" \
+ ".code 32 \n\t");
+#endif
+
+ asm("msr CPSR_c, #0x1F \n\t" \
+ "bx lr \n\t");
+}
+#endif
+
+void chSysSwitchI(Thread *otp, Thread *ntp) {
+
+#ifdef THUMB
+ asm(".p2align 2,, \n\t" \
+ "mov r2, pc \n\t" \
+ "bx r2 \n\t" \
+ ".code 32 \n\t");
+#endif
+
+#ifdef CH_CURRP_REGISTER_CACHE
+ asm("stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} \n\t" \
+ "str sp, [r0, #16] \n\t" \
+ "ldr sp, [r1, #16] \n\t");
+#ifdef THUMB_PRESENT
+ asm("ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} \n\t" \
+ "bx lr \n\t");
+#else /* !THUMB_PRESENT */
+ asm("ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} \n\t");
+#endif /* !THUMB_PRESENT */
+#else /* !CH_CURRP_REGISTER_CACHE */
+ asm("stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} \n\t" \
+ "str sp, [r0, #16] \n\t" \
+ "ldr sp, [r1, #16] \n\t");
+#ifdef THUMB_PRESENT
+ asm("ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} \n\t" \
+ "bx lr \n\t");
+#else /* !THUMB_PRESENT */
+ asm("ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} \n\t");
+#endif /* !THUMB_PRESENT */
+#endif /* !CH_CURRP_REGISTER_CACHE */
+}
+
+/*
+ * System console message (not implemented).
+ */
+void chSysPuts(char *msg) {
+}
+
+/*
+ * Common IRQ exit code, \p chSysIRQExitI() just jumps here.
+ *
+ * System stack frame structure after a context switch in the
+ * interrupt handler:
+ *
+ * High +------------+
+ * | LR_USR | -+
+ * | R12 | |
+ * | R3 | |
+ * | R2 | | External context: IRQ handler frame
+ * | R1 | |
+ * | R0 | |
+ * | LR_IRQ | | (user code return address)
+ * | SPSR | -+ (user code status)
+ * | .... | <- chSchDoRescheduleI() stack frame, optimize it for space
+ * | LR | -+ (system code return address)
+ * | R11 | |
+ * | R10 | |
+ * | R9 | |
+ * | R8 | | Internal context: chSysSwitchI() frame
+ * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
+ * | R6 | |
+ * | R5 | |
+ * SP-> | R4 | -+
+ * Low +------------+
+ */
+__attribute__((naked, weak))
+void IrqCommon(void) {
+ register BOOL b asm("r0");
+
+// VICVectAddr = 0;
+ b = chSchRescRequiredI();
+#ifdef THUMB
+ asm(".p2align 2,, \n\t" \
+ "mov lr, pc \n\t" \
+ "bx lr \n\t" \
+ ".code 32 \n\t");
+#endif
+ /*
+ * If a reschedulation is not required then just returns from the IRQ.
+ */
+ asm("cmp r0, #0 \n\t" \
+ "ldmeqfd sp!, {r0-r3, r12, lr} \n\t" \
+ "subeqs pc, lr, #4 \n\t");
+ /*
+ * Reschedulation required, saves the external context on the
+ * system/user stack and empties the IRQ stack.
+ */
+ asm(".set MODE_IRQ, 0x12 \n\t" \
+ ".set MODE_SYS, 0x1F \n\t" \
+ ".set F_BIT, 0x40 \n\t" \
+ ".set I_BIT, 0x80 \n\t" \
+ "ldmfd sp!, {r0-r3, r12, lr} \n\t" \
+ "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
+ "stmfd sp!, {r0-r3, r12, lr} \n\t" \
+ "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
+ "mrs r0, SPSR \n\t" \
+ "mov r1, lr \n\t" \
+ "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
+ "stmfd sp!, {r0, r1} \n\t");
+
+#ifdef THUMB_NO_INTERWORKING
+ asm("add r0, pc, #1 \n\t" \
+ "bx r0 \n\t" \
+ ".code 16 \n\t" \
+ "bl chSchDoRescheduleI \n\t" \
+ ".p2align 2,, \n\t" \
+ "mov lr, pc \n\t" \
+ "bx lr \n\t" \
+ ".code 32 \n\t");
+#else
+ asm("bl chSchDoRescheduleI \n\t");
+#endif
+
+ /*
+ * Restores the external context.
+ */
+ asm("ldmfd sp!, {r0, r1} \n\t" \
+ "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
+ "msr SPSR_fsxc, r0 \n\t" \
+ "mov lr, r1 \n\t" \
+ "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \
+ "ldmfd sp!, {r0-r3, r12, lr} \n\t" \
+ "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \
+ "subs pc, lr, #4 \n\t");
+
+ /*
+ * Threads entry/exit code. It is declared weak so you can easily replace it.
+ * NOTE: It is always invoked in ARM mode, it does the mode switching.
+ * NOTE: It is included into IrqCommon to make sure the symbol refers to
+ * 32 bit code.
+ */
+ asm(".weak threadstart \n\t" \
+ ".globl threadstart \n\t" \
+ "threadstart: \n\t" \
+ "msr CPSR_c, #MODE_SYS \n\t");
+#ifndef THUMB_NO_INTERWORKING
+ asm("mov r0, r5 \n\t" \
+ "mov lr, pc \n\t" \
+ "bx r4 \n\t" \
+ "bl chThdExit \n\t");
+#else
+ asm("add r0, pc, #1 \n\t" \
+ "bx r0 \n\t" \
+ ".code 16 \n\t" \
+ "mov r0, r5 \n\t" \
+ "bl jmpr4 \n\t" \
+ "bl chThdExit \n\t" \
+ "jmpr4: \n\t" \
+ "bx r4 \n\t");
+#endif
+}
+
+/*
+ * System halt.
+ */
+__attribute__((naked, weak))
+void chSysHalt(void) {
+
+#ifdef THUMB
+ asm("ldr r0, =_halt32 \n\t" \
+ "bx r0 \n\t");
+#endif
+ asm("b _halt32 \n\t");
+}
diff --git a/ports/ARM7-AT91SAM7X/GCC/chcore.h b/ports/ARM7-AT91SAM7X/GCC/chcore.h new file mode 100644 index 000000000..75392b6b9 --- /dev/null +++ b/ports/ARM7-AT91SAM7X/GCC/chcore.h @@ -0,0 +1,129 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _CHCORE_H_
+#define _CHCORE_H_
+
+typedef void *regarm;
+
+/*
+ * Interrupt saved context.
+ */
+struct extctx {
+ regarm spsr_irq;
+ regarm lr_irq;
+ regarm r0;
+ regarm r1;
+ regarm r2;
+ regarm r3;
+ regarm r12;
+};
+
+/*
+ * System saved context.
+ */
+struct intctx {
+ regarm r4;
+ regarm r5;
+ regarm r6;
+#ifndef CH_CURRP_REGISTER_CACHE
+ regarm r7;
+#endif
+ regarm r8;
+ regarm r9;
+ regarm r10;
+ regarm r11;
+ regarm lr;
+};
+
+/*
+ * Port dependent part of the Thread structure, you may add fields in
+ * this structure.
+ */
+typedef struct {
+ struct intctx *r13;
+} Context;
+
+/*
+ * Platform dependent part of the \p chThdCreate() API.
+ */
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \
+ wsize - \
+ sizeof(struct intctx)); \
+ tp->p_ctx.r13->r4 = pf; \
+ tp->p_ctx.r13->r5 = arg; \
+ tp->p_ctx.r13->lr = threadstart; \
+}
+
+#ifdef THUMB
+extern void chSysLock(void);
+extern void chSysUnlock(void);
+#else /* !THUMB */
+#define chSysLock() asm("msr CPSR_c, #0x9F")
+#define chSysUnlock() asm("msr CPSR_c, #0x1F")
+#endif /* THUMB */
+
+#ifdef THUMB
+#define INT_REQUIRED_STACK 0x10
+#else /* !THUMB */
+#define INT_REQUIRED_STACK 0
+#endif /* !THUMB */
+#define StackAlign(n) ((((n) - 1) | 3) + 1)
+#define UserStackSize(n) StackAlign(sizeof(Thread) + \
+ sizeof(struct intctx) + \
+ sizeof(struct extctx) + \
+ (n) + \
+ INT_REQUIRED_STACK)
+#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2];
+
+#ifdef THUMB
+#define chSysIRQEnterI() { \
+ asm(".code 32 \n\t" \
+ "stmfd sp!, {r0-r3, r12, lr} \n\t" \
+ "add r0, pc, #1 \n\t" \
+ "bx r0 \n\t" \
+ ".code 16 \n\t"); \
+}
+
+#define chSysIRQExitI() { \
+ VICVectAddr = 0; \
+ asm("ldr r0, =IrqCommon \n\t" \
+ "bx r0 \n\t"); \
+}
+#else /* !THUMB */
+#define chSysIRQEnterI() { \
+ asm("stmfd sp!, {r0-r3, r12, lr} \n\t"); \
+}
+
+#define chSysIRQExitI() { \
+ asm("b IrqCommon \n\t"); \
+}
+#endif /* !THUMB */
+
+/* It requires zero bytes, but better be safe.*/
+#define IDLE_THREAD_STACK_SIZE 8
+void _IdleThread(void *p) __attribute__((noreturn));
+
+void chSysHalt(void);
+void chSysSwitchI(Thread *otp, Thread *ntp);
+void chSysPuts(char *msg);
+void threadstart(void);
+
+#endif /* _CHCORE_H_ */
diff --git a/ports/ARM7-AT91SAM7X/GCC/chtypes.h b/ports/ARM7-AT91SAM7X/GCC/chtypes.h new file mode 100644 index 000000000..2ac219148 --- /dev/null +++ b/ports/ARM7-AT91SAM7X/GCC/chtypes.h @@ -0,0 +1,47 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _CHTYPES_H_
+#define _CHTYPES_H_
+
+/*
+ * Generic types often dependant on the compiler.
+ */
+#define BOOL char
+#define BYTE8 unsigned char
+#define SBYTE8 char
+#define WORD16 short
+#define UWORD16 unsigned short
+#define LONG32 int
+#define ULONG32 unsigned int
+
+typedef BYTE8 t_tmode;
+typedef BYTE8 t_tstate;
+typedef UWORD16 t_tid;
+typedef ULONG32 t_prio;
+typedef LONG32 t_msg;
+typedef LONG32 t_eventid;
+typedef ULONG32 t_eventmask;
+typedef ULONG32 t_time;
+typedef LONG32 t_cnt;
+typedef ULONG32 t_size;
+
+#define INLINE inline
+
+#endif /* _CHTYPES_H_ */
diff --git a/ports/ARM7-AT91SAM7X/GCC/crt0.s b/ports/ARM7-AT91SAM7X/GCC/crt0.s new file mode 100644 index 000000000..d501770c8 --- /dev/null +++ b/ports/ARM7-AT91SAM7X/GCC/crt0.s @@ -0,0 +1,178 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * Generic ARM startup file for ChibiOS/RT.
+ */
+
+.extern _main
+
+.set MODE_USR, 0x10
+.set MODE_FIQ, 0x11
+.set MODE_IRQ, 0x12
+.set MODE_SVC, 0x13
+.set MODE_ABT, 0x17
+.set MODE_UND, 0x1B
+.set MODE_SYS, 0x1F
+
+.equ I_BIT, 0x80
+.equ F_BIT, 0x40
+
+.text
+.code 32
+.balign 4
+/*
+ * System entry points.
+ */
+_start:
+ b ResetHandler
+ ldr pc, _undefined
+ ldr pc, _swi
+ ldr pc, _prefetch
+ ldr pc, _abort
+ nop
+ ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */
+ ldr pc, _fiq
+
+_undefined:
+ .word UndHandler
+_swi:
+ .word SwiHandler
+_prefetch:
+ .word PrefetchHandler
+_abort:
+ .word AbortHandler
+_fiq:
+ .word FiqHandler
+ .word 0
+ .word 0
+ .word 0
+
+/*
+ * Reset handler.
+ */
+ResetHandler:
+ /*
+ * Stack pointers initialization.
+ */
+ ldr r0, =__ram_end__
+ /* Undefined */
+ msr CPSR_c, #MODE_UND | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__und_stack_size__
+ sub r0, r0, r1
+ /* Abort */
+ msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__abt_stack_size__
+ sub r0, r0, r1
+ /* FIQ */
+ msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__fiq_stack_size__
+ sub r0, r0, r1
+ /* IRQ */
+ msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__irq_stack_size__
+ sub r0, r0, r1
+ /* Supervisor */
+ msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
+ mov sp, r0
+ ldr r1, =__svc_stack_size__
+ sub r0, r0, r1
+ /* System */
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ mov sp, r0
+// ldr r1, =__sys_stack_size__
+// sub r0, r0, r1
+ /*
+ * Data initialization.
+ * NOTE: It assumes that the DATA size is a multiple of 4.
+ */
+ ldr r1, =_textdata
+ ldr r2, =_data
+ ldr r3, =_edata
+dataloop:
+ cmp r2, r3
+ ldrlo r0, [r1], #4
+ strlo r0, [r2], #4
+ blo dataloop
+ /*
+ * BSS initialization.
+ * NOTE: It assumes that the BSS size is a multiple of 4.
+ */
+ mov r0, #0
+ ldr r1, =_bss_start
+ ldr r2, =_bss_end
+bssloop:
+ cmp r1, r2
+ strlo r0, [r1], #4
+ blo bssloop
+ /*
+ * Application-provided HW initialization routine.
+ */
+#ifndef THUMB_NO_INTERWORKING
+ bl hwinit
+ /*
+ * main(0, NULL).
+ */
+ mov r0, #0
+ mov r1, r0
+ bl main
+ bl chSysHalt
+#else
+ add r0, pc, #1
+ bx r0
+.code 16
+ bl hwinit
+ mov r0, #0
+ mov r1, r0
+ bl main
+ bl chSysHalt
+.code 32
+#endif
+
+.weak UndHandler
+.globl UndHandler
+UndHandler:
+
+.weak SwiHandler
+.globl SwiHandler
+SwiHandler:
+
+.weak PrefetchHandler
+.globl PrefetchHandler
+PrefetchHandler:
+
+.weak AbortHandler
+.globl AbortHandler
+AbortHandler:
+
+.weak FiqHandler
+.globl FiqHandler
+FiqHandler:
+
+.weak _halt32
+.globl _halt32
+_halt32:
+ mrs r0, CPSR
+ orr r0, #I_BIT | F_BIT
+ msr CPSR_c, r0
+.loop: b .loop
|