git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8301 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 46 insertions, 43 deletions

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
index ffed12231..a71b6ccd6 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
@@ -109,6 +109,27 @@ SECTIONS
     _etext = .;

     _textdata = _etext;

 

+    /* Special section for exceptions stack.*/

+    .mstack :

+    {

+        . = ALIGN(8);

+        __main_stack_base__ = .;

+        . += __main_stack_size__;

+        . = ALIGN(8);

+        __main_stack_end__ = .;

+    } > MAIN_STACK_RAM

+

+    /* Special section for process stack.*/

+    .pstack :

+    {

+        __process_stack_base__ = .;

+        __main_thread_stack_base__ = .;

+        . += __process_stack_size__;

+        . = ALIGN(8);

+        __process_stack_end__ = .;

+        __main_thread_stack_end__ = .;

+    } > PROCESS_STACK_RAM

+

     /* Special section for non cache-able areas.*/

     .nocache (NOLOAD) : ALIGN(4)

     {

@@ -131,25 +152,6 @@ SECTIONS
         __eth_end__ = .;

     } > ETH_RAM

 

-    .mstack :

-    {

-        . = ALIGN(8);

-        __main_stack_base__ = .;

-        . += __main_stack_size__;

-        . = ALIGN(8);

-        __main_stack_end__ = .;

-    } > MAIN_STACK_RAM

-

-    .pstack :

-    {

-        __process_stack_base__ = .;

-        __main_thread_stack_base__ = .;

-        . += __process_stack_size__;

-        . = ALIGN(8);

-        __process_stack_end__ = .;

-        __main_thread_stack_end__ = .;

-    } > PROCESS_STACK_RAM

-

     .data : ALIGN(4)

     {

         . = ALIGN(4);

diff --git a/os/hal/include/mii.h b/os/hal/include/mii.h
index 395081203..e7e59a343 100644
--- a/os/hal/include/mii.h
+++ b/os/hal/include/mii.h
@@ -146,13 +146,14 @@
 /*

  * PHY identifiers.

  */

-#define MII_DM9161_ID     0x0181b8a0

-#define MII_AM79C875_ID   0x00225540

-#define MII_KS8721_ID     0x00221610

-#define MII_STE101P_ID    0x00061C50

-#define MII_DP83848I_ID   0x20005C90

-#define MII_LAN8710A_ID   0x0007C0F1

-#define MII_LAN8720_ID    0x0007C0F0

+#define MII_DM9161_ID           0x0181b8a0

+#define MII_AM79C875_ID         0x00225540

+#define MII_KS8721_ID           0x00221610

+#define MII_STE101P_ID          0x00061C50

+#define MII_DP83848I_ID         0x20005C90

+#define MII_LAN8710A_ID         0x0007C0F1

+#define MII_LAN8720_ID          0x0007C0F0

+#define MII_LAN8742A_ID         0x0007C130

 

 #endif /* _MII_H_ */

 

diff --git a/os/hal/ports/STM32/LLD/MACv1/mac_lld.c b/os/hal/ports/STM32/LLD/MACv1/mac_lld.c
index 3679d33dd..de3fdba54 100644
--- a/os/hal/ports/STM32/LLD/MACv1/mac_lld.c
+++ b/os/hal/ports/STM32/LLD/MACv1/mac_lld.c
@@ -67,11 +67,11 @@ MACDriver ETHD1;
 static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,

                                               0x37, 0x01, 0x10};

 

-static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS];

-static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS];

+static stm32_eth_rx_descriptor_t __eth_rd[STM32_MAC_RECEIVE_BUFFERS];

+static stm32_eth_tx_descriptor_t __eth_td[STM32_MAC_TRANSMIT_BUFFERS];

 

-static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];

-static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];

+static uint32_t __eth_rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];

+static uint32_t __eth_tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];

 

 /*===========================================================================*/

 /* Driver local functions.                                                   */

@@ -219,14 +219,14 @@ void mac_lld_init(void) {
   /* Descriptor tables are initialized in chained mode, note that the first

      word is not initialized here but in mac_lld_start().*/

   for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) {

-    rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE;

-    rd[i].rdes2 = (uint32_t)rb[i];

-    rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS];

+    __eth_rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE;

+    __eth_rd[i].rdes2 = (uint32_t)__eth_rb[i];

+    __eth_rd[i].rdes3 = (uint32_t)&__eth_rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS];

   }

   for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) {

-    td[i].tdes1 = 0;

-    td[i].tdes2 = (uint32_t)tb[i];

-    td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS];

+    __eth_td[i].tdes1 = 0;

+    __eth_td[i].tdes2 = (uint32_t)__eth_tb[i];

+    __eth_td[i].tdes3 = (uint32_t)&__eth_td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS];

   }

 

   /* Selection of the RMII or MII mode based on info exported by board.h.*/

@@ -236,7 +236,7 @@ void mac_lld_init(void) {
 #else

   AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL;

 #endif

-#elif defined(STM32F2XX) || defined(STM32F4XX)

+#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)

 #if defined(BOARD_PHY_RMII)

   SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;

 #else

@@ -293,11 +293,11 @@ void mac_lld_start(MACDriver *macp) {
 

   /* Resets the state of all descriptors.*/

   for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++)

-    rd[i].rdes0 = STM32_RDES0_OWN;

-  macp->rxptr = (stm32_eth_rx_descriptor_t *)rd;

+    __eth_rd[i].rdes0 = STM32_RDES0_OWN;

+  macp->rxptr = (stm32_eth_rx_descriptor_t *)__eth_rd;

   for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++)

-    td[i].tdes0 = STM32_TDES0_TCH;

-  macp->txptr = (stm32_eth_tx_descriptor_t *)td;

+    __eth_td[i].tdes0 = STM32_TDES0_TCH;

+  macp->txptr = (stm32_eth_tx_descriptor_t *)__eth_td;

 

   /* MAC clocks activation and commanded reset procedure.*/

   rccEnableETH(false);

@@ -337,8 +337,8 @@ void mac_lld_start(MACDriver *macp) {
 

   /* DMA configuration:

      Descriptor chains pointers.*/

-  ETH->DMARDLAR = (uint32_t)rd;

-  ETH->DMATDLAR = (uint32_t)td;

+  ETH->DMARDLAR = (uint32_t)__eth_rd;

+  ETH->DMATDLAR = (uint32_t)__eth_td;

 

   /* Enabling required interrupt sources.*/

   ETH->DMASR    = ETH->DMASR;